coreboot-gerrit November 2024

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85037?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings Configure GPIOs according to schematics_20241107B. BUG=b:377819511 TEST=emerge-nissa coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 5 files changed, 466 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85037?usp=email ) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings Configure GPIOs according to schematics_20241107B. BUG=b:377819511 TEST=emerge-nissa coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 5 files changed, 466 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index bc68972..825d77e 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -53,7 +53,6 @@ config BOARD_GOOGLE_MODEL_FATCAT def_bool n select BOARD_GOOGLE_BASEBOARD_FATCAT - select DRIVERS_GENERIC_MAX98357A config BOARD_GOOGLE_FATCAT select BOARD_GOOGLE_MODEL_FATCAT @@ -67,7 +66,7 @@ select BOARD_GOOGLE_MODEL_FATCAT config BOARD_GOOGLE_FRANCKA - select BOARD_GOOGLE_MODEL_FATCAT + select BOARD_GOOGLE_BASEBOARD_FATCAT if BOARD_GOOGLE_FATCAT_COMMON @@ -144,6 +143,7 @@ config VARIANT_DIR string default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT + default "francka" if BOARD_GOOGLE_FRANCKA config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index 3f94c03..5358721 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -19,8 +19,8 @@ #define EC_SYNC_IRQ 0 /* Not Connected */ #define GPIO_PCH_WP GPP_D02 #elif CONFIG(BOARD_GOOGLE_FRANCKA) - #define EC_SYNC_IRQ 0 /* TODO */ - #define GPIO_PCH_WP 0 /* TODO */ + #define EC_SYNC_IRQ GPP_B05_IRQ + #define GPIO_PCH_WP GPP_E22 #endif #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/fatcat/variants/francka/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/Makefile.mk new file mode 100644 index 0000000..a49954c --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/Makefile.mk @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/fatcat/variants/francka/gpio.c b/src/mainboard/google/fatcat/variants/francka/gpio.c new file mode 100644 index 0000000..9ac2975 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/gpio.c @@ -0,0 +1,451 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <soc/gpio.h> + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* GPP_A00: ESPI_IO0_EC_R */ + /* GPP_A00 : GPP_A00 ==> ESPI_IO0_EC_R configured on reset, do not touch */ + + /* GPP_A01: ESPI_IO1_EC_R */ + /* GPP_A01 : GPP_A01 ==> ESPI_IO1_EC_R configured on reset, do not touch */ + + /* GPP_A02: ESPI_IO2_EC_R */ + /* GPP_A02 : GPP_A02 ==> ESPI_IO2_EC_R configured on reset, do not touch */ + + /* GPP_A03: ESPI_IO3_EC_R */ + /* GPP_A03 : GPP_A03 ==> ESPI_IO3_EC_R configured on reset, do not touch */ + + /* GPP_A04: ESPI_CS0_EC_R_N */ + /* GPP_A04 : GPP_A04 ==> ESPI_CS0_HDR_L configured on reset, do not touch */ + + /* GPP_A05: ESPI_CLK_EC_R */ + /* GPP_A05 : GPP_A05 ==> ESPI_CLK_HDR configured on reset, do not touch */ + + /* GPP_A06: ESPI_RST_EC_R_N */ + /* GPP_A06 : GPP_A06 ==> ESPI_RST_HDR configured on reset, do not touch */ + + /* GPP_A08: SOC_SD_PWR_EN */ + PAD_CFG_GPO(GPP_A08, 1, PLTRST), + /* GPP_A09: SOC_WWAN_OFF#_SW */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), + /* GPP_A10: SOC_WWAN_RA_DIS#_SW */ + PAD_CFG_GPO(GPP_A10, 1, PLTRST), + /* GPP_A11: SOC_WLAN_RST# */ + PAD_CFG_GPO(GPP_A11, 1, PLTRST), + /* GPP_A12: SOC_WL_WAKE# */ + PAD_CFG_GPI_SCI_LOW(GPP_A12, NONE, DEEP, LEVEL), + /* GPP_A13: Not used */ + PAD_NC(GPP_A13, NONE), + /* GPP_A15: Not used */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16: SOC_BT_ON */ + PAD_CFG_GPO(GPP_A16, 1, DEEP), + /* GPP_A17: SOC_WL_OFF# */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + + /* GPP_B00: SOC_USBC_SMLCLK */ + PAD_CFG_NF(GPP_B00, NONE, DEEP, NF1), + /* GPP_B01: SOC_USBC_SMLDATA */ + PAD_CFG_NF(GPP_B01, NONE, DEEP, NF1), + /* GPP_B02: ISH_I2C_0_SDA */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B02, NONE, DEEP, NF3), + /* GPP_B03: ISH_I2C_0_SCL */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_B03, NONE, DEEP, NF3), + /* GPP_B04: Not used */ + PAD_NC(GPP_B04, NONE), + /* GPP_B05: ISH_GP_1_SNSR_HDR */ + PAD_CFG_GPI_APIC(GPP_B05, NONE, PLTRST, LEVEL, INVERT), + /* GPP_B06: SOC_SSD1_RST# */ + PAD_CFG_GPO(GPP_B06, 1, PLTRST), + /* GPP_B07: SOC_CODEC_RST# */ + PAD_NC(GPP_B07, NONE), + /* GPP_B08: SOC_TP_RST#1 */ + PAD_CFG_GPO(GPP_B08, 1, PLTRST), + /* GPP_B09: SOC_TCP0_DP_HPD# */ + PAD_CFG_NF(GPP_B09, NONE, DEEP, NF2), + /* GPP_B10: SOC_TCP1_DP_HPD# */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2), + /* GPP_B11: SOC_RTS_P0_P1_OC# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12: PM_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13: SOC_PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14: Not used */ + PAD_NC(GPP_B14, NONE), + /* GPP_B15: Not used */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16: SOC_SSD2_EN */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + /* GPP_B17: SOC_ENVDD2 */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF2), + /* GPP_B18: TCHSCR_REPORT_DISABLE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* GPP_B19: SOC_CNVI_EN# */ + PAD_CFG_GPO(GPP_B19, 0, PLTRST), + /* GPP_B20: SOC_WWAN_RST# */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + /* GPP_B21: SOC_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + /* GPP_B22: SEN_MODE_EC_PCH_INT_OD# */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), + /* GPP_B23: Not used */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24: Not used */ + PAD_NC(GPP_B24, NONE), + /* GPP_B25: SOC_SD_WAKE# */ + PAD_CFG_GPI(GPP_B25, NONE, DEEP), + + /* GPP_C00: SOC_SMBCLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SOC_SMBDATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), + /* GPP_C02: Not used */ + PAD_NC(GPP_C02, NONE), + /* GPP_C03: SOC_SML0CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04: SOC_SML0DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05: Not used */ + PAD_NC(GPP_C05, NONE), + /* GPP_C06: Not used */ + PAD_NC(GPP_C06, NONE), + /* GPP_C07: Not used */ + PAD_NC(GPP_C07, NONE), + /* GPP_C08: Not used */ + PAD_NC(GPP_C08, NONE), + /* GPP_C09: CLKREQ_PCIE#0 */ + PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), + /* GPP_C10: CLKREQ_PCIE#1 */ + PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), + /* GPP_C11: CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12: Not used */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13: CLKREQ_PCIE#4 */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* GPP_C14: CLKREQ_PCIE#5 */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* GPP_C15: Not used */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16: TBT_0_LSX_TX */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17: TBT_0_LSX_RX */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18: TBT_1_LSX_TX */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* GPP_C19: TBT_2_LSX_RX */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* GPP_C20: TBT_2_LSX_TX */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* GPP_C21: TBT_2_LSX_RX */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* GPP_C22: TBT_3_LSX_TX */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* GPP_C23: TBT_3_LSX_RX */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + + /* GPP_D00: SOC_SD_PRSNT# */ + PAD_CFG_GPO(GPP_D00, 1, PLTRST), + /* GPP_D01: Not used */ + PAD_NC(GPP_D01, NONE), + /* GPP_D02: Not used */ + PAD_NC(GPP_D02, NONE), + /* GPP_D03: SOC_WWAN_PCIE_RST# */ + PAD_CFG_GPO(GPP_D03, 1, PLTRST), + /* GPP_D04: IPCM_SLOW */ + PAD_CFG_GPO(GPP_D04, 1, PLTRST), + /* GPP_D05: SOC_SSD1_EN */ + PAD_CFG_GPO(GPP_D05, 1, PLTRST), + /* GPP_D06: Not used */ + PAD_NC(GPP_D06, NONE), + /* GPP_D07: DDR_STRAP_2 */ + PAD_CFG_GPI(GPP_D07, NONE, DEEP), + /* GPP_D08: DDR_STRAP_1 */ + PAD_CFG_GPI(GPP_D08, NONE, DEEP), + /* GPP_D09: PCH_DGPU_HOLD_RST#_R */ + PAD_NC(GPP_D09, NONE), + /* GPP_D10: HDA_BIT_CLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11: HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF1), + /* GPP_D12: HDA_SDOUT */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF1), + /* GPP_D13: HDA_SDIN0 */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* GPP_D14: SOC_HDMI_STRAP */ + PAD_CFG_GPI(GPP_D14, NONE, DEEP), + /* GPP_D15: Not used */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16: HDA_RST# */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17: FPMCU_INT# */ + PAD_CFG_GPI_INT(GPP_D17, NONE, PLTRST, LEVEL), + /* GPP_D18: CLKREQ_PCIE#6 */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D19: SOC_SD_RST# */ + PAD_CFG_GPO(GPP_D19, 1, PLTRST), + /* GPP_D20: CSE_EARLY_SW */ + PAD_CFG_GPI_SCI_HIGH(GPP_D20, NONE, DEEP, LEVEL), + /* GPP_D21: Not used */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22: SOC_I3C_BPK_SDA */ + PAD_CFG_NF(GPP_D22, NONE, DEEP, NF2), + /* GPP_D23: SOC_I3C_BPK_SCL */ + PAD_CFG_NF(GPP_D23, NONE, DEEP, NF2), + /* GPP_D24: Not used */ + PAD_NC(GPP_D24, NONE), + /* GPP_D25: Not used */ + PAD_NC(GPP_D25, NONE), + + /* GPP_E01: SOC_TP_INT#1 */ + PAD_CFG_GPI_APIC(GPP_E01, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E02: SOC_WWAN_WAKE2#_R */ + PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), + /* GPP_E03: SOC_SSD2_RST# */ + PAD_CFG_GPO(GPP_E03, 1, PLTRST), + /* GPP_E05: SOC_ALS_INT# */ + PAD_CFG_NF(GPP_E05, NONE, DEEP, NF4), + /* GPP_E06: Not used */ + PAD_NC(GPP_E06, NONE), + /* GPP_E07: Not used */ + PAD_NC(GPP_E07, NONE), + /* GPP_E08: Not used_R*/ + PAD_NC(GPP_E08, NONE), + /* GPP_E09: USB_OC0# */ + PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), + /* GPP_E10: Not used */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11: Not used */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12: SOC_THC_I2C_0_SCL */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), + /* GPP_E13: SOC_THC_I2C_0_SDA */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), + /* GPP_E14: Not used */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15: Not used */ + PAD_NC(GPP_E15, NONE), + /* GPP_E16: Not used */ + /* THC NOTE: use GPO instead of GPO for THC0 Rst */ + PAD_NC(GPP_E16, NONE), + /* GPP_E17: Not used */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18: SOC_TP_INT# */ + PAD_CFG_GPI_APIC(GPP_E18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* GPP_E19: Not used */ + PAD_NC(GPP_E19, NONE), + /* GPP_E20: Not used# */ + PAD_NC(GPP_E20, NONE), + /* GPP_E21: SOC_I2C_PD_INT# */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + /* GPP_E22: SOC_WP_OD */ + PAD_CFG_GPI(GPP_E22, NONE, DEEP), + + /* GPP_F00: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01: M.2_CNV_BRI_RSP_BT_UART2_RXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F01, NONE, DEEP, NF1), + /* GPP_F02: M.2_CNV_RGI_DT_BT_UART2_TXD */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F03, NONE, DEEP, NF1), + /* GPP_F04: CNV_RF_RESET_R_N */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05: CRF_CLKREQ_R */ + /* NOTE: IOSSTAGE: 'Ignore' for S0ix */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06: COEX3 */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), + /* GPP_F07: Not used*/ + PAD_NC(GPP_F07, NONE), + /* GPP_F08: Not used */ + PAD_NC(GPP_F08, NONE), + /* GPP_F09: SX_EXIT_HOLDOFF# */ + PAD_CFG_NF(GPP_F09, NONE, DEEP, NF2), + /* GPP_F10: Not used */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11: Not used */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12: Not used */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13: Not used */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14: Not used */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15: Not used */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16: Not used */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17: Not used */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18: Not used */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19: Not used */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20: AP_FP_FW_UP_STRAP */ + PAD_CFG_GPO(GPP_F20, 1, DEEP), + /* GPP_F22: Not used */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23: SLP_S0#_GATE */ + PAD_CFG_GPO(GPP_F23, 1, PLTRST), + + /* GPP_H00: Not used */ + PAD_NC(GPP_H00, NONE), + /* GPP_H01: Not used*/ + PAD_NC(GPP_H01, NONE), + /* GPP_H02: Not used*/ + PAD_NC(GPP_H02, NONE), + /* GPP_H03: EN_PWR_FP */ + PAD_CFG_GPO(GPP_H03, 1, DEEP), + /* GPP_H04: COEX1 */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), + /* GPP_H05: COEX2 */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), + /* GPP_H06: SOC_I2C_3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: SOC_I2C_3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08: UART_0_CRXD_DTXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART_0_CTXD_DRXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + /* GPP_H10: Not used */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_H11, NONE, PLTRST, LEVEL, INVERT), + /* GPP_H13: CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14: ISH_I2C_1_SDA */ + PAD_CFG_NF(GPP_H14, NONE, DEEP, NF2), + /* GPP_H15: ISH_I2C_1_SCL */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF2), + /* GPP_H16: SOC_AUDIO_STRAP */ + PAD_CFG_GPI(GPP_H16, NONE, DEEP), + /* GPP_H17: FP_RST_1V8_OD# */ + PAD_CFG_GPO(GPP_H17, 1, DEEP), + /* GPP_H19: SOC_I2C_0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20: SOC_I2C_0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21: SOC_I2C_1_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22: SOC_I2C_1_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + + /* GPP_S00: SNDW_3_SCL */ + PAD_CFG_NF(GPP_S00, NONE, DEEP, NF1), + /* GPP_S01: SNDW_3_SDA */ + PAD_CFG_NF(GPP_S01, NONE, DEEP, NF1), + /* GPP_S02: SOC_DMIC_CLK0 */ + PAD_CFG_NF(GPP_S02, NONE, DEEP, NF5), + /* GPP_S03: SOC_DMIC_DATA0 */ + PAD_CFG_NF(GPP_S03, NONE, DEEP, NF5), + /* GPP_S04: SNDW2_CLK */ + PAD_CFG_NF(GPP_S04, NONE, DEEP, NF2), + /* GPP_S05: SNDW2_DATA0 */ + PAD_CFG_NF(GPP_S05, NONE, DEEP, NF2), + /* GPP_S06: SOC_DMIC_CLK1 */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* GPP_S07: SOC_DMIC_DATA1 */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), + + /* GPP_V00: PM_BATLOW# */ + PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), + /* GPP_V01: AC_PRESENT */ + PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), + /* GPP_V02: LAN_WAKE# */ + PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), + /* GPP_V03: PBTN_OUT# */ + PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), + /* GPP_V04: PM_SLP_S3# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05: PM_SLP_S4# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06: PM_SLP_A# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07: SUSCLK*/ + PAD_CFG_NF(GPP_V07, NONE, DEEP, NF1), + /* GPP_V08: SLP_WLAN# */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09: PM_SLP_S5# */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10: Not used */ + PAD_NC(GPP_V10, NONE), + /* GPP_V11: PM_SLP_LAN# */ + PAD_NC(GPP_V11, NONE), + /* GPP_V12: WAKE# */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13: GPP_V13_CATERR_N */ + PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), + /* GPP_V14: GPP_V14_FORCEPR_N */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15: GPP_V15_THERMTRIP_N */ + PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), + /* GPP_V16: VCCST_EN */ + PAD_CFG_NF(GPP_V16, NONE, DEEP, NF1), + /* GPP_V17: Not used */ + PAD_NC(GPP_V17, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_H08: UART_0_CRXD_DTXD */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), + /* GPP_H09: UART_0_CTXD_DRXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), + + /* GPP_H06: SOC_I2C_3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07: SOC_I2C_3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_D15: GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_H11, NONE, LEVEL, INVERT, LOCK_CONFIG), +}; + +/* Pad configuration in romstage */ +static const struct pad_config romstage_gpio_table[] = { + /* GPP_C00: SOC_SMBCLK */ + PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), + /* GPP_C01: SOC_SMBDATA */ + PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +/* Create the stub for romstage gpio, typically use for power sequence */ +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE0_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE1_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE2_NAME), + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE3_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h b/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h index 27c87b3..349cf32 100644 --- a/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h +++ b/src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +/* TODO: Add GPIO as per fatcat board */ +/* Dummy pin number for ACPI table to build */ +#define GPE_EC_WAKE GPE0_LAN_WAK + #endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: mb/google/fatcat/var/francka: Add HDA verb tables
by Ian Feng (Code Review) 08 Nov '24

08 Nov '24

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85036?usp=email ) Change subject: mb/google/fatcat/var/francka: Add HDA verb tables ...................................................................... mb/google/fatcat/var/francka: Add HDA verb tables We use ALC256 as HDA codec on francka, add the verb table. BUG=b:370668037 TEST=emerge-nissa coreboot Change-Id: I579c9fd23c763d6791944732889021ffa03da448 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- A src/mainboard/google/fatcat/variants/francka/hda_verb.c 1 file changed, 126 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/85036/1 diff --git a/src/mainboard/google/fatcat/variants/francka/hda_verb.c b/src/mainboard/google/fatcat/variants/francka/hda_verb.c new file mode 100644 index 0000000..2f703b7 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/hda_verb.c @@ -0,0 +1,126 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0256, /* Codec Vendor / Device ID: Realtek ALC256 */ + 0x10ec12ac, /* Subsystem ID */ + 0x00000013, /* Number of jacks (NID entries) */ + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb Table */ + AZALIA_SUBVENDOR(0, 0x10ec12ac), + + /* Pin Widget Verb Table */ + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x04A11040), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40610041), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + /* + * Widget node 0x20 - 1 + * Codec hidden reset and speaker power 2W/4ohm + */ + 0x0205001A, + 0x0204C003, + 0x02050038, + 0x02047901, + /* + * Widget node 0x20 - 2 + * Class D power on Reset + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 3 + * Disable AGC and set AGC limit to -1.5dB + */ + 0x02050016, + 0x02040C50, + 0x02050012, + 0x0204EBC1, + /* + * Widget node 0x20 - 4 + * Set AGC Post gain +1.5dB then Enable AGC + */ + 0x02050013, + 0x02044023, + 0x02050016, + 0x02040E50, + /* + * Widget node 0x20 - 5 + * Silence detector enabling + Set EAPD to verb control + */ + 0x02050037, + 0x0204FE15, + 0x02050010, + 0x02040020, + /* + * Widget node 0x20 - 6 + * Silence data mode Threshold (-90dB) + */ + 0x02050030, + 0x0204A000, + 0x0205001B, + 0x02040A4B, + /* + * Widget node 0x20 - 7 + * Default setting-1 + */ + 0x05750003, + 0x05740DA3, + 0x02050046, + 0x02040004, + /* + * Widget node 0x20 - 8 + * support 1 pin detect two port + */ + 0x02050009, + 0x0204E003, + 0x0205000A, + 0x02047770, + /* + * Widget node 0x20 - 9 + * To set LDO1/LDO2 as default + */ + 0x02050008, + 0x02046A0C, + 0x02050008, + 0x02046A0C, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x01470C00, + 0x02050036, + 0x02047151, + 0x01470740, + /* Dos beep path - 2 */ + 0x0143b000, + 0x01470C02, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; -- To view, visit https://review.coreboot.org/c/coreboot/+/85036?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I579c9fd23c763d6791944732889021ffa03da448 Gerrit-Change-Number: 85036 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

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[XS] Change in coreboot[main]: soc/mediatek/common: Increase DEV_MEM memory range to 16GB
by Yidi Lin (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85035?usp=email ) Change subject: soc/mediatek/common: Increase DEV_MEM memory range to 16GB ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85035/comment/98d0e77d_67305230?us… : PS1, Line 7: soc/mediatek/common: Increase DEV_MEM memory range to 16GB > Will this change have any side effect on existing platforms? I don't think this would cause any side effect. The existed platform won't access the memory address outside 8GB during memory tests. The range is hard coded in the blob. Even if they do access the address outside 8GB or the address they don't support, the errors should be raised before this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/85035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Gerrit-Change-Number: 85035 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 04:04:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85034/comment/5e6cb49d_6e2c4214?us… : PS1, Line 7: LPDDR5 `DDR5/LPDDR5` -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 03:38:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/common: Increase DEV_MEM memory range to 16GB
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85035?usp=email ) Change subject: soc/mediatek/common: Increase DEV_MEM memory range to 16GB ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85035/comment/fd043d72_f9f59552?us… : PS1, Line 7: soc/mediatek/common: Increase DEV_MEM memory range to 16GB Will this change have any side effect on existing platforms? -- To view, visit https://review.coreboot.org/c/coreboot/+/85035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Gerrit-Change-Number: 85035 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 03:37:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 03:36:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek: Obtain LPDDR type from trained memory info
by Yu-Ping Wu (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Crystal Guo, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85033?usp=email ) Change subject: soc/mediatek: Obtain LPDDR type from trained memory info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Gerrit-Change-Number: 85033 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 08 Nov 2024 03:35:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/common: Increase DEV_MEM memory range to 16GB
by Jarried Lin (Code Review) 08 Nov '24

08 Nov '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85035?usp=email ) Change subject: soc/mediatek/common: Increase DEV_MEM memory range to 16GB ...................................................................... soc/mediatek/common: Increase DEV_MEM memory range to 16GB Map a proper DRAM range for memory test during calibration. TEST=memory test passed on Rauru BUG=b:317009620 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef --- M src/soc/mediatek/common/mmu_operations.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/85035/1 diff --git a/src/soc/mediatek/common/mmu_operations.c b/src/soc/mediatek/common/mmu_operations.c index cbd6c09..be216f6 100644 --- a/src/soc/mediatek/common/mmu_operations.c +++ b/src/soc/mediatek/common/mmu_operations.c @@ -19,11 +19,11 @@ mmu_init(); /* - * Set 0x0 to 8GB address as device memory. We want to config IO_PHYS + * Set 0x0 to 16GB address as device memory. We want to config IO_PHYS * address to DEV_MEM, and map a proper range of dram for the memory * test during calibration. */ - mmu_config_range((void *)0, (uintptr_t)8U * GiB, DEV_MEM); + mmu_config_range((void *)0, (uintptr_t)16U * GiB, DEV_MEM); /* SRAM is cached */ mmu_config_range(_sram, REGION_SIZE(sram), SECURE_CACHED_MEM); -- To view, visit https://review.coreboot.org/c/coreboot/+/85035?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I06f31ef14715897ba889076d78b8c2d015dd08ef Gerrit-Change-Number: 85035 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 08 Nov '24

08 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Shuo Liu, Vasiliy Khoruzhick. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/83321?usp=email ) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... Patch Set 49: (1 comment) File src/soc/intel/snowridge/chip.c: https://review.coreboot.org/c/coreboot/+/83321/comment/005295ce_7f386ce4?us… : PS15, Line 418: } > Will the common pci dev enabler be called as well? Seems there is no `enable` method in the default PCI or PCIe device operations, and the `PCI_COMMAND_SERR` is also not set by common code. Thus, this function will set the SERR bit of all PCH static devices if they are marked as enabled and disable responding to IO and memory requests if they are marked as disabled. -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 49 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Fri, 08 Nov 2024 03:06:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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coreboot-gerrit November 2024