coreboot-gerrit November 2024

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[S] Change in coreboot[main]: soc/mediatek: Obtain LPDDR type from trained memory info
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85033?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek: Obtain LPDDR type from trained memory info ...................................................................... soc/mediatek: Obtain LPDDR type from trained memory info Add lpddr_type to ddr_base_info struct to obtain LPDDR type from trained memory info. BUG=b:357743097 TEST=build pass Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85033 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/soc/mediatek/common/include/soc/dramc_param_common.h M src/soc/mediatek/common/include/soc/emi.h M src/soc/mediatek/common/memory.c 3 files changed, 9 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/dramc_param_common.h b/src/soc/mediatek/common/include/soc/dramc_param_common.h index 7dd8bba..a1fac9a 100644 --- a/src/soc/mediatek/common/include/soc/dramc_param_common.h +++ b/src/soc/mediatek/common/include/soc/dramc_param_common.h @@ -92,7 +92,8 @@ struct ddr_base_info { u32 config_dvfs; /* SDRAM_DVFS_FLAG */ struct sdram_info sdram; - u32 voltage_type; /* SDRAM_VOLTAGE_TYPE */ + u16 lpddr_type; + u16 voltage_type; /* SDRAM_VOLTAGE_TYPE */ u32 support_ranks; u64 rank_size[RANK_MAX]; struct emi_mdl emi_config; diff --git a/src/soc/mediatek/common/include/soc/emi.h b/src/soc/mediatek/common/include/soc/emi.h index 0070ec1..313ccff 100644 --- a/src/soc/mediatek/common/include/soc/emi.h +++ b/src/soc/mediatek/common/include/soc/emi.h @@ -16,5 +16,6 @@ u32 get_ddr_geometry(void); u32 get_ddr_type(void); void init_dram_by_params(struct dramc_param *dparam); +enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type); #endif /* SOC_MEDIATEK_COMMON_EMI_H */ diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 089c6af..f08b1d5 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -106,6 +106,11 @@ return size; } +__weak enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type) +{ + return MEM_CHIP_LPDDR4X; +} + static void fill_dram_info(struct mem_chip_info *mc, const struct ddr_base_info *ddr) { unsigned int c, r; @@ -118,7 +123,7 @@ for (r = 0; r < ddr->mrr_info.rank_nums; r++) { entry->channel = c; entry->rank = r; - entry->type = MEM_CHIP_LPDDR4X; + entry->type = map_to_lpddr_dram_type(ddr->lpddr_type); entry->channel_io_width = DQ_DATA_WIDTH_LP4; entry->density_mbits = ddr->mrr_info.mr8_density[r] / CHANNEL_MAX / (MiB / 8); -- To view, visit https://review.coreboot.org/c/coreboot/+/85033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I73c9014784cc4872826d721f3fab9ed1c5255f31 Gerrit-Change-Number: 85033 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add dram calibration support
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85098?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add dram calibration support ...................................................................... soc/mediatek/mt8196: Add dram calibration support Add support for MT8196 DRAM calibration. DRAM parameters and related constants are added in dramc_param.h and dramc_soc.h. As MT8196's dramc_param struct size is different from other MediaTek SoCs, replace the hardcoded RW_MRC_CACHE size in common code with a constant derived from chromeos.fmd. The common emi.c can be reused for MT8196 as well, so remove the duplicate mt8196/emi.{c,h}. Enable MEDIATEK_DRAM_BLOB_FAST_INIT to allow running DRAM fast calibration via the DRAM blob. Test=Build pass BUG=b:317009620 Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85098 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/common/memory.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk D src/soc/mediatek/mt8196/emi.c A src/soc/mediatek/mt8196/include/soc/dramc_param.h A src/soc/mediatek/mt8196/include/soc/dramc_soc.h D src/soc/mediatek/mt8196/include/soc/emi.h 7 files changed, 186 insertions(+), 36 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/common/memory.c b/src/soc/mediatek/common/memory.c index 72ea37e..089c6af 100644 --- a/src/soc/mediatek/common/memory.c +++ b/src/soc/mediatek/common/memory.c @@ -5,6 +5,7 @@ #include <cbmem.h> #include <commonlib/bsd/mem_chip_info.h> #include <console/console.h> +#include <fmap_config.h> #include <soc/dramc_common.h> #include <mrc_cache.h> #include <soc/dramc_param.h> @@ -13,12 +14,8 @@ #include <symbols.h> #include <timer.h> -/* This must be defined in chromeos.fmd in same name and size. */ -#define CAL_REGION_RW_MRC_CACHE "RW_MRC_CACHE" -#define CAL_REGION_RW_MRC_CACHE_SIZE 0x2000 - -_Static_assert(sizeof(struct dramc_param) <= CAL_REGION_RW_MRC_CACHE_SIZE, - "sizeof(struct dramc_param) exceeds " CAL_REGION_RW_MRC_CACHE); +_Static_assert(sizeof(struct dramc_param) <= FMAP_SECTION_RW_MRC_CACHE_SIZE, + "sizeof(struct dramc_param) exceeds RW_MRC_CACHE size"); const char *get_dram_geometry_str(u32 ddr_geometry); const char *get_dram_type_str(u32 ddr_type); diff --git a/src/soc/mediatek/mt8196/Kconfig b/src/soc/mediatek/mt8196/Kconfig index d373b95..69823e4 100644 --- a/src/soc/mediatek/mt8196/Kconfig +++ b/src/soc/mediatek/mt8196/Kconfig @@ -8,6 +8,9 @@ select ARCH_ROMSTAGE_ARMV8_64 select ARCH_RAMSTAGE_ARMV8_64 select HAVE_UART_SPECIAL + select CACHE_MRC_SETTINGS + select MEDIATEK_DRAM_BLOB_FAST_INIT + select USE_CBMEM_DRAM_INFO select SOC_MEDIATEK_COMMON select FLASH_DUAL_IO_READ select ARM64_USE_ARCH_TIMER diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index f67ef0c..b0eb693 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -18,14 +18,18 @@ bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c +romstage-y += ../common/dram_init.c +romstage-y += ../common/dramc_param.c romstage-$(CONFIG_PCI) += ../common/early_init.c ../common/pcie.c -romstage-y += emi.c +romstage-y += ../common/emi.c romstage-y += irq2axi.c romstage-y += l2c_ops.c +romstage-y += ../common/memory.c +romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-y += ../common/early_init.c -ramstage-y += emi.c +ramstage-y += ../common/emi.c ramstage-y += l2c_ops.c ramstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c @@ -35,6 +39,15 @@ CPPFLAGS_common += -Isrc/soc/mediatek/mt8196/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include +MT8196_BLOB_DIR := 3rdparty/blobs/soc/mediatek/mt8196 + +DRAM_CBFS := $(CONFIG_CBFS_PREFIX)/dram +$(DRAM_CBFS)-file := $(MT8196_BLOB_DIR)/dram.elf +$(DRAM_CBFS)-type := stage +$(DRAM_CBFS)-compression := $(CBFS_PRERAM_COMPRESS_FLAG) +ifneq ($(wildcard $($(DRAM_CBFS)-file)),) + cbfs-files-y += $(DRAM_CBFS) +endif $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin ./util/mtkheader/gen-bl-img.py mt8196 sf $< $@ diff --git a/src/soc/mediatek/mt8196/emi.c b/src/soc/mediatek/mt8196/emi.c deleted file mode 100644 index 1129ce1..0000000 --- a/src/soc/mediatek/mt8196/emi.c +++ /dev/null @@ -1,13 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on MT8196 Functional Specification - * Chapter number: 10.2 - */ - -#include <soc/emi.h> - -size_t sdram_size(void) -{ - return (size_t)4 * GiB; -} diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_param.h b/src/soc/mediatek/mt8196/include/soc/dramc_param.h new file mode 100644 index 0000000..b35d518 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/dramc_param.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ +#define __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ + +/* + * NOTE: This file is shared between coreboot and dram blob. Any change in this + * file should be synced to the other repository. + */ + +#include <soc/dramc_param_common.h> +#include <soc/dramc_soc.h> +#include <stdint.h> +#include <sys/types.h> + +#define DRAMC_PARAM_HEADER_VERSION 2 + +struct sdram_params { + /* rank, cbt */ + u32 rank_num; + u32 dram_cbt_mode; + + u16 delay_cell_timex100; + u8 u18ph_dly; + + /* duty */ + s8 duty_clk_delay[CHANNEL_MAX][RANK_MAX]; + s8 duty_dqs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_wck_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_mck16x_delay[CHANNEL_MAX][DQS_NUMBER_LP5 + 1]; + s8 duty_dq_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + s8 duty_dqm_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* cbt */ + u8 cbt_final_vref[CHANNEL_MAX][RANK_MAX]; + u8 cbt_final_range[CHANNEL_MAX][RANK_MAX]; + s16 cbt_cmd_dly[CHANNEL_MAX]; + u16 cbt_cs_dly[CHANNEL_MAX]; + u8 cbt_ca_prebit_dly[CHANNEL_MAX][DQS_BIT_NUMBER]; + + /* write leveling */ + u8 wr_level_pi[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 wr_level_dly[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* gating */ + u8 gating_UI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_PI[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 gating_pass_count[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 wck2dqo_cnt[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* rx input buffer */ + s8 dq_offc[CHANNEL_MAX][DQ_DATA_WIDTH_LP5]; + s8 dqm_offc[CHANNEL_MAX][DQS_NUMBER_LP5]; + + /* tx perbit */ + u16 tx_window_vref[CHANNEL_MAX][RANK_MAX]; + u16 tx_window_vref_range[CHANNEL_MAX][RANK_MAX]; + u16 tx_dq[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_dqm_only[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_perbit_dlyline[CHANNEL_MAX][RANK_MAX][EXT_DQ_DATA_WIDTH]; + u16 wck2dqi_cnt0[CHANNEL_MAX][RANK_MAX]; + u16 wck2dqi_cnt1[CHANNEL_MAX][RANK_MAX]; + + /* rx datlat */ + u8 rx_datlat[CHANNEL_MAX]; + + /* rx perbit */ + u8 rx_best_vref_perbyte[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 rx_best_vref_perbit[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + u16 rx_perbit_dqs[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dqm[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 rx_perbit_dq[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + s16 rx_perbit_begin; + + /* dvs */ + u8 dvs_delay[CHANNEL_MAX][DQS_NUMBER_LP5]; + u8 perbit_dcc[CHANNEL_MAX][RANK_MAX][DQ_DATA_WIDTH_LP5]; + + /* dcm */ + u8 best_u[CHANNEL_MAX][RANK_MAX]; + u8 best_l[CHANNEL_MAX][RANK_MAX]; + + /* Read DCA */ + s8 rdca_u[CHANNEL_MAX][RANK_MAX]; + s8 rdca_l[CHANNEL_MAX][RANK_MAX]; + + /* RDCC */ + s8 rdcc[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + + /* tx oe */ + u8 tx_oe_dq_mck[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u8 tx_oe_dq_ui[CHANNEL_MAX][RANK_MAX][DQS_NUMBER_LP5]; + u16 tx_oe_offset[CHANNEL_MAX][RANK_MAX]; +}; + +struct dramc_data { + struct ddr_base_info ddr_info; + struct sdram_params freq_params[DRAM_DFS_SHU_MAX]; +}; + +struct dramc_param { + struct dramc_param_header header; + void (*do_putc)(unsigned char c); + struct dramc_data dramc_datas; +}; + +struct dramc_param *get_dramc_param_from_blob(void *blob); +void dump_param_header(const void *blob); +int validate_dramc_param(const void *blob); +int is_valid_dramc_param(const void *blob); +int initialize_dramc_param(void *blob); + +#endif /* __SOC_MEDIATEK_MT8196_DRAMC_PARAM_H__ */ diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h new file mode 100644 index 0000000..dde00c2 --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__ +#define __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__ + +#include <soc/dramc_soc_common.h> +#include <stdint.h> + +typedef enum { + CHANNEL_A = 0, + CHANNEL_B, + CHANNEL_C, + CHANNEL_D, + CHANNEL_MAX, +} DRAM_CHANNEL_T; + +typedef enum { + RANK_0 = 0, + RANK_1, + RANK_MAX, +} DRAM_RANK_T; + +typedef enum { + SRAM_SHU0 = 0, + SRAM_SHU1, + SRAM_SHU2, + SRAM_SHU3, + SRAM_SHU4, + SRAM_SHU5, + SRAM_SHU6, + SRAM_SHU7, + SRAM_SHU8, + SRAM_SHU9, + SRAM_SHU10, + SRAM_SHU11, + DRAM_DFS_SRAM_MAX +} DRAM_DFS_SRAM_SHU_T; /* DRAM SRAM RG type */ + +typedef enum { + DRVP = 0, + DRVN, + ODTN, + IMP_DRV_MAX, +} DRAM_IMP_DRV_T; + +#define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX +#define DQS_NUMBER_LP5 2 +#define DQ_DATA_WIDTH_LP5 16 +#define EXT_DQ_DATA_WIDTH 18 + +#endif /* __SOC_MEDIATEK_MT8196_DRAMC_SOC_H__ */ diff --git a/src/soc/mediatek/mt8196/include/soc/emi.h b/src/soc/mediatek/mt8196/include/soc/emi.h deleted file mode 100644 index 6acc0cf..0000000 --- a/src/soc/mediatek/mt8196/include/soc/emi.h +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is created based on MT8196 Functional Specification - * Chapter number: 10.2 - */ - -#ifndef SOC_MEDIATEK_MT8196_EMI_H -#define SOC_MEDIATEK_MT8196_EMI_H - -#include <stddef.h> - -size_t sdram_size(void); - -#endif /* SOC_MEDIATEK_MT8196_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85098?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeaf73e31b29ef376a28ca2721dba0d4866d6e8b Gerrit-Change-Number: 85098 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85094?usp=email ) Change subject: mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K ...................................................................... mb/google/rauru: Enlarge RW_MRC_CACHE from 8K to 16K Rauru has MT8196 SoC. Following previous MediaTek SoCs, MT8196 will enable CACHE_MRC_SETTINGS, in order to store the DRAM parameters in the FMAP section RW_MRC_CACHE. As the size of the MT8196 parameters is larger (15968 bytes) compared to previous SoCs (7616 bytes), enlarge RW_MRC_CACHE from 8K to 16K. TEST=Build pass BUG=b:317009620 Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85094 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/chromeos.fmd 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Hung-Te Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/chromeos.fmd b/src/mainboard/google/rauru/chromeos.fmd index 5b2234d..a1595df 100644 --- a/src/mainboard/google/rauru/chromeos.fmd +++ b/src/mainboard/google/rauru/chromeos.fmd @@ -28,9 +28,9 @@ RW_FWID_A 0x100 } RW_MISC 36K { - RW_VPD(PRESERVE) 16K # At least 8K. + RW_VPD(PRESERVE) 8K # At least 8K. RW_NVRAM(PRESERVE) 8K - RW_MRC_CACHE(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 16K RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. } RW_SECTION_B 1500K { -- To view, visit https://review.coreboot.org/c/coreboot/+/85094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I35aad5a3a82686a68dd66e993355aa32cc19043e Gerrit-Change-Number: 85094 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Karthik Ramasubramanian, Kenneth Chan, Subrata Banik. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85107?usp=email ) Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85107/comment/ad7f9a21_284f14aa?us… : PS2, Line 10: remvoed > Nit: removed fixed. https://review.coreboot.org/c/coreboot/+/85107/comment/b29a6dde_0e05fa6f?us… : PS2, Line 18: to > Nit: remove 'to' fixed. File src/mainboard/google/brox/variants/jubilant/smihandler.c: https://review.coreboot.org/c/coreboot/+/85107/comment/76b93ba0_6122d2fa?us… : PS2, Line 16: if (slp_typ == ACPI_S5) { : if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { > I would recommend to check specifically for LTE and LTE SAR config. […] fixed. File src/mainboard/google/brox/variants/jubilant/variant.c: https://review.coreboot.org/c/coreboot/+/85107/comment/27b276a6_eb5f8270?us… : PS2, Line 41: if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { > Same comment as in the other file: […] fixed. -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:09:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Karthik Ramasubramanian, Kenneth Chan, Subrata Banik. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85107?usp=email ) Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... Patch Set 5: (1 comment) File src/mainboard/google/brox/variants/jubilant/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85107/comment/06b63722_6b86a889?us… : PS2, Line 14: smm-y-$(CONFIG_FW_CONFIG) > smm-$(CONFIG_FW_CONFIG) This will cause build error! -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:08:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Ren Kuo, Subrata Banik. Hello David Wu, Karthik Ramasubramanian, Kenneth Chan, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85107?usp=email to look at the new patch set (#3). Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor The current WWAN(LTE) does not require any sar setting from RF team's suggestion, and sar sensor will be removed from DVT schematic. To reserve the extendibility, add the fw_config DB_1A_LTE_SAR: field DB_USB 11 12 option DB_1A 0 (None LTE) option DB_1A_LTE 1 (LTE without sar sensor) option DB_1A_LTE_SAR 2 (LTE with sar sensor) end Base on the fw_config to enable/disable related functions: 0)Disable WWAN and Sar if DB_USB = DB_1A 1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE 2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR BUG=b:375341992 TEST=Build and verify on jubilant by fw_config ls -l /sys/bus/i2c/devices i2cdetect -y -r Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/smihandler.c M src/mainboard/google/brox/variants/jubilant/variant.c 5 files changed, 34 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/85107/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: 3rdparty/intel-microcode: Update submodule to upstream main
by Elyes Haouas (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85113?usp=email ) Change subject: 3rdparty/intel-microcode: Update submodule to upstream main ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdb00537c7e8733c8c81c834313e24b5c7842609 Gerrit-Change-Number: 85113 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 13 Nov 2024 00:58:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: util/scripts/update_submodule: Extend commit ids to 12 chars
by Elyes Haouas (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85112?usp=email ) Change subject: util/scripts/update_submodule: Extend commit ids to 12 chars ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: see #85096 🙂 -- To view, visit https://review.coreboot.org/c/coreboot/+/85112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e356066b6598f586054f940684c26b6e5db2169 Gerrit-Change-Number: 85112 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 13 Nov 2024 00:57:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 12 Nov '24

12 Nov '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84986?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... 3rdparty/fsp: Update submodule to upstream master Updating from commit id 68328e2: 2024-08-05 14:46:35 +0800 - (NEX ADL-PS IPU 2024.4 (5045_03) FSP) to commit id d793185: 2024-10-14 15:15:03 +0800 - (NEX MTL-UH_MTL-PS MR1 (4053_58) FSP) This brings in 6 new commits: d793185 NEX MTL-UH_MTL-PS MR1 (4053_58) FSP 02b30da NEX RPL-P MR2 Hotfix (5134_03) FSP 08f9082 NEX RPL-S MR4/RPL-S Refresh MR2 Hotfix (5134_05) FSP 4dfe5cb NEX AZB IPU 2025.1 (5363_00) FSP 307e484 Update MemInfoHob.h 01f9575 Update MemInfoHob.h Change-Id: Ib4887f9ce8a76c374aeaa3fb03a8679ba446dff4 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84986 Reviewed-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M 3rdparty/fsp 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Nicholas Chin: Looks good to me, approved build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/3rdparty/fsp b/3rdparty/fsp index 68328e2..d793185 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 68328e297e195a6cfb1949b60d971c032a172ba3 +Subproject commit d7931859bfb1f7949bb455d53b9494dd731e9642 -- To view, visit https://review.coreboot.org/c/coreboot/+/84986?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4887f9ce8a76c374aeaa3fb03a8679ba446dff4 Gerrit-Change-Number: 84986 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: 3rdparty/fsp: Update submodule to upstream master
by Felix Singer (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Matt DeVillier. Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/84986?usp=email ) Change subject: 3rdparty/fsp: Update submodule to upstream master ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84986/comment/ad9da86f_a5101dea?us… : PS1, Line 9: commit id 68328e2 > Acknowledged I've created CB:85112 -- To view, visit https://review.coreboot.org/c/coreboot/+/84986?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib4887f9ce8a76c374aeaa3fb03a8679ba446dff4 Gerrit-Change-Number: 84986 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 22:19:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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