coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[L] Change in coreboot[main]: soc/mediatek/mt8196: Add mtcmos init support
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Guangjie Song, Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84497?usp=email ) Change subject: soc/mediatek/mt8196: Add mtcmos init support ...................................................................... Patch Set 32: (1 comment) File src/soc/mediatek/mt8196/mtcmos.c: https://review.coreboot.org/c/coreboot/+/84497/comment/46b96dc8_f918fb95?us… : PS26, Line 886: mtcmos_cb_register > @jarried.lin@mediatek.com @guangjie.song@mediatek.corp-partner.google. […] Any update? -- To view, visit https://review.coreboot.org/c/coreboot/+/84497?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f2bb10453377a8412e80ac0c100760ebfbaff9 Gerrit-Change-Number: 84497 Gerrit-PatchSet: 32 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:44:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Guangjie Song <guangjie.song(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire This change adds support for the ALC721 codec in the device tree and enables it based on the fw_config. BUG=b:368495490 TEST=Boot on google fatcat board Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Signed-off-by: Varun Upadhyay <varun.upadhyay(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/fw_config.c M src/mainboard/google/fatcat/variants/fatcat/overridetree.cb 2 files changed, 7 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c index 3162df4..9900492 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/fw_config.c +++ b/src/mainboard/google/fatcat/variants/fatcat/fw_config.c @@ -551,7 +551,8 @@ GPIO_PADBASED_OVERRIDE(padbased_table, i2s_enable_pads); else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_MAX98373_ALC5682_SNDW))) GPIO_PADBASED_OVERRIDE(padbased_table, sndw_external_codec_enable_pads); - else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW))) + else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC722_SNDW)) || + fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC721_SNDW))) GPIO_PADBASED_OVERRIDE(padbased_table, sndw_alc722_enable_pads); else if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads); diff --git a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb index bed928e..0fd79d0 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/fatcat/overridetree.cb @@ -5,6 +5,7 @@ option AUDIO_ALC722_SNDW 2 option AUDIO_ALC256_HDA 3 option AUDIO_MAX98360_ALC5682I_I2S 4 + option AUDIO_ALC721_SNDW 5 end field WIFI 4 5 option WIFI_CNVI_6 0 @@ -623,6 +624,10 @@ device generic 1.1 on probe AUDIO AUDIO_ALC722_SNDW end + # SoundWire Link 3 ID 1 + device generic 3.1 on + probe AUDIO AUDIO_ALC721_SNDW + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 4 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com>

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[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Crystal Guo. Yu-Ping Wu has posted comments on this change by Crystal Guo. ( https://review.coreboot.org/c/blobs/+/85110?usp=email ) Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration ...................................................................... Patch Set 3: Code-Review+2 Verified+1 -- To view, visit https://review.coreboot.org/c/blobs/+/85110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Gerrit-Change-Number: 85110 Gerrit-PatchSet: 3 Gerrit-Owner: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:30:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85044?usp=email ) ( 4 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT ...................................................................... mb/google/nissa/var/rull: when using pcie wifi7, turn off CNVI BT When we use PCIE wifi7, CNVI BT and BT offload should be turned off. BUG=b:378053901 BRANCH=None TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Signed-off-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85044 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> Reviewed-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/rull/variant.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved Kapil Porwal: Looks good to me, approved Kun Liu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/rull/variant.c b/src/mainboard/google/brya/variants/rull/variant.c index 8bb7fac..e1a95e6 100644 --- a/src/mainboard/google/brya/variants/rull/variant.c +++ b/src/mainboard/google/brya/variants/rull/variant.c @@ -22,6 +22,10 @@ printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); config->cnvi_bt_core = true; config->cnvi_bt_audio_offload = true; + } else { + printk(BIOS_INFO, "CNVi bluetooth disabled by fw_config\n"); + config->cnvi_bt_core = false; + config->cnvi_bt_audio_offload = false; } } -- To view, visit https://review.coreboot.org/c/coreboot/+/85044?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0adc446220051da59560c9a59d6f334b3a11ac7b Gerrit-Change-Number: 85044 Gerrit-PatchSet: 6 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: util/scripts/update_submodule: Extend commit ids to 12 chars
by Matt DeVillier (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer. Matt DeVillier has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85112?usp=email ) Change subject: util/scripts/update_submodule: Extend commit ids to 12 chars ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e356066b6598f586054f940684c26b6e5db2169 Gerrit-Change-Number: 85112 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:23:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Use CSE sync in ramstage config
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85108?usp=email ) Change subject: soc/intel/alderlake: Use CSE sync in ramstage config ...................................................................... soc/intel/alderlake: Use CSE sync in ramstage config This patch updates the eSOL rendering logic to use the SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of SOC_INTEL_CSE_LITE_SKU. The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to determine whether to render eSOL during ramstage. The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically indicates whether CSE synchronization is performed during ramstage, making it a more appropriate choice for this purpose. This change ensures that eSOL is rendered correctly during ramstage on platforms that require CSE synchronization. TEST=Able to render eSOL during ramstage for google/trulo. Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85108 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Christian Walter <christian.walter(a)9elements.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Christian Walter: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fc9721c..c98ce10 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -439,7 +439,7 @@ * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take * < 1-minute hence, let's inform the end user with an on-screen text message. */ - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) { if (esol_required) { name = "memory training and CSE update"; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/85108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Gerrit-Change-Number: 85108 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85103?usp=email ) Change subject: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/85103/comment/ae657a5e_d679e47f?us… : PS1, Line 188: ux_inform_user_of_update_operation("CSE update"); > We might not need extensively relocated event logging. It's currently right after the CSE sync update, which serves the purpose of event logging. The patch CB:84398 actually moved the CSE sync logging during CSE FW sync. > > Furthermore, ESOL and event logging for CSE sync are two different entities. We may not need to check ESOL status; the log just informs that the CSE sync operation has been performed. > > Therefore, I believe we might not need CB:85111. sorry my bad, i missed that I have already migrated elog into CSE driver from soc local. https://review.coreboot.org/c/coreboot/+/84398/2/src/soc/intel/common/block… please ignore my review comment -- To view, visit https://review.coreboot.org/c/coreboot/+/85103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Gerrit-Change-Number: 85103 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:20:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: util/scripts/update_submodule: Extend commit ids to 12 chars
by Matt DeVillier (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Elyes Haouas, Felix Singer. Matt DeVillier has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85112?usp=email ) Change subject: util/scripts/update_submodule: Extend commit ids to 12 chars ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > see #85096 🙂 this one does the hash truncation better IMO -- To view, visit https://review.coreboot.org/c/coreboot/+/85112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e356066b6598f586054f940684c26b6e5db2169 Gerrit-Change-Number: 85112 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:14:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Anil Kumar K, Naveen M, Pranava Y N, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/16c9b3d1_1c663130?us… : PS2, Line 8: AUDIO_ALC721_SNDW > Re#1: In the current scenario yes, either RT721/RT722 will configure the same sdw GPIO pins.. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:06:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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coreboot-gerrit November 2024