coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Dinesh Gehlot (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85103?usp=email ) Change subject: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/85103/comment/86e8ffc8_6d7ae644?us… : PS1, Line 188: ux_inform_user_of_update_operation("CSE update"); > Earlier it was getting logged from cse_fw_update. […] We might not need extensively relocated event logging. It's currently right after the CSE sync update, which serves the purpose of event logging. The patch CB:84398 actually moved the CSE sync logging during CSE FW sync. Furthermore, ESOL and event logging for CSE sync are two different entities. We may not need to check ESOL status; the log just informs that the CSE sync operation has been performed. Therefore, I believe we might not need CB:85111. -- To view, visit https://review.coreboot.org/c/coreboot/+/85103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Gerrit-Change-Number: 85103 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:04:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Naveen M (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik, Varun Upadhyay. Naveen M has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/5c612897_0bd9d1ce?us… : PS2, Line 8: AUDIO_ALC721_SNDW > > Yes. This data is important for kernel & ucm. […] Re#1: In the current scenario yes, either RT721/RT722 will configure the same sdw GPIO pins.. But assume if we have multiple combinations for the same sound card but for different boards. Example: Already Implemented following REX audio configuration caters different mic configuration for the same audio card(sof-rt5682) with delta wrt only DMIC channels, this helps us to apply different UCM settings by creating 2 folders(sof-rt5682.rex & sof-rt5682.rex.2ch) 2channel dmic: https://chrome-internal.googlesource.com/chromeos/project/rex/rex/+/refs/he… Corresponding UCM Directory: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/e0fb79aeb6cc… 4channel dmic: https://chrome-internal.googlesource.com/chromeos/project/rex/rex/+/refs/he… Corresponding UCM Directory: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/e0fb79aeb6cc… Overall to distinguish UCM configuration for a specific board, currently we need to rely on cbi config. Re#2,Re#3: As this method is already implemented in Rex, we followed a similar configuration, will explore better method if we can optimize this. Thanks -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 03:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add HWCCF init support
by Jarried Lin (Code Review) 12 Nov '24

12 Nov '24

Jarried Lin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84496?usp=email ) Change subject: soc/mediatek/mt8196: Add HWCCF init support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie10819b5c5b205e92ab2ca0071e182803afc1f2e Gerrit-Change-Number: 84496 Gerrit-PatchSet: 11 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add early init support
by Jarried Lin (Code Review) 12 Nov '24

12 Nov '24

Jarried Lin has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84695?usp=email ) Change subject: soc/mediatek/mt8196: Add early init support ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84695?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44bc32812ad42724d8978b7b58c2e72ad659789e Gerrit-Change-Number: 84695 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jianjun Wang <jianjun.wang(a)mediatek.com> Gerrit-Reviewer: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Amanda Hwang, Dtrain Hsu, Paul Menzel, Pranava Y N, Subrata Banik. Hello Amanda Hwang, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85037?usp=email to look at the new patch set (#9). Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings 1. Configure GPIOs according to schematics_20241112. 2. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka. 3. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka. 4. Set TMP I2C bus to 0x01 for francka. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 5 files changed, 472 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 9 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Dinesh Gehlot (Code Review) 12 Nov '24

12 Nov '24

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[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place
by Dinesh Gehlot (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, Tarun. Dinesh Gehlot has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email ) Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/85111/comment/54b57428_2c41dca8?us… : PS1, Line 449: elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); I was wondering if it would be alright to add a CSE logging event at this stage, given that the CSE sync hasn't started. -- To view, visit https://review.coreboot.org/c/coreboot/+/85111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Gerrit-Change-Number: 85111 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:50:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: vc/google: Refactor config to set Fn key scancode
by Kapil Porwal (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Paul Menzel. Kapil Porwal has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85109?usp=email ) Change subject: vc/google: Refactor config to set Fn key scancode ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85109/comment/447b5be1_87a7bc1c?us… : PS1, Line 9: Google Strauss : keyboard > What is the difference to the standard keyboard version? A different key? Yes, it has a Fn key with scan code 94. -- To view, visit https://review.coreboot.org/c/coreboot/+/85109?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5d54879d415e4403b2d7948432bb06ab983b86 Gerrit-Change-Number: 85109 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:49:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Enable lastbus debug hardware
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84928?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Enable lastbus debug hardware ...................................................................... soc/mediatek/mt8196: Enable lastbus debug hardware Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out on the serial console for bus hanging analysis. TEST=build pass, and check log with: [INFO ] ******************* MT8196 lastbus ****************** [INFO ] --- debug_ctrl_ao_APINFRA_IO_AO 0x10155000 37 --- [INFO ] 00402504 [INFO ] c34b00d6 [INFO ] 61804050 [INFO ] 00051840 [INFO ] 10401610 BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84928 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/lastbus.c 4 files changed, 164 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 559b8a1..3a1d103 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -13,6 +13,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += ../common/early_init.c +bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 19b90ee..578d353 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/early_init.h> +#include <soc/lastbus_v2.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/wdt.h> @@ -9,6 +10,7 @@ void bootblock_soc_init(void) { mtk_mmu_init(); + lastbus_init(); mtk_wdt_init(); mt_pll_init(); mt_pll_post_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 73702bf..24cea8f 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -6,6 +6,7 @@ enum { MCUSYS_BASE = 0x0C000000, MCUPM_CFG_BASE = 0x0C240000, + BUS_TRACE_MONITOR_BASE = 0x0D040000, IO_PHYS = 0x10000000, }; @@ -35,11 +36,20 @@ BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, GPIO_BASE = IO_PHYS + 0x0002D000, + DBGSYS_AO_DEBUG_BASE = IO_PHYS + 0x00031000, + APINFRA_IO_AO_DEBUG_BASE = IO_PHYS + 0x00155000, APINFRA_IO_CTRL_AO_BCRM_BASE = IO_PHYS + 0x00156000, + APINFRA_IO_CTRL_AO_DEBUG_BASE = IO_PHYS + 0x00157000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + APINFRA_DRAMC_AO_DEBUG_BASE = IO_PHYS + 0x002F1000, EMI0_BASE = IO_PHYS + 0x00469000, EMI0_MPU_BASE = IO_PHYS + 0x00468000, + NEMI_AO_DEBUG_BASE = IO_PHYS + 0x00416000, + SEMI_AO_DEBUG_BASE = IO_PHYS + 0x00516000, EMI1_BASE = IO_PHYS + 0x00569000, + APINFRA_EMI_AO_DEBUG_BASE = IO_PHYS + 0x00611000, + EMI_INFRA_AO_DEBUG_BASE = IO_PHYS + 0x00644000, + APINFRA_BIG4_AO_DEBUG_BASE = IO_PHYS + 0x00691000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, @@ -75,12 +85,21 @@ I2C8_BASE = IO_PHYS + 0x03B30000, I2C9_BASE = IO_PHYS + 0x03BB0000, IMP_IIC_WRAP_N_BASE = IO_PHYS + 0x03C30000, + APINFRA_IO_INTF_AO_DEBUG_BASE = IO_PHYS + 0x04011000, APINFRA_IO_NOC_AO_BCRM_BASE = IO_PHYS + 0x04012000, + APINFRA_MEM_INTF_AO_DEBUG_BASE = IO_PHYS + 0x04031000, APINFRA_MEM_NOC_AO_BCRM_BASE = IO_PHYS + 0x04032000, + APINFRA_INT_AO_DEBUG_BASE = IO_PHYS + 0x04051000, + APINFRA_MMU_AO_DEBUG_BASE = IO_PHYS + 0x04071000, + APINFRA_SLB_AO_DEBUG_BASE = IO_PHYS + 0x04091000, + APINFRA_MEM_AO_DEBUG_BASE = IO_PHYS + 0x04116000, APINFRA_MEM_CTRL_AO_BCRM_BASE = IO_PHYS + 0x04124000, + APINFRA_MEM_CTRL_AO_DEBUG_BASE = IO_PHYS + 0x04125000, APIFRBUS_AO_MEM_REG_BASE = IO_PHYS + 0x04126000, THERM_CTRL_BASE = IO_PHYS + 0x04414000, VOTE_BASE = IO_PHYS + 0x04500000, + DBG_TRACKER_BASE = IO_PHYS + 0x04780000, + INFRA_TRACKER_BASE = IO_PHYS + 0x047A0000, UART0_BASE = IO_PHYS + 0x06000000, SPI0_BASE = IO_PHYS + 0x06110000, SPI1_BASE = IO_PHYS + 0x06130000, @@ -113,11 +132,13 @@ PERI_PAR_BCRM_BASE = IO_PHYS + 0x06610000, PERICFG_AO_SEC_BASE = IO_PHYS + 0x06630000, PERICFG_AO_BASE = IO_PHYS + 0x06640000, + PERI_PAR_AO_DEBUG_BASE = IO_PHYS + 0x06680000, SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00, SSUSB_SIF_BASE = IO_PHYS + 0x06730300, USB_BUS_BCRM_BASE = IO_PHYS + 0x06781000, UFSHCI_BASE = IO_PHYS + 0x06810000, SSR_TOP_BASE = IO_PHYS + 0x08000000, + APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, VLPCFG_BASE = IO_PHYS + 0x0C001000, SCP_BASE = IO_PHYS + 0x0C004000, SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, @@ -128,7 +149,9 @@ PMIF_SPMI_BASE = IO_PHYS + 0x0C01A000, SPMI_MST_BASE = IO_PHYS + 0x0C01C000, SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, + VLP_AO_DEBUG_BASE = IO_PHYS + 0x0C031000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, + VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, @@ -143,6 +166,7 @@ MMVOTE_CAM_MAIN_R1A_BASE = IO_PHYS + 0x1A000000, MMVOTE_CCU_MAIN_BASE = IO_PHYS + 0x1C800000, MMVOTE_DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x1E800000, + MMUP_AO_DEBUG_BASE = IO_PHYS + 0x21A22000, MMVOTE_BASE = IO_PHYS + 0x21B00000, MMPC_BASE = IO_PHYS + 0x21B50000, MMSYS_CONFIG_BASE = IO_PHYS + 0x22000000, diff --git a/src/soc/mediatek/mt8196/lastbus.c b/src/soc/mediatek/mt8196/lastbus.c new file mode 100644 index 0000000..6e2f032 --- /dev/null +++ b/src/soc/mediatek/mt8196/lastbus.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/lastbus_v2.h> + +static const struct lastbus_monitor monitors[] = { + { + .name = "debug_ctrl_ao_DBGSYS_AO", + .base = DBGSYS_AO_DEBUG_BASE, + .num_ports = 1, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_AO", + .base = APINFRA_IO_AO_DEBUG_BASE, + .num_ports = 37, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_CTRL_AO", + .base = APINFRA_IO_CTRL_AO_DEBUG_BASE, + .num_ports = 3, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_DRAMC_AO", + .base = APINFRA_DRAMC_AO_DEBUG_BASE, + .num_ports = 11, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_EMI_AO", + .base = APINFRA_EMI_AO_DEBUG_BASE, + .num_ports = 15, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_BIG4_AO", + .base = APINFRA_BIG4_AO_DEBUG_BASE, + .num_ports = 13, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_INTF_AO", + .base = APINFRA_IO_INTF_AO_DEBUG_BASE, + .num_ports = 33, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_INTF_AO", + .base = APINFRA_MEM_INTF_AO_DEBUG_BASE, + .num_ports = 42, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_INT_AO", + .base = APINFRA_INT_AO_DEBUG_BASE, + .num_ports = 7, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MMU_AO", + .base = APINFRA_MMU_AO_DEBUG_BASE, + .num_ports = 8, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_SLB_AO", + .base = APINFRA_SLB_AO_DEBUG_BASE, + .num_ports = 8, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_AO", + .base = APINFRA_MEM_AO_DEBUG_BASE, + .num_ports = 26, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_CTRL_AO", + .base = APINFRA_MEM_CTRL_AO_DEBUG_BASE, + .num_ports = 2, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_SSR_AO", + .base = APINFRA_SSR_AO_DEBUG_BASE, + .num_ports = 5, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_NEMI_AO", + .base = NEMI_AO_DEBUG_BASE, + .num_ports = 18, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_SEMI_AO", + .base = SEMI_AO_DEBUG_BASE, + .num_ports = 18, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_EMI_INFRA_AO", + .base = EMI_INFRA_AO_DEBUG_BASE, + .num_ports = 70, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_PERI_PAR_AO", + .base = PERI_PAR_AO_DEBUG_BASE, + .num_ports = 27, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_VLP_AO", + .base = VLP_AO_DEBUG_BASE, + .num_ports = 17, + .bus_freq_mhz = 156, + }, + { + .name = "debug_ctrl_ao_MMUP_AO", + .base = MMUP_AO_DEBUG_BASE, + .num_ports = 25, + .bus_freq_mhz = 728, + }, +}; + +const struct lastbus_config lastbus_cfg = { + .latch_platform = "MT8196", + .timeout_ms = 200, + .timeout_type = 0, + .num_used_monitors = ARRAY_SIZE(monitors), + .monitors = monitors, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/84928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Gerrit-Change-Number: 84928 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/rauru: Pass reset gpio parameter to BL31
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84933?usp=email ) ( 9 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/rauru: Pass reset gpio parameter to BL31 ...................................................................... mb/google/rauru: Pass reset gpio parameter to BL31 Pass the reset gpio parameter to BL31 to support SoC reset. BUG=b:334753311 TEST=run reboot command Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84933 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rauru/mainboard.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/mainboard/google/rauru/mainboard.c b/src/mainboard/google/rauru/mainboard.c index a2d725a..c2d24e1 100644 --- a/src/mainboard/google/rauru/mainboard.c +++ b/src/mainboard/google/rauru/mainboard.c @@ -2,6 +2,7 @@ #include <device/device.h> #include <gpio.h> +#include <soc/bl31.h> #include <soc/pcie.h> #include <soc/usb.h> @@ -23,6 +24,9 @@ { setup_usb_host(); power_on_fpmcu(); + + if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE)) + register_reset_to_bl31(GPIO_AP_EC_WARM_RST_REQ.id, true); } static void mainboard_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/84933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Gerrit-Change-Number: 84933 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com>

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coreboot-gerrit November 2024