coreboot-gerrit November 2024

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[S] Change in coreboot[main]: mb/google/rauru: Configure TPM
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84932?usp=email ) Change subject: mb/google/rauru: Configure TPM ...................................................................... mb/google/rauru: Configure TPM 1. Add Google Ti50 TPM support 2. Configure I2C speed to I2C_SPEED_FAST_PLUS 3. Pass GPIO_GSC_AP_INT_ODL to the payload 4. Configure IRQ type to IRQ_TYPE_EDGE_RISING for now BUG=b:317009620 TEST=build pass, boot ok and there is no CR50 TPM timeout log Pass log: [INFO ] Probing TPM I2C: done! DID_VID 0x504a6666 [DEBUG] GSC TPM 2.0 (i2c 1:0x50 id 0x504a) Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84932 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h 4 files changed, 26 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index c7483e2..da6d99c 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -11,7 +11,6 @@ config VBOOT select VBOOT_VBNV_FLASH select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_MOCK_SECDATA config BOARD_SPECIFIC_OPTIONS def_bool y @@ -25,6 +24,9 @@ select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_SPI + select I2C_TPM if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select TPM_GOOGLE_TI50 if VBOOT config MAINBOARD_DIR string @@ -43,4 +45,13 @@ config EC_GOOGLE_CHROMEEC_SPI_BUS hex default 0x1 + +config DRIVER_TPM_I2C_BUS + hex + default 0x1 + +config DRIVER_TPM_I2C_ADDR + hex + default 0x50 + endif diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index bbebf52..6e0a4ee 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,8 @@ #include <bootblock_common.h> #include <gpio.h> +#include <soc/gpio.h> +#include <soc/i2c.h> #include <soc/pcie.h> #include <soc/spi.h> @@ -17,8 +19,10 @@ if (CONFIG(PCI)) mtk_pcie_pre_init(); + mtk_i2c_bus_init(CONFIG_DRIVER_TPM_I2C_BUS, I2C_SPEED_FAST_PLUS); mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); + gpio_eint_configure(GPIO_GSC_AP_INT_ODL, IRQ_TYPE_EDGE_RISING); } diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index a24995f..de36114 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <boot/coreboot_tables.h> +#include <drivers/tpm/cr50.h> #include <gpio.h> +#include <console/console.h> #include "gpio.h" void setup_chromeos_gpios(void) { gpio_input(GPIO_EC_AP_INT_ODL); + gpio_input(GPIO_GSC_AP_INT_ODL); gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_BEEP_ON_OD, 0); @@ -24,6 +27,12 @@ { GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" }, { GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" }, { GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" }, + { GPIO_GSC_AP_INT_ODL.id, ACTIVE_HIGH, -1, "TPM interrupt" }, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); } + +int cr50_plat_irq_status(void) +{ + return gpio_eint_poll(GPIO_GSC_AP_INT_ODL); +} diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index b8c9a82..d97b38d 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -7,6 +7,7 @@ #define GPIO_BEEP_ON_OD GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) +#define GPIO_GSC_AP_INT_ODL GPIO(EINT18) #define GPIO_EC_AP_INT_ODL GPIO(EINT19) #define GPIO_XHCI_INIT_DONE GPIO(EINT28) #define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) -- To view, visit https://review.coreboot.org/c/coreboot/+/84932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I582f010a9033ccb1771dbb3ccab9f16314628796 Gerrit-Change-Number: 84932 Gerrit-PatchSet: 15 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com>

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[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
by Yidi Lin (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Crystal Guo, Yu-Ping Wu. Yidi Lin has posted comments on this change by Crystal Guo. ( https://review.coreboot.org/c/blobs/+/85110?usp=email ) Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/blobs/+/85110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Gerrit-Change-Number: 85110 Gerrit-PatchSet: 3 Gerrit-Owner: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:46:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
by Crystal Guo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Crystal Guo has posted comments on this change by Crystal Guo. ( https://review.coreboot.org/c/blobs/+/85110?usp=email ) Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration ...................................................................... Patch Set 3: (1 comment) File soc/mediatek/mt8196/dram_release_notes.txt: https://review.coreboot.org/c/blobs/+/85110/comment/d581b113_487f31bf?usp=e… : PS2, Line 3: . > from ChromeOS version ... Done -- To view, visit https://review.coreboot.org/c/blobs/+/85110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Gerrit-Change-Number: 85110 Gerrit-PatchSet: 3 Gerrit-Owner: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:45:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
by Crystal Guo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Crystal Guo, Yidi Lin. Hello Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/blobs/+/85110?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration ...................................................................... soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration This blob includes both full calibration and fast calibration flow. BUG=b:317009620 TEST=DRAM calibration pass. Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> --- M soc/mediatek/mt8196/README.md A soc/mediatek/mt8196/dram.elf A soc/mediatek/mt8196/dram.elf.md5 A soc/mediatek/mt8196/dram_release_notes.txt 4 files changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/blobs refs/changes/10/85110/3 -- To view, visit https://review.coreboot.org/c/blobs/+/85110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Gerrit-Change-Number: 85110 Gerrit-PatchSet: 3 Gerrit-Owner: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in blobs[main]: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Crystal Guo, Yidi Lin. Yu-Ping Wu has posted comments on this change by Crystal Guo. ( https://review.coreboot.org/c/blobs/+/85110?usp=email ) Change subject: soc/mediatek/mt8196: Add dram.elf version 0.3.0 for DRAM calibration ...................................................................... Patch Set 2: (1 comment) File soc/mediatek/mt8196/dram_release_notes.txt: https://review.coreboot.org/c/blobs/+/85110/comment/e1ff39e2_48d57424?usp=e… : PS2, Line 3: . from ChromeOS version ... -- To view, visit https://review.coreboot.org/c/blobs/+/85110?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I726f1cdadb99ba160cf20e65a6eacaa81998d043 Gerrit-Change-Number: 85110 Gerrit-PatchSet: 2 Gerrit-Owner: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:39:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Amanda Hwang, Dtrain Hsu, Paul Menzel, Pranava Y N, Subrata Banik. Ian Feng has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85037?usp=email ) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... Patch Set 8: (7 comments) File src/mainboard/google/fatcat/Kconfig: https://review.coreboot.org/c/coreboot/+/85037/comment/836cf226_5b870911?us… : PS6, Line 71: select BOARD_GOOGLE_BASEBOARD_FATCAT > Maybe mention this too in the commit message. Done File src/mainboard/google/fatcat/variants/francka/gpio.c: https://review.coreboot.org/c/coreboot/+/85037/comment/eb765b59_33929e2d?us… : PS6, Line 62: ISH_GP_1_SNSR_HDR > Please modify the pin name. Done https://review.coreboot.org/c/coreboot/+/85037/comment/7d7c02b6_3919063d?us… : PS6, Line 62: ISH_GP_1_SNSR_HDR > Please modify the pin name. Done https://review.coreboot.org/c/coreboot/+/85037/comment/35229b98_45c73ffe?us… : PS6, Line 219: used_R > Should it delete _R? Done https://review.coreboot.org/c/coreboot/+/85037/comment/146313cf_17eba20e?us… : PS6, Line 219: used_R > Should it delete _R? Done https://review.coreboot.org/c/coreboot/+/85037/comment/1509d8f9_c0f7e4ee?us… : PS6, Line 390: /* GPP_V13: GPP_V13_CATERR_N */ : PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), : /* GPP_V14: GPP_V14_FORCEPR_N */ : PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), : /* GPP_V15: GPP_V15_THERMTRIP_N */ : PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), > Please check settings with EE, I didn't see the settings in the GPIO table. Done https://review.coreboot.org/c/coreboot/+/85037/comment/7463c2df_87f919b4?us… : PS6, Line 390: /* GPP_V13: GPP_V13_CATERR_N */ : PAD_CFG_NF(GPP_V13, NONE, DEEP, NF1), : /* GPP_V14: GPP_V14_FORCEPR_N */ : PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), : /* GPP_V15: GPP_V15_THERMTRIP_N */ : PAD_CFG_NF(GPP_V15, NONE, DEEP, NF1), > Please check settings with EE, I didn't see the settings in the GPIO table. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 8 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 02:38:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Amanda Hwang, Ian Feng, Pranava Y N, Subrata Banik. Hello Amanda Hwang, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85037?usp=email to look at the new patch set (#8). Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings 1. Configure GPIOs according to schematics_20241112. 2. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka. 3. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka. 4. Set TMP I2C bus to 0x01 for francka. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 5 files changed, 472 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 8 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Amanda Hwang, Ian Feng, Pranava Y N, Subrata Banik. Hello Amanda Hwang, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85037?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+2 by Amanda Hwang, Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings 1. Configure GPIOs according to schematics_20241112. 2. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka. 3. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 5 files changed, 472 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 7 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Map LPDDR type to mem_chip_type
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85099?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Map LPDDR type to mem_chip_type ...................................................................... soc/mediatek/mt8196: Map LPDDR type to mem_chip_type Implement map_to_lpddr_dram_type to convert MT8196 specific DRAM_DRAM_TYPE_T values to mem_chip_type. BUG=b:357743097 TEST=Firmware shows the following log: LPDDR5 chan0(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan0(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan1(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan2(x16) rank1: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank0: density 12288mbits x16, MF 06 rev 0800 LPDDR5 chan3(x16) rank1: density 12288mbits x16, MF 06 rev 0800 Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85099 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/dramc_soc.h A src/soc/mediatek/mt8196/memory.c 3 files changed, 37 insertions(+), 1 deletion(-) Approvals: Yu-Ping Wu: Looks good to me, approved Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index b0eb693..559b8a1 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -24,7 +24,7 @@ romstage-y += ../common/emi.c romstage-y += irq2axi.c romstage-y += l2c_ops.c -romstage-y += ../common/memory.c +romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c diff --git a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h index dde00c2..c01daf5 100644 --- a/src/soc/mediatek/mt8196/include/soc/dramc_soc.h +++ b/src/soc/mediatek/mt8196/include/soc/dramc_soc.h @@ -43,6 +43,23 @@ IMP_DRV_MAX, } DRAM_IMP_DRV_T; +typedef enum { + TYPE_DDR1 = 1, + TYPE_DDR2, + TYPE_DDR3, + TYPE_DDR4, + TYPE_DDR5, + TYPE_LPDDR2, + TYPE_LPDDR3, + TYPE_PCDDR3, + TYPE_LPDDR4, + TYPE_LPDDR4X, + TYPE_LPDDR4P, + TYPE_LPDDR5, + TYPE_LPDDR5X, + TYPE_MAX, +} DRAM_DRAM_TYPE_T; + #define DRAM_DFS_SHU_MAX DRAM_DFS_SRAM_MAX #define DQS_NUMBER_LP5 2 #define DQ_DATA_WIDTH_LP5 16 diff --git a/src/soc/mediatek/mt8196/memory.c b/src/soc/mediatek/mt8196/memory.c new file mode 100644 index 0000000..2689e5a --- /dev/null +++ b/src/soc/mediatek/mt8196/memory.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <commonlib/bsd/mem_chip_info.h> +#include <soc/emi.h> + +enum mem_chip_type map_to_lpddr_dram_type(uint16_t lpddr_type) +{ + switch (lpddr_type) { + case TYPE_LPDDR4X: + return MEM_CHIP_LPDDR4X; + case TYPE_LPDDR5: + return MEM_CHIP_LPDDR5; + case TYPE_LPDDR5X: + return MEM_CHIP_LPDDR5X; + default: + return MEM_CHIP_UNDEFINED; + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85099?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63ce238ff0fbcdde9020a7cf4fee2e29d6decf37 Gerrit-Change-Number: 85099 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mem_chip_info: Add LPDDR5 enums to mem_chip_type
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85034?usp=email ) Change subject: mem_chip_info: Add LPDDR5 enums to mem_chip_type ...................................................................... mem_chip_info: Add LPDDR5 enums to mem_chip_type Add MEM_CHIP_LPDDR5 and MEM_CHIP_LPDDR5X to mem_chip_type enum. BUG=b:357743097 TEST=build pass Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Signed-off-by: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85034 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h index 5d4d37c..f191cc7 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h +++ b/src/commonlib/bsd/include/commonlib/bsd/mem_chip_info.h @@ -6,11 +6,15 @@ #include <stddef.h> enum mem_chip_type { + MEM_CHIP_UNDEFINED = 0x00, MEM_CHIP_DDR3 = 0x30, MEM_CHIP_LPDDR3 = 0x38, MEM_CHIP_DDR4 = 0x40, MEM_CHIP_LPDDR4 = 0x48, MEM_CHIP_LPDDR4X = 0x49, + MEM_CHIP_DDR5 = 0x50, + MEM_CHIP_LPDDR5 = 0x58, + MEM_CHIP_LPDDR5X = 0x59, }; #define MEM_CHIP_STRUCT_VERSION 0 /* Hopefully we'll never have to bump this... */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85034?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic947932bacf9bef53f275685b2616601d0a6823c Gerrit-Change-Number: 85034 Gerrit-PatchSet: 6 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Crystal Guo <crystal.guo(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit November 2024