coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR
by Jérémy Compostella (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email ) Change subject: soc/intel/xeon_sp: Reserve PRMRR ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: Shouldn't this CL and the following be in a different order ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Gerrit-Change-Number: 84314 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 16:56:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/lenovo/m900_tiny: Add option to enable Intel PTT fTPM
by Michał Kopeć (Code Review) 12 Nov '24

12 Nov '24

Michał Kopeć has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84814?usp=email ) Change subject: mb/lenovo/m900_tiny: Add option to enable Intel PTT fTPM ...................................................................... Abandoned I've found a way to update the onboard TPM 1.2 to 2.0 firmware, so this change is not needed and actually causes issues with the discrete TPM 2.0 -- To view, visit https://review.coreboot.org/c/coreboot/+/84814?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d55d4579707123a1e31cf0459ff6b5845b6ea46 Gerrit-Change-Number: 84814 Gerrit-PatchSet: 5 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: cpu/x86/mtrr: Use fls/ffs from lib.h
by Jérémy Compostella (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Shuo Liu. Jérémy Compostella has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85104?usp=email ) Change subject: cpu/x86/mtrr: Use fls/ffs from lib.h ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/85104/comment/cee8f14b_5f1f0cc3?us… : PS5, Line 80: #include <lib.h> nit: I know this is not an official rule but most of the time but the inclusion follows the alphabetical order and I personally like perpetuating it as it helps find a particular inclusion in a long list or help detect unnecessary double inclusion. -- To view, visit https://review.coreboot.org/c/coreboot/+/85104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093 Gerrit-Change-Number: 85104 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 16:53:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: build system: define and use an OS-specific sed
by Jérémy Compostella (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Singer, Idwer Vollering, Martin L Roth. Jérémy Compostella has posted comments on this change by Idwer Vollering. ( https://review.coreboot.org/c/coreboot/+/84807?usp=email ) Change subject: build system: define and use an OS-specific sed ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I found other occurrences where sed is being used, shouldn't they also be addressed ? ``` ./payloads/external/depthcharge/Makefile ./payloads/external/edk2/Makefile ./payloads/external/iPXE/Makefile ./payloads/external/SeaBIOS/seabios/scripts/kconfig/Makefile ./payloads/libpayload/curses/PDCurses/Makefile.in ./payloads/libpayload/Makefile.mk ./src/arch/arm64/Makefile.mk ./src/commonlib/storage/Makefile.mk ./src/lib/Makefile.mk ./src/sbom/Makefile.mk ./src/soc/amd/common/Makefile.mk ./src/soc/intel/baytrail/Makefile.mk ./src/soc/intel/broadwell/Makefile.mk ./src/soc/intel/common/block/fast_spi/Makefile.mk ./src/vendorcode/amd/opensil/Makefile.mk ./util/cbfstool/lz4/lib/Makefile ./util/docker/Makefile ./util/kconfig/Makefile.mk ./util/nvidia/cbootimage/src/Makefile.am ``` Note: In addition, some third party projects want to take advantage of it. ``` ./3rdparty/arm-trusted-firmware/Makefile ./3rdparty/ffs/ffs/test/Makefile ./3rdparty/libgfxinit/common/Makefile.inc ./3rdparty/libhwbase/common/Makefile.inc ./3rdparty/libhwbase/Makefile ./3rdparty/libhwbase/Makefile.proof ./3rdparty/open-power-signing-utils/Makefile.am ./3rdparty/opensbi/Makefile ./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Makefile ./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Source/C/Common/Makefile ./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Source/C/Makefile ./3rdparty/stm/Stm/StmPkg/EdkII/BaseTools/Source/Python/Makefile ./3rdparty/vboot/Makefile ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84807?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia7c2d188f1deee67ffb2e0f4eaea4212fa2f98f0 Gerrit-Change-Number: 84807 Gerrit-PatchSet: 1 Gerrit-Owner: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 16:50:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data
by Felix Held (Code Review) 12 Nov '24

12 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85059?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data ...................................................................... drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data The basic flash parameter table described in JESB216F can be up to 23 DWORDs (92 bytes) long which is larger than the 47 byte SPI data buffer in the AMD SoCs which also contains the data from the command buffer except the command byte. TEST=Calling 'read_sfdp_data' with a data length of 256 bytes which is larger than the buffer of the AMD SPI host controller now works and returns the SFDP data expected from the W74M12JW SPI flash: 0x00: 53 46 44 50 06 01 02 ff 00 06 01 10 80 00 00 ff SFDP............ 0x10: 84 00 01 02 d0 00 00 ff 03 00 01 02 f0 00 00 ff ................ 0x20: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ ... 0x80: e5 20 f9 ff ff ff ff 07 44 eb 08 6b 08 3b 42 bb . ......D..k.;B. 0x90: fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52 ..........@.. .R 0xa0: 10 d8 00 00 36 02 a6 00 82 ea 14 c9 e9 63 76 33 ....6........cv3 0xb0: 7a 75 7a 75 f7 bd d5 5c 19 f7 4d ff e9 30 f8 80 zuzu...\..M..0.. 0xc0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xd0: 00 00 f0 ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xe0: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ................ 0xf0: 38 9b 96 f0 a5 ad a5 ff ff ff ff ff ff ff ff ff 8............... Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85059 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/drivers/spi/spi_flash_sfdp.c 1 file changed, 21 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c index 46117bc..94509fd 100644 --- a/src/drivers/spi/spi_flash_sfdp.c +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -10,8 +10,6 @@ /* * Assumptions (not) made in the code: * - code is supposed to be endian-safe - * - requested SFDP data blocks are small enough to fit into the SPI controller buffer, so no - * spi_crop_chunk calls are needed * * Limitations: * - only legacy access protocol supported: @@ -24,20 +22,35 @@ #define CMD_READ_SFDP 0x5a +static void read_sfdp_data_update_buffer_offset(uint8_t *buf_cmd, uint32_t offset) +{ + buf_cmd[1] = offset >> 16 & 0xff; + buf_cmd[2] = offset >> 8 & 0xff; + buf_cmd[3] = offset >> 0 & 0xff; +} + static enum cb_err read_sfdp_data(const struct spi_flash *flash, uint32_t offset, size_t len, uint8_t *buf) { uint8_t buf_cmd[5]; buf_cmd[0] = CMD_READ_SFDP; - buf_cmd[1] = offset >> 16 & 0xff; - buf_cmd[2] = offset >> 8 & 0xff; - buf_cmd[3] = offset >> 0 & 0xff; + /* the read offset in buf_cmd[1..3] gets written in + read_sfdp_data_update_buffer_offset */ buf_cmd[4] = 0; /* dummy byte */ - /* TODO: use spi_crop_chunk to break up larger transfers */ - if (spi_flash_cmd_multi(&flash->spi, buf_cmd, sizeof(buf_cmd), buf, len)) - return CB_ERR; + uint8_t *data = buf; + + /* split data transfers into chunks that each fit into the SPI controller's buffer */ + while (len) { + uint32_t xfer_len = spi_crop_chunk(&flash->spi, sizeof(buf_cmd), len); + read_sfdp_data_update_buffer_offset(buf_cmd, offset); + if (spi_flash_cmd_multi(&flash->spi, buf_cmd, sizeof(buf_cmd), data, xfer_len)) + return CB_ERR; + offset += xfer_len; + data += xfer_len; + len -= xfer_len; + } return CB_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Gerrit-Change-Number: 85059 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/spi: add RPMC info to spi_flash struct
by Felix Held (Code Review) 12 Nov '24

12 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85009?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: drivers/spi: add RPMC info to spi_flash struct ...................................................................... drivers/spi: add RPMC info to spi_flash struct Fill 'rpmc_caps' struct inside the 'spi_flash' struct with the RPMC info from the SFDP table. TEST=On a board with a W74M12JW SPI flash chip, the 'rpmc_caps' struct has the expected entries (RPMC available, OP2 extended status as polling method, 4 RPMC counters, OP1 is 0x9b, and OP2 is 0x96). Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85009 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk M src/drivers/spi/spi_flash.c M src/drivers/spi/spi_flash_internal.h A src/drivers/spi/spi_flash_rpmc.c M src/include/spi_flash.h 6 files changed, 56 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved Matt DeVillier: Looks good to me, but someone else must approve diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 72fcec5..5d9698e 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -194,6 +194,12 @@ help Include serial flash discoverable parameters (SFDP) support. +config SPI_FLASH_RPMC + bool + select SPI_FLASH_SFDP + help + Include replay-protected monotonic counter (RPMC) support. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/drivers/spi/Makefile.mk b/src/drivers/spi/Makefile.mk index d873c90..3310b96 100644 --- a/src/drivers/spi/Makefile.mk +++ b/src/drivers/spi/Makefile.mk @@ -32,6 +32,7 @@ $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c $(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c $(1)-$(CONFIG_SPI_FLASH_SFDP) += spi_flash_sfdp.c +$(1)-$(CONFIG_SPI_FLASH_RPMC) += spi_flash_rpmc.c endef $(eval $(call add_spi_stage,bootblock,_EARLY)) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 6ecd29f..b7a024c 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -569,6 +569,11 @@ spi_flash_cmd(&flash->spi, CMD_EXIT_4BYTE_ADDR_MODE, NULL, 0); } + /* TODO: only do this in stages that will need to call those functions? */ + if (CONFIG(SPI_FLASH_RPMC)) { + spi_flash_fill_rpmc_caps(flash); + } + return 0; } diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index 830a178..a30f58f 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -159,4 +159,7 @@ enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, struct sfdp_rpmc_info *rpmc_info); +/* Fill rpmc_caps field in spi_flash struct with RPMC config from SFDP */ +void spi_flash_fill_rpmc_caps(struct spi_flash *flash); + #endif /* SPI_FLASH_INTERNAL_H */ diff --git a/src/drivers/spi/spi_flash_rpmc.c b/src/drivers/spi/spi_flash_rpmc.c new file mode 100644 index 0000000..148e3bb --- /dev/null +++ b/src/drivers/spi/spi_flash_rpmc.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <string.h> +#include <timer.h> +#include <types.h> + +#include "spi_flash_internal.h" + +void spi_flash_fill_rpmc_caps(struct spi_flash *flash) +{ + struct sfdp_rpmc_info rpmc_info; + + flash->rpmc_caps.rpmc_available = false; + + if (spi_flash_get_sfdp_rpmc(flash, &rpmc_info) != CB_SUCCESS) + return; + + if (rpmc_info.monotonic_counter_size != SFDP_RPMC_COUNTER_BITS_32) { + printk(BIOS_WARNING, "RPMC: unexpected counter size\n"); + return; + } + + flash->rpmc_caps.poll_op2_ext_stat = rpmc_info.busy_polling_method == + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS; + flash->rpmc_caps.number_of_counters = rpmc_info.number_of_counters; + flash->rpmc_caps.op1_write_cmd = rpmc_info.op1_write_command; + flash->rpmc_caps.op2_read_cmd = rpmc_info.op2_read_command; + flash->rpmc_caps.rpmc_available = true; +} diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index 7736a94..76c33be 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -95,6 +95,14 @@ struct spi_flash_part_id; +struct spi_flash_rpmc_cap { + bool rpmc_available; + bool poll_op2_ext_stat; + unsigned int number_of_counters; + uint8_t op1_write_cmd; + uint8_t op2_read_cmd; +}; + struct spi_flash { struct spi_slave spi; u8 vendor; @@ -118,6 +126,7 @@ /* If !NULL all protection callbacks exist. */ const struct spi_flash_protection_ops *prot_ops; const struct spi_flash_part_id *part; + struct spi_flash_rpmc_cap rpmc_caps; }; void lb_spi_flash(struct lb_header *header); -- To view, visit https://review.coreboot.org/c/coreboot/+/85009?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a8332bffe93e1691f6fc87c3936025f158f3ab9 Gerrit-Change-Number: 85009 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Felix Held (Code Review) 12 Nov '24

12 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters JESD216F.02 and JESD260 were used as a reference. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/85008 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/drivers/spi/spi_flash_internal.h M src/drivers/spi/spi_flash_sfdp.c 2 files changed, 176 insertions(+), 4 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/drivers/spi/spi_flash_internal.h b/src/drivers/spi/spi_flash_internal.h index d0f32c5..830a178 100644 --- a/src/drivers/spi/spi_flash_internal.h +++ b/src/drivers/spi/spi_flash_internal.h @@ -136,4 +136,27 @@ /* Page Programming Command Set with 0xd8 Sector Erase command. */ extern const struct spi_flash_ops_descriptor spi_flash_pp_0xd8_sector_desc; +struct sfdp_rpmc_info { + bool flash_hardening; + enum { + SFDP_RPMC_COUNTER_BITS_32 = 0, + SFDP_RPMC_COUNTER_BITS_RESERVED = 1, + } monotonic_counter_size; + enum { + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS = 0, + SFDP_RPMC_POLL_READ_STATUS = 1, + } busy_polling_method; + uint8_t number_of_counters; + uint8_t op1_write_command; + uint8_t op2_read_command; + uint64_t update_rate_s; + uint64_t read_counter_polling_delay_us; + uint64_t write_counter_polling_short_delay_us; + uint64_t write_counter_polling_long_delay_us; +}; + +/* Get RPMC information from the SPI flash's SFDP table */ +enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, + struct sfdp_rpmc_info *rpmc_info); + #endif /* SPI_FLASH_INTERNAL_H */ diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c index 807a33be..46117bc 100644 --- a/src/drivers/spi/spi_flash_sfdp.c +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -164,10 +164,9 @@ } } -static inline enum cb_err find_sfdp_parameter_header(const struct spi_flash *flash, - uint16_t table_id, uint16_t *revision, - uint8_t *length_dwords, - uint32_t *table_pointer) +static enum cb_err find_sfdp_parameter_header(const struct spi_flash *flash, uint16_t table_id, + uint16_t *revision, uint8_t *length_dwords, + uint32_t *table_pointer) { enum cb_err stat; uint16_t sfdp_rev; @@ -201,3 +200,153 @@ return CB_ERR; } + +#define SFDP_PARAMETER_ID_RPMC 0xff03 + +#define SFDP_RPMC_TABLE_LENGTH_DWORDS 2 +#define SFDP_RPMC_TABLE_SUPPORTED_MAJOR_REV 1 + +/* RPMC parameter table byte offsets and fields */ +#define SFDP_RPMC_TABLE_CONFIG 0 +#define SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT BIT(0) +#define SFDP_RPMC_TABLE_CONFIG_MONOTONIC_COUNTER_SIZE_BIT BIT(1) +#define SFDP_RPMC_TABLE_CONFIG_BUSY_POLLING_METHOD BIT(2) +#define SFDP_RPMC_TABLE_CONFIG_RESERVED BIT(3) +#define SFDP_RPMC_TABLE_CONFIG_RESERVED_VALUE 0x08 +#define SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_MASK 0xf0 +#define SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_SHIFT 4 +#define SFDP_RPMC_TABLE_RPMC_OP1 1 +#define SFDP_RPMC_TABLE_RPMC_OP2 2 +#define SFDP_RPMC_TABLE_UPDATE_RATE 3 +#define SFDP_RPMC_TABLE_UPDATE_RATE_MASK 0x0f +#define SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_MASK 0xf0 +#define SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_VALUE 0xf0 +#define SFDP_RPMC_TABLE_READ_COUNTER_POLLING_DELAY 4 +#define SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_SHORT_DELAY 5 +#define SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_LONG_DELAY 6 +#define SFDP_RPMC_TABLE_RESERVED_BYTE 7 +#define SFDP_RPMC_TABLE_RESERVED_BYTE_VALUE 0xff + +static uint64_t calc_rpmc_update_rate_s(uint8_t val) +{ + /* val is at most 15, so this won't overflow */ + return 5 * 1 << (val & SFDP_RPMC_TABLE_UPDATE_RATE_MASK); +} + +#define SPDF_RPMC_DELAY_VALUE_MASK 0x1f +#define SPDF_RPMC_DELAY_UNIT_MASK 0x60 +#define SPDF_RPMC_DELAY_UNIT_SHIFT 5 +#define SPDF_RPMC_DELAY_SHORT_UNIT_0_US 1 /* 1us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_1_US 16 /* 16us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_2_US 128 /* 128us */ +#define SPDF_RPMC_DELAY_SHORT_UNIT_3_US 1000 /* 1ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_0_US 1000 /* 1ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_1_US 16000 /* 16ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_2_US 128000 /* 128ms */ +#define SPDF_RPMC_DELAY_LONG_UNIT_3_US 1000000 /* 1s */ + +static uint64_t calc_rpmc_short_delay_us(uint8_t val) +{ + const uint8_t value = val & SPDF_RPMC_DELAY_VALUE_MASK; + const uint8_t shift = (val & SPDF_RPMC_DELAY_UNIT_MASK) >> SPDF_RPMC_DELAY_UNIT_SHIFT; + uint64_t multiplier; + + switch (shift) { + case 0: + multiplier = SPDF_RPMC_DELAY_SHORT_UNIT_0_US; + break; + case 1: + multiplier = SPDF_RPMC_DELAY_SHORT_UNIT_1_US; + break; + case 2: + multiplier = SPDF_RPMC_DELAY_SHORT_UNIT_2_US; + break; + default: + multiplier = SPDF_RPMC_DELAY_SHORT_UNIT_3_US; + break; + } + + return value * multiplier; +} + +static uint64_t calc_rpmc_long_delay_us(uint8_t val) +{ + const uint8_t value = val & SPDF_RPMC_DELAY_VALUE_MASK; + const uint8_t shift = (val & SPDF_RPMC_DELAY_UNIT_MASK) >> SPDF_RPMC_DELAY_UNIT_SHIFT; + uint64_t multiplier; + + switch (shift) { + case 0: + multiplier = SPDF_RPMC_DELAY_LONG_UNIT_0_US; + break; + case 1: + multiplier = SPDF_RPMC_DELAY_LONG_UNIT_1_US; + break; + case 2: + multiplier = SPDF_RPMC_DELAY_LONG_UNIT_2_US; + break; + default: + multiplier = SPDF_RPMC_DELAY_LONG_UNIT_3_US; + break; + } + + return value * multiplier; +} + +enum cb_err spi_flash_get_sfdp_rpmc(const struct spi_flash *flash, + struct sfdp_rpmc_info *rpmc_info) +{ + uint16_t rev; + uint8_t length_dwords; + uint32_t table_pointer; + uint8_t buf[SFDP_RPMC_TABLE_LENGTH_DWORDS * sizeof(uint32_t)]; + + if (find_sfdp_parameter_header(flash, SFDP_PARAMETER_ID_RPMC, &rev, &length_dwords, + &table_pointer) != CB_SUCCESS) + return CB_ERR; + + if (length_dwords != SFDP_RPMC_TABLE_LENGTH_DWORDS) + return CB_ERR; + + if (rev >> 8 != SFDP_RPMC_TABLE_SUPPORTED_MAJOR_REV) { + printk(BIOS_ERR, "Unsupprted major RPMC table revision %#x\n", rev >> 8); + return CB_ERR; + } + + if (read_sfdp_data(flash, table_pointer, sizeof(buf), buf) != CB_SUCCESS) + return CB_ERR; + + if ((buf[SFDP_RPMC_TABLE_CONFIG] & SFDP_RPMC_TABLE_CONFIG_RESERVED) != + SFDP_RPMC_TABLE_CONFIG_RESERVED_VALUE || + (buf[SFDP_RPMC_TABLE_UPDATE_RATE] & SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_MASK) != + SFDP_RPMC_TABLE_UPDATE_RATE_RESERVED_VALUE || + buf[SFDP_RPMC_TABLE_RESERVED_BYTE] != SFDP_RPMC_TABLE_RESERVED_BYTE_VALUE) { + printk(BIOS_ERR, "Unexpected reserved values in RPMC table\n"); + return CB_ERR; + } + + rpmc_info->flash_hardening = !!(buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT); + rpmc_info->monotonic_counter_size = (buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_FLASH_HARDENING_BIT) ? + SFDP_RPMC_COUNTER_BITS_RESERVED : + SFDP_RPMC_COUNTER_BITS_32; + rpmc_info->busy_polling_method = (buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_BUSY_POLLING_METHOD) ? + SFDP_RPMC_POLL_READ_STATUS : + SFDP_RPMC_POLL_OP2_EXTENDED_STATUS; + rpmc_info->number_of_counters = ((buf[SFDP_RPMC_TABLE_CONFIG] & + SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_MASK) >> + SFDP_RPMC_TABLE_CONFIG_NUM_COUNTERS_SHIFT) + 1; + rpmc_info->op1_write_command = buf[SFDP_RPMC_TABLE_RPMC_OP1]; + rpmc_info->op2_read_command = buf[SFDP_RPMC_TABLE_RPMC_OP2]; + rpmc_info->update_rate_s = calc_rpmc_update_rate_s(buf[SFDP_RPMC_TABLE_UPDATE_RATE] & + SFDP_RPMC_TABLE_UPDATE_RATE_MASK); + rpmc_info->read_counter_polling_delay_us = calc_rpmc_short_delay_us( + buf[SFDP_RPMC_TABLE_READ_COUNTER_POLLING_DELAY]); + rpmc_info->write_counter_polling_short_delay_us = calc_rpmc_short_delay_us( + buf[SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_SHORT_DELAY]); + rpmc_info->write_counter_polling_long_delay_us = calc_rpmc_long_delay_us( + buf[SFDP_RPMC_TABLE_WRITE_COUNTER_POLLING_LONG_DELAY]); + return CB_SUCCESS; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add basic SFDP support
by Felix Held (Code Review) 12 Nov '24

12 Nov '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84786?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add basic SFDP support ...................................................................... drivers/spi/spi_flash_sfdp: add basic SFDP support Add basic support for the Serial Flash Discoverable Parameters (SFDP) standard which can be used to discover the parameters to interact with any SPI flash chip that supports this mechanism. This commit adds functionality to find specific SFDP parameter headers and print all SFDP parameter headers, but not to parse any SFDP parameter table. This is a preparation for a follow-up patch that adds support to parse the RPMC SFDP parameter table. Since 'find_sfdp_parameter_header' is only used in the next patch, it's marked as static inline in this commit so that the code still build; the 'inline' keyword will be removed again in that follow-up patch. For now, only the legacy access protocol using single bit SPI transfers is supported, but this should cover most of the SPI NOR flash chips. In any other case, the code will error out. It's also assumed that the SFDP data blocks read from the SPI flash chip are small enough to fit into the SPI host controller buffer and don't need to be broken up into multiple transfers. This limitation will be addressed in a follow-up patch. JESD216F.02 was used as a reference. TEST=On a board with a W74M12JW SPI flash chip, calling 'spi_flash_print_sfdp_headers' prints this on the console output: Manufacturer: ef SF: Detected ef 6018 with sector size 0x1000, total 0x1000000 SF: Exiting 4-byte addressing mode SFDP header found in SPI flash. major rev 0x1, minor rev 0x6, access protocol 0xff, number of headers 3 SFPD header with index 0: table ID 0xff00, major rev 0x1, minor rev 0x6 table pointer 0x80, table length DWORDS 0x10 SFPD header with index 1: table ID 0xff84, major rev 0x1, minor rev 0x0 table pointer 0xd0, table length DWORDS 0x2 SFPD header with index 2: table ID 0xff03, major rev 0x1, minor rev 0x0 table pointer 0xf0, table length DWORDS 0x2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/84786 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com> --- M src/drivers/spi/Kconfig M src/drivers/spi/Makefile.mk A src/drivers/spi/spi_flash_sfdp.c M src/include/spi_flash.h 4 files changed, 212 insertions(+), 0 deletions(-) Approvals: Martin Roth: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/drivers/spi/Kconfig b/src/drivers/spi/Kconfig index 86e609c..72fcec5 100644 --- a/src/drivers/spi/Kconfig +++ b/src/drivers/spi/Kconfig @@ -189,6 +189,11 @@ On some platforms with SPI flashes larger than 16MB, the SPI flash may need to remain in 4-byte addressing mode. +config SPI_FLASH_SFDP + bool + help + Include serial flash discoverable parameters (SFDP) support. + endif # SPI_FLASH config HAVE_EM100PRO_SPI_CONSOLE_SUPPORT diff --git a/src/drivers/spi/Makefile.mk b/src/drivers/spi/Makefile.mk index 97c3d63..d873c90 100644 --- a/src/drivers/spi/Makefile.mk +++ b/src/drivers/spi/Makefile.mk @@ -31,6 +31,7 @@ $(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c $(1)-$(CONFIG_SPI_FLASH_ISSI) += issi.c +$(1)-$(CONFIG_SPI_FLASH_SFDP) += spi_flash_sfdp.c endef $(eval $(call add_spi_stage,bootblock,_EARLY)) diff --git a/src/drivers/spi/spi_flash_sfdp.c b/src/drivers/spi/spi_flash_sfdp.c new file mode 100644 index 0000000..807a33be --- /dev/null +++ b/src/drivers/spi/spi_flash_sfdp.c @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <spi-generic.h> +#include <spi_flash.h> +#include <types.h> + +#include "spi_flash_internal.h" + +/* + * Assumptions (not) made in the code: + * - code is supposed to be endian-safe + * - requested SFDP data blocks are small enough to fit into the SPI controller buffer, so no + * spi_crop_chunk calls are needed + * + * Limitations: + * - only legacy access protocol supported: + * - only NOR flash + * - read SFDP instruction is sufficient and no fetch SFDP instruction needed + * - always 3 byte addresses for SFDP + * - only 1 bit SPI mode supported + * - always 8 dummy cycles after the address is sent +*/ + +#define CMD_READ_SFDP 0x5a + +static enum cb_err read_sfdp_data(const struct spi_flash *flash, uint32_t offset, size_t len, + uint8_t *buf) +{ + uint8_t buf_cmd[5]; + + buf_cmd[0] = CMD_READ_SFDP; + buf_cmd[1] = offset >> 16 & 0xff; + buf_cmd[2] = offset >> 8 & 0xff; + buf_cmd[3] = offset >> 0 & 0xff; + buf_cmd[4] = 0; /* dummy byte */ + + /* TODO: use spi_crop_chunk to break up larger transfers */ + if (spi_flash_cmd_multi(&flash->spi, buf_cmd, sizeof(buf_cmd), buf, len)) + return CB_ERR; + + return CB_SUCCESS; +} + +#define SFDP_HEADER_OFFSET 0 +#define SFDP_HEADER_LEN (2 * sizeof(uint32_t)) +#define SFDP_HEADER_SIGNATURE 0x50444653 /* LE: "SFDP" */ +#define SFDP_HEADER_ACCESS_PROTOCOL_LEGACY 0xff +/* header byte offsets */ +#define SFDP_HEADER_SIGNATURE_0 0 +#define SFDP_HEADER_SIGNATURE_1 1 +#define SFDP_HEADER_SIGNATURE_2 2 +#define SFDP_HEADER_SIGNATURE_3 3 +#define SFDP_HEADER_MINOR_REV 4 +#define SFDP_HEADER_MAJOR_REV 5 +#define SFDP_HEADER_PARAMETER_HEADER_NUMBER 6 +#define SFDP_HEADER_ACCESS_PROTOCOL 7 + +static enum cb_err get_sfdp_header(const struct spi_flash *flash, uint16_t *sfdp_revision, + uint8_t *number_of_parameter_headers, + uint8_t *access_prototcol) +{ + uint8_t buf[SFDP_HEADER_LEN]; + uint32_t signature; + + if (read_sfdp_data(flash, SFDP_HEADER_OFFSET, SFDP_HEADER_LEN, buf) != CB_SUCCESS) + return CB_ERR; + + signature = buf[SFDP_HEADER_SIGNATURE_0] | buf[SFDP_HEADER_SIGNATURE_1] << 8 | + buf[SFDP_HEADER_SIGNATURE_2] << 16 | buf[SFDP_HEADER_SIGNATURE_3] << 24; + *sfdp_revision = buf[SFDP_HEADER_MINOR_REV] | buf[SFDP_HEADER_MAJOR_REV] << 8; + *number_of_parameter_headers = buf[SFDP_HEADER_PARAMETER_HEADER_NUMBER] + 1; + *access_prototcol = buf[SFDP_HEADER_ACCESS_PROTOCOL]; + + if (signature != SFDP_HEADER_SIGNATURE) + return CB_ERR; + + /* We make the assumption in the code that the legacy access protocol is used */ + if (*access_prototcol != SFDP_HEADER_ACCESS_PROTOCOL_LEGACY) + return CB_ERR; + + return CB_SUCCESS; +} + +#define SFDP_PARAMETER_HEADER_LEN (2 * sizeof(uint32_t)) +#define SFDP_PARAMETER_HEADER_OFFSET(n) (SFDP_HEADER_OFFSET + SFDP_HEADER_LEN + \ + n * SFDP_PARAMETER_HEADER_LEN) +/* parameter header byte offsets */ +#define SFDP_PARAMETER_HEADER_ID_LSB 0 +#define SFDP_PARAMETER_HEADER_MINOR_REV 1 +#define SFDP_PARAMETER_HEADER_MAJOR_REV 2 +#define SFDP_PARAMETER_HEADER_LENGTH_DWORDS 3 +#define SFDP_PARAMETER_HEADER_POINTER_0 4 +#define SFDP_PARAMETER_HEADER_POINTER_1 5 +#define SFDP_PARAMETER_HEADER_POINTER_2 6 +#define SFDP_PARAMETER_HEADER_ID_MSB 7 + +/* get_sfdp_parameter_header_by_index must be called with a valid index */ +static enum cb_err get_sfdp_parameter_header_by_index(const struct spi_flash *flash, + uint8_t index, uint16_t *id, + uint16_t *revision, + uint8_t *length_dwords, + uint32_t *table_pointer) +{ + uint8_t buf[SFDP_PARAMETER_HEADER_LEN]; + + if (read_sfdp_data(flash, SFDP_PARAMETER_HEADER_OFFSET(index), + SFDP_PARAMETER_HEADER_LEN, buf) != CB_SUCCESS) + return CB_ERR; + + *id = buf[SFDP_PARAMETER_HEADER_ID_LSB] | buf[SFDP_PARAMETER_HEADER_ID_MSB] << 8; + *revision = buf[SFDP_PARAMETER_HEADER_MINOR_REV] | + buf[SFDP_PARAMETER_HEADER_MAJOR_REV] << 8; + *length_dwords = buf[SFDP_PARAMETER_HEADER_LENGTH_DWORDS]; + *table_pointer = buf[SFDP_PARAMETER_HEADER_POINTER_0] | + buf[SFDP_PARAMETER_HEADER_POINTER_1] << 8 | + buf[SFDP_PARAMETER_HEADER_POINTER_2] << 16; + + /* the parameter table pointer byte address must be DWORD-aligned */ + if (!IS_ALIGNED(*table_pointer, sizeof(uint32_t))) + return CB_ERR; + + /* TODO: check id validity? */ + + return CB_SUCCESS; +} + +void spi_flash_print_sfdp_headers(const struct spi_flash *flash) +{ + enum cb_err stat; + uint16_t sfdp_rev; + uint8_t param_header_count; + uint8_t access_protocol; + + if (get_sfdp_header(flash, &sfdp_rev, &param_header_count, &access_protocol) != + CB_SUCCESS) { + printk(BIOS_ERR, "Failed to read SFDP header from SPI flash\n"); + return; + } + + printk(BIOS_DEBUG, "SFDP header found in SPI flash.\n"); + printk(BIOS_DEBUG, "major rev %#x, minor rev %#x, access protocol %#x, " + "number of headers %d\n", sfdp_rev >> 8, sfdp_rev & 0xff, access_protocol, + param_header_count); + + uint16_t tbl_id; + uint16_t tbl_rev; + uint8_t tbl_len_dwords; + uint32_t tbl_pointer; + + for (unsigned int i = 0; i < param_header_count; i++) { + stat = get_sfdp_parameter_header_by_index(flash, i, &tbl_id, &tbl_rev, + &tbl_len_dwords, &tbl_pointer); + + if (stat == CB_SUCCESS) { + printk(BIOS_DEBUG, "SFPD header with index %d:\n", i); + printk(BIOS_DEBUG, " table ID %#x, major rev %#x, minor rev %#x\n", + tbl_id, tbl_rev >> 8, tbl_rev & 0xff); + printk(BIOS_DEBUG, " table pointer %#x, table length DWORDS %#x\n", + tbl_pointer, tbl_len_dwords); + } else { + printk(BIOS_ERR, "Cound't read SFPD header with index %d.\n", i); + } + } +} + +static inline enum cb_err find_sfdp_parameter_header(const struct spi_flash *flash, + uint16_t table_id, uint16_t *revision, + uint8_t *length_dwords, + uint32_t *table_pointer) +{ + enum cb_err stat; + uint16_t sfdp_rev; + uint8_t param_header_count; + uint8_t access_protocol; + + if (get_sfdp_header(flash, &sfdp_rev, &param_header_count, &access_protocol) != + CB_SUCCESS) + return CB_ERR; + + /* TODO: add version check? */ + + uint16_t tbl_id; + uint16_t tbl_rev; + uint8_t tbl_len_dwords; + uint32_t tbl_pointer; + + for (unsigned int i = 0; i < param_header_count; i++) { + stat = get_sfdp_parameter_header_by_index(flash, i, &tbl_id, &tbl_rev, + &tbl_len_dwords, &tbl_pointer); + + if (stat == CB_SUCCESS && tbl_id == table_id) { + *revision = tbl_rev; + *length_dwords = tbl_len_dwords; + *table_pointer = tbl_pointer; + return CB_SUCCESS; + } + } + + printk(BIOS_WARNING, "Cound't find SFPD header with table ID %#x.\n", table_id); + + return CB_ERR; +} diff --git a/src/include/spi_flash.h b/src/include/spi_flash.h index e0d5b2b..7736a94 100644 --- a/src/include/spi_flash.h +++ b/src/include/spi_flash.h @@ -249,4 +249,7 @@ */ uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table); +/* Print the SFDP headers read from the SPI flash */ +void spi_flash_print_sfdp_headers(const struct spi_flash *flash); + #endif /* _SPI_FLASH_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5a1706acf7d60fd64292e8f0677992ab4aebf46a Gerrit-Change-Number: 84786 Gerrit-PatchSet: 12 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data
by Matt DeVillier (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Held. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85059?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: use spi_crop_chunk when reading SFDP data ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85059?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia602a54566c9e9cffaebc813ee493254d966e9e4 Gerrit-Change-Number: 85059 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 15:23:58 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters
by Matt DeVillier (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Held, Martin Roth. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/85008?usp=email ) Change subject: drivers/spi/spi_flash_sfdp: add SFDP support to get RPMC parameters ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a1f7a5d16dd3ca6c8263b617ae9c21184b6a5b9 Gerrit-Change-Number: 85008 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 15:23:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024