coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: soc/intel/alderlake: Use CSE sync in ramstage config
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85108?usp=email ) Change subject: soc/intel/alderlake: Use CSE sync in ramstage config ...................................................................... soc/intel/alderlake: Use CSE sync in ramstage config This patch updates the eSOL rendering logic to use the SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option instead of SOC_INTEL_CSE_LITE_SKU. The SOC_INTEL_CSE_LITE_SKU config option was incorrectly used to determine whether to render eSOL during ramstage. The SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE config option specifically indicates whether CSE synchronization is performed during ramstage, making it a more appropriate choice for this purpose. This change ensures that eSOL is rendered correctly during ramstage on platforms that require CSE synchronization. TEST=Able to render eSOL during ramstage for google/trulo. Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/85108/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fc9721c..c98ce10 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -439,7 +439,7 @@ * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take * < 1-minute hence, let's inform the end user with an on-screen text message. */ - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) { if (esol_required) { name = "memory training and CSE update"; } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/85108?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0dd335d5653d774bb5a2e6d7b65831bba080f272 Gerrit-Change-Number: 85108 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Karthik Ramasubramanian, Kenneth Chan. Ren Kuo has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85107?usp=email ) Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85107/comment/d093abc3_b2d33073?us… : PS1, Line 9: The current WWAN(LTE) does not require any sar setting from RF team suggestion, > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. https://review.coreboot.org/c/coreboot/+/85107/comment/bc874dc8_c6a7cc02?us… : PS1, Line 11: To reserve the extendibility, add the fw_config DB_1A_LTE_SAR in field DB_USB: > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 08:19:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Karthik Ramasubramanian, Kenneth Chan. Hello Karthik Ramasubramanian, Kenneth Chan, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85107?usp=email to look at the new patch set (#2). Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor The current WWAN(LTE) does not require any sar setting from RF team's suggestion, and sar sensor will be remvoed from DVT schematic. To reserve the extendibility, add the fw_config DB_1A_LTE_SAR: field DB_USB 11 12 option DB_1A 0 (None LTE) option DB_1A_LTE 1 (LTE without sar sensor) option DB_1A_LTE_SAR 2 (LTE with sar sensor) end Base on the fw_config to enable/disable to related functions: 0)Disable WWAN and Sar if DB_USB = DB_1A 1)Enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE 2)Enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR BUG=b:375341992 TEST=Build and verify on jubilant by fw_config ls -l /sys/bus/i2c/devices i2cdetect -y -r Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/smihandler.c M src/mainboard/google/brox/variants/jubilant/variant.c 5 files changed, 34 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/85107/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Ren Kuo (Code Review) 12 Nov '24

12 Nov '24

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85107?usp=email ) Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor The current WWAN(LTE) does not require any sar setting from RF team suggestion, and sar sensor will be remvoed from DVT schematic. To reserve the extendibility, add the fw_config DB_1A_LTE_SAR in field DB_USB: field DB_USB 11 12 option DB_1A 0 (None LTE) option DB_1A_LTE 1 (LTE without sar sensor) option DB_1A_LTE_SAR 2 (LTE with sar sensor) end Base on the fw_config to disable unused WWAN Sar sensor's realted GPIOs: 0)Disable WWAN and Sar if DB_USB = DB_1A 1)enable WWAN and disable sar sensor if DB_USB = DB_1A_LTE 2)enable WWAN and Sar sensor if DB_USB = DB_1A_LTE_SAR BUG=b:375341992 TEST=Build and verify on jubilant by fw_config ls -l /sys/bus/i2c/devices i2cdetect -y -r Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/fw_config.c M src/mainboard/google/brox/variants/jubilant/overridetree.cb M src/mainboard/google/brox/variants/jubilant/smihandler.c M src/mainboard/google/brox/variants/jubilant/variant.c 5 files changed, 34 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/85107/1 diff --git a/src/mainboard/google/brox/variants/jubilant/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/Makefile.mk index bb7543b..071de2b 100644 --- a/src/mainboard/google/brox/variants/jubilant/Makefile.mk +++ b/src/mainboard/google/brox/variants/jubilant/Makefile.mk @@ -11,4 +11,4 @@ ramstage-y += gpio.c ramstage-y += ramstage.c -smm-y += smihandler.c +smm-y-$(CONFIG_FW_CONFIG) += smihandler.c diff --git a/src/mainboard/google/brox/variants/jubilant/fw_config.c b/src/mainboard/google/brox/variants/jubilant/fw_config.c index df57e15..6d50ca2 100644 --- a/src/mainboard/google/brox/variants/jubilant/fw_config.c +++ b/src/mainboard/google/brox/variants/jubilant/fw_config.c @@ -46,6 +46,21 @@ PAD_NC(GPP_A12, NONE), /* GPP_H23 : WWAN_RST_L */ PAD_NC(GPP_H23, NONE), + /* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L (NC) */ + PAD_NC(GPP_H19, NONE), +}; + +static const struct pad_config lte_sar_disable_pads[] = { + /* GPP_D5 : WWAN_SAR_ODL */ + PAD_NC(GPP_D5, NONE), + /* GPP_S4 : WWAN_WLAN_COEX1 */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 : WWAN_WLAN_COEX2 */ + PAD_NC(GPP_S5, NONE), + /* GPP_F6 : WWAN_WLAN_COEX3 */ + PAD_NC(GPP_F6, NONE), + /* GPP_H19 : SRCCLKREQ4_L ==> SAR1_INT_L (NC) */ + PAD_NC(GPP_H19, NONE), }; static const struct pad_config nvme_disable_pads[] = { @@ -69,11 +84,16 @@ gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads)); } - if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n"); gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); } + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { + printk(BIOS_INFO, "Disable LTE's Sar sensor related GPIO pins by fw_config.\n"); + gpio_configure_pads(lte_sar_disable_pads, ARRAY_SIZE(lte_sar_disable_pads)); + } + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n"); gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index 48cc783..880b3dd 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -10,6 +10,7 @@ field DB_USB 11 12 option DB_1A 0 option DB_1A_LTE 1 + option DB_1A_LTE_SAR 2 end field FPMCU 17 18 option FPMCU_ABSENT 0 @@ -220,6 +221,7 @@ register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port4 on probe DB_USB DB_1A_LTE + probe DB_USB DB_1A_LTE_SAR probe unprovisioned end end @@ -269,6 +271,7 @@ register "type" = "UPC_TYPE_INTERNAL" device ref usb3_port4 on probe DB_USB DB_1A_LTE + probe DB_USB DB_1A_LTE_SAR probe unprovisioned end end @@ -431,7 +434,7 @@ register "input_precharge_resistor_ohms" = "4000" register "input_analog_gain" = "1" device i2c 28 on - probe DB_USB DB_1A_LTE + probe DB_USB DB_1A_LTE_SAR probe unprovisioned end end diff --git a/src/mainboard/google/brox/variants/jubilant/smihandler.c b/src/mainboard/google/brox/variants/jubilant/smihandler.c index 9f848ea..f73470d 100644 --- a/src/mainboard/google/brox/variants/jubilant/smihandler.c +++ b/src/mainboard/google/brox/variants/jubilant/smihandler.c @@ -3,6 +3,7 @@ #include <acpi/acpi.h> #include <baseboard/variants.h> #include <delay.h> +#include <fw_config.h> #include "gpio.h" @@ -13,9 +14,11 @@ void variant_smi_sleep(u8 slp_typ) { if (slp_typ == ACPI_S5) { - /* WWAN RW101R-GL power off sequence */ - gpio_set(WWAN_RSL_L, 0); - mdelay(WWAN_TOFF); - gpio_set(WWAN_FCPO_L, 0); + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { + /* WWAN RW101R-GL power off sequence */ + gpio_set(WWAN_RSL_L, 0); + mdelay(WWAN_TOFF); + gpio_set(WWAN_FCPO_L, 0); + } } } diff --git a/src/mainboard/google/brox/variants/jubilant/variant.c b/src/mainboard/google/brox/variants/jubilant/variant.c index ff84374..6d058eb 100644 --- a/src/mainboard/google/brox/variants/jubilant/variant.c +++ b/src/mainboard/google/brox/variants/jubilant/variant.c @@ -38,7 +38,7 @@ static void wwan_out_of_reset(void *unused) { - if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { gpio_set(WWAN_FCPO_L, 1); gpio_set(WWAN_RSL_L, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR
by Angel Pons (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email ) Change subject: soc/intel/xeon_sp: Reserve PRMRR ...................................................................... Patch Set 7: Code-Review+1 (2 comments) File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/84314/comment/a2ca72b3_7b8a2df4?us… : PS6, Line 171: /* : * fls64: find least significant bit set in a 64-bit word : * As samples, fls64(0x0) = 64; fls64(0x4400) = 10; : * fls64(0x40400000000) = 34. : */ : static uint32_t fls64(uint64_t x) : { : uint32_t lo = (uint32_t)x; : if (lo) : return fls(lo); : uint32_t hi = x >> 32; : return fls(hi) + 32; : } > Acknowledged CB:85104 File src/soc/intel/xeon_sp/uncore.c: https://review.coreboot.org/c/coreboot/+/84314/comment/ea88cc0c_446b41b9?us… : PS7, Line 173: *base = msr_read(msr_addr); : : /* Clean the BIT0-BIT11 to get the base address */ : *base = (*base >> RANGE_SHIFT) << RANGE_SHIFT; I think there's a macro somewhere to do the `(1 << x) - 1` thing but I can't find it: ```suggestion /* Mask out bits 0-11 to get the base address */ *base = msr_read(msr_addr) & ~((1 << RANGE_SHIFT) - 1); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Gerrit-Change-Number: 84314 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 07:51:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: cpu/x86/mtrr: Use fls/ffs from lib.h
by Angel Pons (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Shuo Liu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85104?usp=email ) Change subject: cpu/x86/mtrr: Use fls/ffs from lib.h ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: PS5: Making a note for myself because these three-letter abbreviations are obviously clear and totally not confusing at all: ``` __fls = fms __ffs = fls ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093 Gerrit-Change-Number: 85104 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 07:44:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Pranava Y N. Hello Pranava Y N, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85106?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration ...................................................................... mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to accommodate different hardware configurations. Specifically, GPP_E07 is not connected (NC) on google/fatcat boards with the Microchip EC AIC. However, it is required for google/fatcat boards with Nuvoton/ITE AICs. BUG=b:378603337 Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85106/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2 Gerrit-Change-Number: 85106 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85106?usp=email ) Change subject: mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration ...................................................................... mb/google/fatcat: Refactor EC_SOC_INT_ODL (GPP_E07) configuration This patch refactors the configuration of GPP_E07 (EC_SOC_INT_ODL) to accommodate different hardware configurations. Specifically, GPP_E07 is not connected (NC) on google/fatcat boards with the Microchip EC AIC. However, it is required for google/fatcat boards with Nuvoton/ITE AICs. Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85106/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index 7833fe8..14d38a9 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -210,8 +210,13 @@ PAD_CFG_GPO(GPP_E03, 1, PLTRST), /* GPP_E06: SECURE_CAM_SW */ PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, PLTRST, LEVEL, ACPI), +#if CONFIG(BOARD_GOOGLE_FATCAT) /* GPP_E07: Not used */ PAD_NC(GPP_E07, NONE), +#else + /* GPP_E07 : [] ==> EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E07, NONE, LEVEL, INVERT, LOCK_CONFIG), +#endif /* GPP_E08: Not used */ PAD_NC(GPP_E08, NONE), /* GPP_E09: USB_RD_FP_CONN_12_OC0_N */ -- To view, visit https://review.coreboot.org/c/coreboot/+/85106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I540ba1feadc962866be16d44d2ad607fd0e97ad2 Gerrit-Change-Number: 85106 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add USB A1 port support
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85105?usp=email ) Change subject: mb/google/rex/var/kanix: Add USB A1 port support ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Gerrit-Change-Number: 85105 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 07:00:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add USB A1 port support
by Tyler Wang (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun. Tyler Wang has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85105?usp=email ) Change subject: mb/google/rex/var/kanix: Add USB A1 port support ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/85105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Gerrit-Change-Number: 85105 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 06:47:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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coreboot-gerrit November 2024