coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Angel Pons, Felix Held, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#53). Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/dlb.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/itss.c A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/pcie_rp.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 65 files changed, 4,979 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/53 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 53 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add USB A1 port support
by Tyler Wang (Code Review) 12 Nov '24

12 Nov '24

Tyler Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85105?usp=email ) Change subject: mb/google/rex/var/kanix: Add USB A1 port support ...................................................................... mb/google/rex/var/kanix: Add USB A1 port support BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/kanix/gpio.c M src/mainboard/google/rex/variants/kanix/overridetree.cb 2 files changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/85105/1 diff --git a/src/mainboard/google/rex/variants/kanix/gpio.c b/src/mainboard/google/rex/variants/kanix/gpio.c index b512c19..202dae6 100644 --- a/src/mainboard/google/rex/variants/kanix/gpio.c +++ b/src/mainboard/google/rex/variants/kanix/gpio.c @@ -205,8 +205,8 @@ PAD_NC(GPP_E07, NONE), /* GPP_E08 : NC net. */ PAD_NC(GPP_E08, NONE), - /* GPP_E09 : SOC_PEN_DETECT */ - PAD_CFG_GPI_SCI_LOCK(GPP_E09, NONE, EDGE_SINGLE, NONE, LOCK_CONFIG), + /* GPP_E09 : [] ==> USB_OC0# */ + PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), /* GPP_E10 : [] ==> SOC_FPMCU_INT_L */ PAD_CFG_GPI_IRQ_WAKE(GPP_E10, NONE, PWROK, LEVEL, INVERT), /* GPP_E11 : [] ==> MEM_STRAP_0 */ diff --git a/src/mainboard/google/rex/variants/kanix/overridetree.cb b/src/mainboard/google/rex/variants/kanix/overridetree.cb index 6c8a158..012657c 100644 --- a/src/mainboard/google/rex/variants/kanix/overridetree.cb +++ b/src/mainboard/google/rex/variants/kanix/overridetree.cb @@ -2,10 +2,12 @@ register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # Type-A Port A0 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port A0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port A1 register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C0 register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB3_C1 @@ -289,6 +291,13 @@ device ref usb2_port2 on end end chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (DB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" @@ -308,6 +317,13 @@ register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85105?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie76b20cab9e15a1944451697ebf243c0f0cc4740 Gerrit-Change-Number: 85105 Gerrit-PatchSet: 1 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS
by Name of user not set (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85041?usp=email ) Change subject: soc/intel/common/block/gpmr: Add Kconfig item HAVE_GPMR_REGISTERS ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/gpmr/Kconfig: PS1: > Seems no. […] Since GPMR are only used for extended BIOS, what do you think using `CONFIG_FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW` to enable its definitions? -- To view, visit https://review.coreboot.org/c/coreboot/+/85041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I975840684b3dd9e9e76ec6a08de12d8dd3c8f08a Gerrit-Change-Number: 85041 Gerrit-PatchSet: 3 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 06:09:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Name of user not set (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Felix Held. yuchi.chen(a)intel.com has posted comments on this change by yuchi.chen(a)intel.com. ( https://review.coreboot.org/c/coreboot/+/85012?usp=email ) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/common/block/itss/itss.c: https://review.coreboot.org/c/coreboot/+/85012/comment/9c89a65f_629fe3af?us… : PS5, Line 138: enum pirq itss_get_dev_pirq(struct device *dev, enum pci_pin pin) > Huh, I don't see `itss_get_dev_pirq` getting called in CB:85013 though. For usage, you can find it at https://review.coreboot.org/c/coreboot/+/83321/52/src/soc/intel/snowridge/a… and https://review.coreboot.org/c/coreboot/+/83321/52/src/soc/intel/snowridge/l… -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 06:07:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: yuchi.chen(a)intel.com Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR
by Name of user not set (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Held, yuchi.chen(a)intel.com. Hello Angel Pons, Felix Held, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85012?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ...................................................................... soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIR ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one of PIRQA-H. This patch adds a function itss_get_dev_pirq() returning PIRQ for a given device and INT pin. Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/itss.h M src/soc/intel/common/block/itss/itss.c 2 files changed, 22 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85012?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b Gerrit-Change-Number: 85012 Gerrit-PatchSet: 7 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC
by Name of user not set (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Elyes Haouas, Felix Held, Felix Singer, Frans Hendriks, Jérémy Compostella, Paul Menzel, Vasiliy Khoruzhick, yuchi.chen(a)intel.com. Hello Angel Pons, Felix Held, Jérémy Compostella, Shuo Liu, Vasiliy Khoruzhick, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83321?usp=email to look at the new patch set (#52). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC ...................................................................... soc/intel/snowridge: Add support for Intel Atom Snow Ridge SoC Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com> Tested-by: Vasiliy Khoruzhick <vasilykh(a)arista.com> --- A src/soc/intel/snowridge/Kconfig A src/soc/intel/snowridge/Makefile.mk A src/soc/intel/snowridge/acpi.c A src/soc/intel/snowridge/acpi/hostbridges.asl A src/soc/intel/snowridge/acpi/pci_irqs.asl A src/soc/intel/snowridge/acpi/pcie.asl A src/soc/intel/snowridge/acpi/pcie_port.asl A src/soc/intel/snowridge/acpi/pmc.asl A src/soc/intel/snowridge/acpi/southcluster.asl A src/soc/intel/snowridge/acpi/uncore.asl A src/soc/intel/snowridge/bootblock/bootblock.c A src/soc/intel/snowridge/bootblock/bootblock.h A src/soc/intel/snowridge/bootblock/early_uart_init.c A src/soc/intel/snowridge/chip.c A src/soc/intel/snowridge/chip.h A src/soc/intel/snowridge/common/fsp_hob.c A src/soc/intel/snowridge/common/fsp_hob.h A src/soc/intel/snowridge/common/gpio.c A src/soc/intel/snowridge/common/hob_display.c A src/soc/intel/snowridge/common/kti_cache.c A src/soc/intel/snowridge/common/kti_cache.h A src/soc/intel/snowridge/common/pmclib.c A src/soc/intel/snowridge/common/reset.c A src/soc/intel/snowridge/common/spi.c A src/soc/intel/snowridge/common/systemagent_early.c A src/soc/intel/snowridge/common/uart8250mem.c A src/soc/intel/snowridge/common/uart8250mem.h A src/soc/intel/snowridge/common/upd_display.c A src/soc/intel/snowridge/cpu.c A src/soc/intel/snowridge/dlb.c A src/soc/intel/snowridge/finalize.c A src/soc/intel/snowridge/heci.c A src/soc/intel/snowridge/include/soc/acpi.h A src/soc/intel/snowridge/include/soc/cpu.h A src/soc/intel/snowridge/include/soc/gpio.h A src/soc/intel/snowridge/include/soc/gpio_defs.h A src/soc/intel/snowridge/include/soc/gpio_snr.h A src/soc/intel/snowridge/include/soc/iomap.h A src/soc/intel/snowridge/include/soc/irq.h A src/soc/intel/snowridge/include/soc/lpc.h A src/soc/intel/snowridge/include/soc/msr.h A src/soc/intel/snowridge/include/soc/nvs.h A src/soc/intel/snowridge/include/soc/p2sb.h A src/soc/intel/snowridge/include/soc/pci_devs.h A src/soc/intel/snowridge/include/soc/pcr_gpmr.h A src/soc/intel/snowridge/include/soc/pcr_ids.h A src/soc/intel/snowridge/include/soc/pm.h A src/soc/intel/snowridge/include/soc/pmc.h A src/soc/intel/snowridge/include/soc/sata.h A src/soc/intel/snowridge/include/soc/smbus.h A src/soc/intel/snowridge/include/soc/soc_chip.h A src/soc/intel/snowridge/include/soc/systemagent.h A src/soc/intel/snowridge/itss.c A src/soc/intel/snowridge/lockdown.c A src/soc/intel/snowridge/lpc.c A src/soc/intel/snowridge/nis.c A src/soc/intel/snowridge/pcie_rp.c A src/soc/intel/snowridge/qat.c A src/soc/intel/snowridge/ramstage.h A src/soc/intel/snowridge/romstage/gpio_snr.c A src/soc/intel/snowridge/romstage/romstage.c A src/soc/intel/snowridge/sata.c A src/soc/intel/snowridge/smihandler.c A src/soc/intel/snowridge/sriov.c A src/soc/intel/snowridge/systemagent.c 65 files changed, 5,009 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/52 -- To view, visit https://review.coreboot.org/c/coreboot/+/83321?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f Gerrit-Change-Number: 83321 Gerrit-PatchSet: 52 Gerrit-Owner: yuchi.chen(a)intel.com Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Vasiliy Khoruzhick <vasilykh(a)arista.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: soc/mediatek/**/spi.h: Enclose complex macros in parentheses
by Yu-Ping Wu (Code Review) 12 Nov '24

12 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85001?usp=email ) Change subject: soc/mediatek/**/spi.h: Enclose complex macros in parentheses ...................................................................... soc/mediatek/**/spi.h: Enclose complex macros in parentheses Fix the checkpatch error: Macros with complex values should be enclosed in parentheses Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74 Signed-off-by: Yu-Ping Wu <yupingso(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85001 Reviewed-by: Yidi Lin <yidilin(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/mediatek/mt8173/include/soc/spi.h M src/soc/mediatek/mt8183/include/soc/spi.h M src/soc/mediatek/mt8186/include/soc/spi.h M src/soc/mediatek/mt8188/include/soc/spi.h M src/soc/mediatek/mt8192/include/soc/spi.h M src/soc/mediatek/mt8195/include/soc/spi.h 6 files changed, 12 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved diff --git a/src/soc/mediatek/mt8173/include/soc/spi.h b/src/soc/mediatek/mt8173/include/soc/spi.h index 4a81eae..3cb1a01 100644 --- a/src/soc/mediatek/mt8173/include/soc/spi.h +++ b/src/soc/mediatek/mt8173/include/soc/spi.h @@ -7,8 +7,8 @@ #define SPI_BUS_NUMBER 1 -#define GET_SCK_REG(x) x->spi_cfg0_reg -#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg +#define GET_SCK_REG(x) ((x)->spi_cfg0_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg) DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 7, 0) DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 8) diff --git a/src/soc/mediatek/mt8183/include/soc/spi.h b/src/soc/mediatek/mt8183/include/soc/spi.h index 47dee02..48e0d55 100644 --- a/src/soc/mediatek/mt8183/include/soc/spi.h +++ b/src/soc/mediatek/mt8183/include/soc/spi.h @@ -7,8 +7,8 @@ #define SPI_BUS_NUMBER 6 -#define GET_SCK_REG(x) x->spi_cfg2_reg -#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg) DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) diff --git a/src/soc/mediatek/mt8186/include/soc/spi.h b/src/soc/mediatek/mt8186/include/soc/spi.h index 2588dcc..e70f3cd 100644 --- a/src/soc/mediatek/mt8186/include/soc/spi.h +++ b/src/soc/mediatek/mt8186/include/soc/spi.h @@ -12,8 +12,8 @@ #define SPI_BUS_NUMBER 6 -#define GET_SCK_REG(x) x->spi_cfg2_reg -#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg) DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) diff --git a/src/soc/mediatek/mt8188/include/soc/spi.h b/src/soc/mediatek/mt8188/include/soc/spi.h index b1ac9ff..a44ba43 100644 --- a/src/soc/mediatek/mt8188/include/soc/spi.h +++ b/src/soc/mediatek/mt8188/include/soc/spi.h @@ -13,8 +13,8 @@ #define SPI_BUS_NUMBER 6 -#define GET_SCK_REG(x) x->spi_cfg2_reg -#define GET_TICK_DLY_REG(x) x->spi_cmd_reg +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cmd_reg) DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h index 28fe839..e2f6955 100644 --- a/src/soc/mediatek/mt8192/include/soc/spi.h +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -7,8 +7,8 @@ #define SPI_BUS_NUMBER 8 -#define GET_SCK_REG(x) x->spi_cfg2_reg -#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg) DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) diff --git a/src/soc/mediatek/mt8195/include/soc/spi.h b/src/soc/mediatek/mt8195/include/soc/spi.h index cd87277..9bd69f9 100644 --- a/src/soc/mediatek/mt8195/include/soc/spi.h +++ b/src/soc/mediatek/mt8195/include/soc/spi.h @@ -7,8 +7,8 @@ #define SPI_BUS_NUMBER 6 -#define GET_SCK_REG(x) x->spi_cfg2_reg -#define GET_TICK_DLY_REG(x) x->spi_cfg1_reg +#define GET_SCK_REG(x) ((x)->spi_cfg2_reg) +#define GET_TICK_DLY_REG(x) ((x)->spi_cfg1_reg) DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/85001?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0e4582c1dd19ed3f757a2cb3c3fc33138302d74 Gerrit-Change-Number: 85001 Gerrit-PatchSet: 2 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Override DRAM Freq
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85102?usp=email ) Change subject: mb/google/fatcat/var/francka: Override DRAM Freq ...................................................................... mb/google/fatcat/var/francka: Override DRAM Freq Due to the hardware limitation on francka, reduce the memory speed to 7467 MT/s. BUG=b:373394046 TEST=emerge-fatcat coreboot Change-Id: I9c45c90952e20fc96943df03f591075338624e88 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85102 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/fatcat/variants/francka/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Amanda Hwang: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index bfd637a..e38b186 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -1,5 +1,7 @@ chip soc/intel/pantherlake + register "max_dram_speed_mts" = "7467" + device domain 0 on end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c45c90952e20fc96943df03f591075338624e88 Gerrit-Change-Number: 85102 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add config option to limit DRAM frequency
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85101?usp=email ) Change subject: soc/intel/pantherlake: Add config option to limit DRAM frequency ...................................................................... soc/intel/pantherlake: Add config option to limit DRAM frequency This patch adds a new config option to limit the maximum DRAM frequency for Pantherlake platforms. The mainboard code should try to set `max_dram_speed_mts` from override device tree if required. BUG=b:373394046 TEST=Able to build and boot google/fatcat. Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85101 Reviewed-by: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/soc/intel/pantherlake/chip.h M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Amanda Hwang: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index b59ce5e..5846037 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -512,6 +512,8 @@ */ uint8_t slow_slew_rate_config[NUM_VR_DOMAINS]; + uint16_t max_dram_speed_mts; + }; typedef struct soc_intel_pantherlake_config config_t; diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index b105d3d..e6ed19ec 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -74,6 +74,9 @@ m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; } + if (config->max_dram_speed_mts) + m_cfg->DdrFreqLimit = config->max_dram_speed_mts; + m_cfg->RMT = config->rmt; m_cfg->MrcFastBoot = 1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/85101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic92947b2997c116ea8ed0abff4c6b3c2ca956c65 Gerrit-Change-Number: 85101 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add audio codec/amp support
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Tarun, Tyler Wang. Subrata Banik has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85100?usp=email ) Change subject: mb/google/rex/var/kanix: Add audio codec/amp support ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Gerrit-Change-Number: 85100 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 04:58:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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