coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[L] Change in coreboot[main]: mb/google/rex/var/kanix: Add initial overridetree settings
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Tarun, Tyler Wang. Subrata Banik has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85021?usp=email ) Change subject: mb/google/rex/var/kanix: Add initial overridetree settings ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85021?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I468ca388f495b2e527841145f8162b21074058cc Gerrit-Change-Number: 85021 Gerrit-PatchSet: 12 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 04:57:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Anil Kumar K, Naveen M, Pranava Y N, Varun Upadhyay. Subrata Banik has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/ae39c5ae_b5a8c139?us… : PS2, Line 8: AUDIO_ALC721_SNDW > Yes. This data is important for kernel & ucm. > 1. Based on codec combination selected in CBI setting, fw_config is expected to configure h/w gpios. looking at the CBI, I can tell that we cam have either ALC722 or ALC721 therefore, it's either configuration therefore, the GPIO configuration taken care w/o any duplication. > 2. Kernel acpi match table will use this exposed coreboot data and load specific machine driver This looks to me little static configuration where we are telling any AIC (and not soldered down module) will be assigned link 3 ? therefore, we need to keep redundant entries for ALC722 and ALC721 > 3. As same machine driver loads multiple codec combinations, config.star in ui/ucm further granularize & applies required mixer setting for that specific codec and i assume the link and ID numbers are meant to pick the correct mixer settings depending on the Audio codec attached ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 04:57:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[S] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Karthik Ramasubramanian (Code Review) 12 Nov '24

12 Nov '24

Karthik Ramasubramanian has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85038?usp=email ) Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... mb/google/brox: Do not select HAVE_ACPI_RESUME Brox mainboard does not reliably support S3 entry/exit. Hence do not select HAVE_ACPI_RESUME config option. Also trigger a fail-safe board reset if the system resumes from S3. BUG=b:337274309 TEST=Build Brox BIOS image and boot to OS. Ensure that the _S3 name variable is not advertised in the DSDT. Trigger a S3 entry and ensure that on S3 exit, the board reset is triggered. Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85038 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bob Moragues <moragues(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/bootblock.c 2 files changed, 11 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Bob Moragues: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index ce14d5b..fb3dfc4 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -23,7 +23,6 @@ select FW_CONFIG select FW_CONFIG_SOURCE_CHROMEEC_CBI select GOOGLE_SMBIOS_MAINBOARD_VERSION - select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select I2C_TPM diff --git a/src/mainboard/google/brox/bootblock.c b/src/mainboard/google/brox/bootblock.c index c24e959..3a5f785 100644 --- a/src/mainboard/google/brox/bootblock.c +++ b/src/mainboard/google/brox/bootblock.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpi.h> #include <baseboard/variants.h> #include <bootblock_common.h> +#include <bootmode.h> +#include <reset.h> +#include <security/vboot/vboot_common.h> void bootblock_mainboard_early_init(void) { @@ -13,6 +17,13 @@ void bootblock_mainboard_init(void) { + if (platform_is_resuming()) { + printk(BIOS_EMERG, "ACPI S3 resume is not supported on this platform\n"); + /* Prepare for reboot to clear the sleep state such that the board + is not stuck in reboot loop. */ + vboot_platform_prepare_reboot(); + board_reset(); + } variant_update_descriptor(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire
by Naveen M (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N, Subrata Banik, Varun Upadhyay. Naveen M has posted comments on this change by Varun Upadhyay. ( https://review.coreboot.org/c/coreboot/+/85074?usp=email ) Change subject: mb/google/fatcat: Add FW_CONFIG Support for ALC721 soundwire ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/fatcat/variants/fatcat/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85074/comment/a9b0feb9_eb29fc2b?us… : PS2, Line 8: AUDIO_ALC721_SNDW > > jfyi, at kernel, we add driver data & match table for codec at sndw3.. […] Yes. This data is important for kernel & ucm. 1. Based on codec combination selected in CBI setting, fw_config is expected to configure h/w gpios. 2. Kernel acpi match table will use this exposed coreboot data and load specific machine driver 3. As same machine driver loads multiple codec combinations, config.star in ui/ucm further granularize & applies required mixer setting for that specific codec -- To view, visit https://review.coreboot.org/c/coreboot/+/85074?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If5ca1502942f0ca009db398589c4a243d9e2804c Gerrit-Change-Number: 85074 Gerrit-PatchSet: 2 Gerrit-Owner: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Naveen M <naveen.m(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 03:26:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Naveen M <naveen.m(a)intel.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Varun Upadhyay <varun.upadhyay(a)intel.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Optimize reset handling for non-UFS boot
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84996?usp=email ) Change subject: soc/intel/alderlake: Optimize reset handling for non-UFS boot ...................................................................... soc/intel/alderlake: Optimize reset handling for non-UFS boot This patch optimizes the reset handling in the Alder Lake romstage while disabling the UFS controller in an uni-boot scenario (a unified AP firmware image can boot both UFS and non-UFS systems). It introduces a check in `mainboard_expects_another_reset()` to skip unnecessary resets when a CSE slot switch is due, meaning CSE is not booting from the RW slot. This saves one reset for non-UFS SKUs when a CSE slot switch is pending. The patch also relocates the `cse_fw_sync()` call after disabling the UFS controllers to ensure the system reset flow can be better optimized and combined with any expected resets due to CSE synchronization. TEST=Able to build google/trulo eMMC sku and able to save one reset. Without this patch: 1. Warm reset after disabling UFS (1st reset) 2. Global reset after CSE sync (2nd reset) 3. Warm reset after disabling UFS (3rd reset) 4. Boot to OS With this patch: 1. Skip disabling UFS if CSE sync is due, aka no reset. 2. Global reset after CSE sync (1st reset) 3. CSE is booting from slot RW meaning CSE sync is done, perform UFS disabling and issue a warm reset after disabling UFS (2nd reset) 4. Boot to OS Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84996 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Jayvik Desai <jayvik(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c 1 file changed, 16 insertions(+), 4 deletions(-) Approvals: Eric Lai: Looks good to me, approved Karthik Ramasubramanian: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Jayvik Desai: Looks good to me, approved diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index 3acd2fd..d2abaee 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -34,7 +34,19 @@ bool __weak mainboard_expects_another_reset(void) { - return false; + bool reset_pending = true; + + if (!CONFIG(SOC_INTEL_CSE_LITE_SKU)) + reset_pending = false; + + /* + * Skip reset if CSE slot switch is pending meaning, CSE is booting from RO. + * CSE state switch will issue a reset anyway. + */ + if (is_cse_boot_to_rw() == true) + reset_pending = false; + + return reset_pending; } static void disable_ufs(void) @@ -182,9 +194,6 @@ if (!CONFIG(INTEL_TXT)) disable_intel_txt(); - if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) - cse_fw_sync(); - /* Program to Disable UFS Controllers */ if (!is_devfn_enabled(PCH_DEVFN_UFS) && (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { @@ -196,6 +205,9 @@ } } + if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) + cse_fw_sync(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84996?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I04e6943fb136d126a1d1a829aadb316d2cdd0ac9 Gerrit-Change-Number: 84996 Gerrit-PatchSet: 5 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/cmn/pmc: Perform PM register init for CSE
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85025?usp=email ) Change subject: soc/intel/cmn/pmc: Perform PM register init for CSE ...................................................................... soc/intel/cmn/pmc: Perform PM register init for CSE Before entering FSP-M, AP firmware must ensure the PM1_CNT register reflects the correct sleep state if a global reset occurred. This is crucial when Intel CSE has reset the system, as indicated by the global reset bit and wake status register. If PM1_CNT doesn't contain a valid sleep state after a CSE reset, AP firmware must enforce an S5 exit path before handing control to FSP-M for CSE initialization. This ensures proper system initialization and avoids potential issues caused by an inconsistent sleep state. Additionally, clears the PM1 status register (PM1_STS) after retrieving the power state. This prevents stale status information from persisting across power cycles, which could lead to confusion during subsequent boots. BUG=b:265939425 TEST=Verified that `prev_sleep_state` holds the correct value (5 for S5) after CSE performs a global reset. Fixes: Inconsistent sleep state after CSE reset. Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 46 insertions(+), 0 deletions(-) Approvals: Karthik Ramasubramanian: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0b3863a..c51a960 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -430,6 +430,9 @@ /* Clear SLP_TYP. */ pmc_write_pm1_control(ps->pm1_cnt & ~(SLP_TYP)); + + /* Clear PM1_STATUS */ + pmc_clear_pm1_status(); } prev_sleep_state = soc_prev_sleep_state(ps, prev_sleep_state); @@ -440,6 +443,34 @@ return prev_sleep_state; } +static bool pmc_get_global_reset_sts_mmio(void) +{ + uint8_t *addr = pmc_mmio_regs(); + + return !!(read32p((uintptr_t)(addr + GEN_PMCON_A)) & GBL_RST_STS); +} + +static bool pmc_get_global_reset_sts_pci(void) +{ +#if defined(__SIMPLE_DEVICE__) + pci_devfn_t dev = PCI_DEV(0, PCI_SLOT(PCH_DEVFN_PMC), PCI_FUNC(PCH_DEVFN_PMC)); +#else + struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC); + if (!dev) + return false; +#endif + + return !!(pci_read_config32(dev, GEN_PMCON_A) & GBL_RST_STS); +} + +static bool pmc_get_global_reset_sts(void) +{ + if (CONFIG(SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION)) + return pmc_get_global_reset_sts_mmio(); + else + return pmc_get_global_reset_sts_pci(); +} + void pmc_fill_pm_reg_info(struct chipset_power_state *ps) { int i; @@ -450,6 +481,21 @@ ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); ps->pm1_cnt = pmc_read_pm1_control(); + /* + * Before system memory initialization, AP firmware should check the wake status + * to determine if Intel CSE has reset the system and system sleep state (PM1_CNT) + * holds a valid sleep entry? + * + * If not, then AP FW should force to take a S5 exit path (by programming the PM1_CNT) + * register as per PM register initialization requirement for CSE. + */ + if (pmc_get_global_reset_sts() && (ps->pm1_sts & WAK_STS) && !(ps->pm1_cnt & SLP_TYP)) { + printk(BIOS_DEBUG, "Enforcing the S5 exit path\n"); + uint32_t pm1_cnt_slp_type = SLP_TYP_S5 << SLP_TYP_SHIFT; + ps->pm1_cnt |= pm1_cnt_slp_type; + pmc_enable_pm1_control(pm1_cnt_slp_type); + } + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); -- To view, visit https://review.coreboot.org/c/coreboot/+/85025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae9c026da86fef4a3571e06b1bb20504c3d8c9be Gerrit-Change-Number: 85025 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/alderlake: Support early Sign of Life for CSE FW Sync
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85103?usp=email ) Change subject: soc/intel/alderlake: Support early Sign of Life for CSE FW Sync ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/85103/comment/3177943f_c0139864?us… : PS1, Line 188: ux_inform_user_of_update_operation("CSE update"); please add eventlog as well ``` elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Gerrit-Change-Number: 85103 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 02:55:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brox: Do not select HAVE_ACPI_RESUME
by Subrata Banik (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Edward Hill, Karthik Ramasubramanian, Nick Vaccaro, Shyam Sundar Radjacoumar. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85038?usp=email ) Change subject: mb/google/brox: Do not select HAVE_ACPI_RESUME ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85038?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief0936fbcd9e5e34ef175736a858f98edf840719 Gerrit-Change-Number: 85038 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Bob Moragues <moragues(a)google.com> Gerrit-Reviewer: Edward Hill <ecgh(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Edward Hill <ecgh(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 02:50:10 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add audio codec/amp support
by Tyler Wang (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Subrata Banik, Tarun. Tyler Wang has posted comments on this change by Tyler Wang. ( https://review.coreboot.org/c/coreboot/+/85100?usp=email ) Change subject: mb/google/rex/var/kanix: Add audio codec/amp support ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85100/comment/4ccda70b_41869d42?us… : PS2, Line 9: Add support for audio codec ALC5682I-VS and audio amp : ALC1019. > Fits in one line. After add "Realtek", the commit message will be longer than 75 characters. It has to be 2 lines. Please help to take a look, thanks. https://review.coreboot.org/c/coreboot/+/85100/comment/b4b0fa10_08e6b4ba?us… : PS2, Line 11: > Also mention the Realtek devices? Done, thanks for your advice. https://review.coreboot.org/c/coreboot/+/85100/comment/b6134afa_d36e7ab6?us… : PS2, Line 11: > Also mention the Realtek devices? Done, thanks for your advise. -- To view, visit https://review.coreboot.org/c/coreboot/+/85100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Gerrit-Change-Number: 85100 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 02:49:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/rex/var/kanix: Add audio codec/amp support
by Tyler Wang (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, Tyler Wang. Hello David Wu, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85100?usp=email to look at the new patch set (#4). Change subject: mb/google/rex/var/kanix: Add audio codec/amp support ...................................................................... mb/google/rex/var/kanix: Add audio codec/amp support Add support for Realtek audio codec ALC5682I-VS and Realtek audio amp ALC1019. BUG=b:366291025 TEST=emerge-rex coreboot pass Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/Kconfig M src/mainboard/google/rex/variants/kanix/gpio.c M src/mainboard/google/rex/variants/kanix/overridetree.cb 3 files changed, 22 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/85100/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85100?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0cac934004b0b1b72feaacea99a602fffd2f1457 Gerrit-Change-Number: 85100 Gerrit-PatchSet: 4 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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coreboot-gerrit November 2024