coreboot-gerrit November 2024

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[XS] Change in coreboot[main]: 3rdparty/intel-microcode: Update submodule to upstream main
by Felix Singer (Code Review) 12 Nov '24

12 Nov '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85113?usp=email ) Change subject: 3rdparty/intel-microcode: Update submodule to upstream main ...................................................................... 3rdparty/intel-microcode: Update submodule to upstream main Updating from commit id 129f82f7429c: 2024-10-29 17:43:50 -0600 - (microcode-20241029 Release) to commit id 8ac9378a8487: 2024-11-12 11:14:21 -0600 - (microcode-20241112 Release) This brings in 1 new commits: 8ac9378a8487 microcode-20241112 Release Change-Id: Icdb00537c7e8733c8c81c834313e24b5c7842609 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M 3rdparty/intel-microcode 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85113/1 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 129f82f..8ac9378 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 129f82f7429c29976b15d6837d2f573cc6a02c26 +Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df -- To view, visit https://review.coreboot.org/c/coreboot/+/85113?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdb00537c7e8733c8c81c834313e24b5c7842609 Gerrit-Change-Number: 85113 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: util/scripts/update_submodule: Extend commit ids to 12 chars
by Felix Singer (Code Review) 12 Nov '24

12 Nov '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85112?usp=email ) Change subject: util/scripts/update_submodule: Extend commit ids to 12 chars ...................................................................... util/scripts/update_submodule: Extend commit ids to 12 chars Checkpatch suggests to use 12 chars of the commit id. So adjust the submodule update script in order to be consistent. Change-Id: I0e356066b6598f586054f940684c26b6e5db2169 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/scripts/update_submodules 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85112/1 diff --git a/util/scripts/update_submodules b/util/scripts/update_submodules index 9f6c14f..48bb7f7 100755 --- a/util/scripts/update_submodules +++ b/util/scripts/update_submodules @@ -102,7 +102,7 @@ exit 1 fi - initial_commit_id="$(git log --pretty='%h' -n 1)" + initial_commit_id="$(git log --pretty='%h' -n 1 --abbrev=12)" initial_commit_description="$(git log --pretty='%ci - (%s)' -n 1)" if [[ ${skip_sync} != "1" ]]; then git fetch 2>/dev/null @@ -116,14 +116,14 @@ fi done - updated_commit_id="$(git log --pretty='%h' -n 1 "${branch_name}" -- )" + updated_commit_id="$(git log --pretty='%h' -n 1 --abbrev=12 "${branch_name}" -- )" updated_commit_description="$(git log --pretty='%ci - (%s)' -n 1 "${updated_commit_id}")" if [ "${initial_commit_id}" = "${updated_commit_id}" ]; then echo "No updates for ${submodule}" continue fi SUBMODULES_WITH_UPDATES+=1 - update_log="$(git log --oneline "${initial_commit_id}..${updated_commit_id}")" + update_log="$(git log --oneline --abbrev=12 "${initial_commit_id}..${updated_commit_id}")" update_count="$(echo "${update_log}" | wc -l)" if [[ "${update_count}" -gt "${max_commits_to_list}" ]]; then update_log="" -- To view, visit https://review.coreboot.org/c/coreboot/+/85112?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e356066b6598f586054f940684c26b6e5db2169 Gerrit-Change-Number: 85112 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Karthik Ramasubramanian (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85103?usp=email ) Change subject: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/85103/comment/8f263661_6d977e93?us… : PS1, Line 188: ux_inform_user_of_update_operation("CSE update"); > please add eventlog as well […] Earlier it was getting logged from cse_fw_update. But I felt it is not the right location since we are not displaying ESOL from there and the code was not checking if ESOL was enabled either. So I uploaded a CL: https://review.coreboot.org/c/coreboot/+/85111 to move logging ESOL event to the more appropriate location. -- To view, visit https://review.coreboot.org/c/coreboot/+/85103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Gerrit-Change-Number: 85103 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Tue, 12 Nov 2024 20:50:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place
by Karthik Ramasubramanian (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, Tarun. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email ) Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place ...................................................................... soc/intel: Log CSE Sync Early Sign of Life event from a better place CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW update is complete. This happens irrespective of whether Early Sign of Life screen is enabled or not. Move CSE Sync ESOL event right before displaying the ESOL screen. BUG=b:378458829 TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event for CSE Sync is logged. Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/meteorlake/romstage/fsp_params.c 4 files changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85111/1 diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index fc9721c..b6236aa 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -446,6 +446,7 @@ name = "CSE update"; esol_required = true; } + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); } if (esol_required) diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index d3a2884..daf2b76 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -208,8 +208,10 @@ if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE) && !s3wake) { cse_fill_bp_info(); if (CONFIG(CHROMEOS_ENABLE_ESOL) && - is_cse_fw_update_required() && !is_cse_boot_to_rw()) + is_cse_fw_update_required() && !is_cse_boot_to_rw()) { + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); ux_inform_user_of_update_operation("CSE update"); + } cse_fw_sync(); } diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 09281ab..67c7ef3 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -835,7 +835,6 @@ return CB_ERR; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); - elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); return CB_SUCCESS; } diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index bc7c20b..3010b1d 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -456,8 +456,10 @@ elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); } - if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { vga_init_control = VGA_INIT_CONTROL_ENABLE; + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); + } if (!vga_init_control) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/85111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Gerrit-Change-Number: 85111 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[S] Change in coreboot[main]: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync
by Karthik Ramasubramanian (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Hello Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85103?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/alderlake: Display early Sign of Life for CSE FW Sync ...................................................................... soc/intel/alderlake: Display early Sign of Life for CSE FW Sync This will ensure that the user is informed about an ongoing CSE FW Sync. BUG=b:378458829 TEST=Build Brox BIOS image and boot to OS. Ensure that ESOL is displayed during CSE FW Sync. Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/alderlake/romstage/ux.h 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/85103/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85103?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e7b71da7a98be87361dc7ab9e6c4ae572f61773 Gerrit-Change-Number: 85103 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[L] Change in coreboot[main]: mb/asus: Add PRIME H610M-K D4
by Máté Kukri (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Felix Singer. Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/84243?usp=email ) Change subject: mb/asus: Add PRIME H610M-K D4 ...................................................................... Patch Set 12: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84243/comment/c5200846_d0ca4ee2?us… : PS10, Line 11: TODO (please don't submit before this is removed): > Maybe mark it as WIP again, so that people don't start reviewing. The SIO stuff can use some clean up but most TODOs are done here. File src/mainboard/asus/h610m-k/devicetree.cb: https://review.coreboot.org/c/coreboot/+/84243/comment/002455db_bade84aa?us… : PS11, Line 56: device ref pcie_rp1 on > Missing smbios slot descriptions Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/84243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab821f6799009d231de4d21219f0ac2ae89c5c9 Gerrit-Change-Number: 84243 Gerrit-PatchSet: 12 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 17:58:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[L] Change in coreboot[main]: mb/asus: Add PRIME H610M-K D4
by Máté Kukri (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Máté Kukri. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84243?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/asus: Add PRIME H610M-K D4 ...................................................................... mb/asus: Add PRIME H610M-K D4 See `Documentation/mainboard/asus/h610m-k.md`. Extras notes: - GPIO table obtained from vendor FW via inteltool+intelp2m - Obtained using hackily examining registers: - PCIe clk_src and clk_req map (the ICC and FIA sideband ports, and the src_muxsel register offsets in the PCH atasheet are an outright lie) - SATA port list - USB OC pins - Confirmed USB port list by plugging things in - HDA verbs and VBT dumped from Linux sysfs under vendor FW - Super I/O really is a NCT6798D but the NCT6791D code is good enough for what I need Change-Id: I6ab821f6799009d231de4d21219f0ac2ae89c5c9 Signed-off-by: Mate Kukri <km(a)mkukri.xyz> --- A Documentation/mainboard/asus/h610m-k.md A src/mainboard/asus/h610m-k/Kconfig A src/mainboard/asus/h610m-k/Kconfig.name A src/mainboard/asus/h610m-k/Makefile.mk A src/mainboard/asus/h610m-k/board_info.txt A src/mainboard/asus/h610m-k/bootblock.c A src/mainboard/asus/h610m-k/data.vbt A src/mainboard/asus/h610m-k/devicetree.cb A src/mainboard/asus/h610m-k/dsdt.asl A src/mainboard/asus/h610m-k/gpio.h A src/mainboard/asus/h610m-k/hda_verb.c A src/mainboard/asus/h610m-k/ramstage.c A src/mainboard/asus/h610m-k/romstage.c 13 files changed, 929 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/84243/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84243?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6ab821f6799009d231de4d21219f0ac2ae89c5c9 Gerrit-Change-Number: 84243 Gerrit-PatchSet: 12 Gerrit-Owner: Máté Kukri <km(a)mkukri.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Máté Kukri <km(a)mkukri.xyz>

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[S] Change in coreboot[main]: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor
by Karthik Ramasubramanian (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: David Wu, Ren Kuo, Subrata Banik. Karthik Ramasubramanian has posted comments on this change by Ren Kuo. ( https://review.coreboot.org/c/coreboot/+/85107?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/brox/var/jubilant: Add fw_config for WWAN Sar Sensor ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85107/comment/4d08a01d_e171cb79?us… : PS2, Line 10: remvoed Nit: removed https://review.coreboot.org/c/coreboot/+/85107/comment/7b18d4cb_484f83c3?us… : PS2, Line 18: to Nit: remove 'to' File src/mainboard/google/brox/variants/jubilant/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85107/comment/b96de3e9_3f78119f?us… : PS2, Line 14: smm-y-$(CONFIG_FW_CONFIG) smm-$(CONFIG_FW_CONFIG) File src/mainboard/google/brox/variants/jubilant/smihandler.c: https://review.coreboot.org/c/coreboot/+/85107/comment/93ecac24_e1d76350?us… : PS2, Line 16: if (slp_typ == ACPI_S5) { : if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { I would recommend to check specifically for LTE and LTE SAR config. This will help in the future when you have another Daughter board without LTE config. That way you don't have to come and change here. ``` if (slp_typ == ACPI_S5 && (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE)) || (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE_SAR)) { ... } ``` File src/mainboard/google/brox/variants/jubilant/variant.c: https://review.coreboot.org/c/coreboot/+/85107/comment/06802900_a142a802?us… : PS2, Line 41: if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { Same comment as in the other file: ``` if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE) || fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE_SAR))) { ... } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85107?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If9231ac8df94e1dc514ecf0780c99adbfb902893 Gerrit-Change-Number: 85107 Gerrit-PatchSet: 2 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Kenneth Chan <kenneth.chan(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Richard Lin <richardlin(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 17:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Reserve PRMRR
by Angel Pons (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/84314?usp=email ) Change subject: soc/intel/xeon_sp: Reserve PRMRR ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > Shouldn't this CL and the following be in a different order ? It would make more sense, yes -- To view, visit https://review.coreboot.org/c/coreboot/+/84314?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I81d17b1376459510f7c0d43ba4b519b1f2bd3e1f Gerrit-Change-Number: 84314 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 12 Nov 2024 17:25:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: cpu/x86/mtrr: Use fls/ffs from lib.h
by Angel Pons (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Angel Pons, Felix Held, Fred Reitberger, Jason Glenesk, Jérémy Compostella, Matt DeVillier, Shuo Liu. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85104?usp=email ) Change subject: cpu/x86/mtrr: Use fls/ffs from lib.h ...................................................................... Patch Set 5: (1 comment) File src/include/cpu/x86/mtrr.h: https://review.coreboot.org/c/coreboot/+/85104/comment/87620597_11186cb6?us… : PS5, Line 80: #include <lib.h> > nit: I know this is not an official rule but most of the time but the inclusion follows the alphabet […] I would agree with this but there's other includes at the beginning of the file and none of them are sorted alphabetically. I don't think this change makes it worse, and I wouldn't mind if someone consolidated the includes at the start of the file. Actually, this change *is* consistent with the existing *reverse* alphabetical order in the file :^) -- To view, visit https://review.coreboot.org/c/coreboot/+/85104?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic9c6f1027447b04627d7f21d777cbea142588093 Gerrit-Change-Number: 85104 Gerrit-PatchSet: 5 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 12 Nov 2024 17:25:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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coreboot-gerrit November 2024