coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

1 participants
2521 discussions

[XS] Change in coreboot[main]: mb/google/nissa/var/rull: add RAM ID H58G56BK8BX068 for rull
by Rui Zhou (Code Review) 13 Nov '24

13 Nov '24

Rui Zhou has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85117?usp=email ) Change subject: mb/google/nissa/var/rull: add RAM ID H58G56BK8BX068 for rull ...................................................................... mb/google/nissa/var/rull: add RAM ID H58G56BK8BX068 for rull BUG=b:378821948 BRANCH=None TEST=boot to kernel success Change-Id: I4c4ad191a5e9703ee0f3bed150c816bfb098daf5 --- M src/mainboard/google/brya/variants/rull/memory/Makefile.mk M src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85117/1 diff --git a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk index 33cf7f9..e3a31f1 100644 --- a/src/mainboard/google/brya/variants/rull/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/rull/memory/Makefile.mk @@ -8,3 +8,4 @@ SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 1(0b0001) Parts = K3KL8L80CM-MGCT, H58G56BK7BX068 SPD_SOURCES += spd/lp5/set-0/spd-8.hex # ID = 2(0b0010) Parts = K3KL9L90CM-MGCT SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 3(0b0011) Parts = H58G66BK8BX067 +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 4(0b0100) Parts = H58G56BK8BX068 diff --git a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt index 9a4250c..4c02501 100644 --- a/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/rull/memory/dram_id.generated.txt @@ -10,3 +10,4 @@ H58G56BK7BX068 1 (0001) K3KL9L90CM-MGCT 2 (0010) H58G66BK8BX067 3 (0011) +H58G56BK8BX068 4 (0100) diff --git a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt index 6b13e72..5b3e6ed 100644 --- a/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/rull/memory/mem_parts_used.txt @@ -15,3 +15,4 @@ H58G56BK7BX068 K3KL9L90CM-MGCT H58G66BK8BX067 +H58G56BK8BX068 -- To view, visit https://review.coreboot.org/c/coreboot/+/85117?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c4ad191a5e9703ee0f3bed150c816bfb098daf5 Gerrit-Change-Number: 85117 Gerrit-PatchSet: 1 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com>

1 0

[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Amanda Hwang, Dtrain Hsu, Paul Menzel, Pranava Y N, Subrata Banik. Ian Feng has posted comments on this change by Ian Feng. ( https://review.coreboot.org/c/coreboot/+/85037?usp=email ) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... Patch Set 11: (1 comment) Patchset: PS9: > Understood Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 11 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 08:09:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

1 0

[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Add overridetree
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Ian Feng, Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85116?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/fatcat/var/francka: Add overridetree ...................................................................... mb/google/fatcat/var/francka: Add overridetree Add override devicetree based on schematic_20241104. BUG=b:372395211 TEST=emerge-fatcat coreboot Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/fw_config.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 4 files changed, 428 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85116/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Gerrit-Change-Number: 85116 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Add overridetree
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Ian Feng, Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85116?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/google/fatcat/var/francka: Add overridetree ...................................................................... mb/google/fatcat/var/francka: Add overridetree Add override devicetree based on schematic_20241104. BUG=b:372395211 TEST=emerge-fatcat coreboot Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/fw_config.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 4 files changed, 428 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85116/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Gerrit-Change-Number: 85116 Gerrit-PatchSet: 2 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Add overridetree
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85116?usp=email ) Change subject: mb/google/fatcat/var/francka: Add overridetree ...................................................................... mb/google/fatcat/var/francka: Add overridetree Add override devicetree based on schematic_20241104. BUG=b:372395211 TEST=emerge-fatcat coreboot Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/fw_config.c M src/mainboard/google/fatcat/variants/francka/overridetree.cb 4 files changed, 429 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85116/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 8f93969..5fa2e77 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -9,6 +9,7 @@ select DRIVERS_INTEL_PMC select DRIVERS_INTEL_SOUNDWIRE select DRIVERS_WWAN_FM350GL + select DRIVERS_AUDIO_SOF select DRIVERS_SOUNDWIRE_ALC722 select DRIVERS_SPI_ACPI select DUMP_SMBIOS_TYPE17 @@ -133,7 +134,8 @@ config TPM_TIS_ACPI_INTERRUPT int - default 47 # GPE0_DW1_15 (GPP_D15) + default 47 if BOARD_GOOGLE_MODEL_FATCAT # GPE0_DW1_15 (GPP_D15) + default 11 if BOARD_GOOGLE_FRANCKA # GPE0_DW0_15 (GPP_H11) # FIXME: update as per board schematics config UART_FOR_CONSOLE diff --git a/src/mainboard/google/fatcat/variants/francka/Makefile.mk b/src/mainboard/google/fatcat/variants/francka/Makefile.mk index a49954c..bb28536 100644 --- a/src/mainboard/google/fatcat/variants/francka/Makefile.mk +++ b/src/mainboard/google/fatcat/variants/francka/Makefile.mk @@ -3,5 +3,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-y += gpio.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c diff --git a/src/mainboard/google/fatcat/variants/francka/fw_config.c b/src/mainboard/google/fatcat/variants/francka/fw_config.c new file mode 100644 index 0000000..f1c3d23 --- /dev/null +++ b/src/mainboard/google/fatcat/variants/francka/fw_config.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <bootstate.h> +#include <console/console.h> +#include <fw_config.h> +#include <gpio.h> +#include <inttypes.h> + +/* t: base table; o: override table */ +#define GPIO_PADBASED_OVERRIDE(t, o) gpio_padbased_override(t, o, ARRAY_SIZE(o)) +/* t: table */ +#define GPIO_CONFIGURE_PADS(t) gpio_configure_pads(t, ARRAY_SIZE(t)) + +static const struct pad_config hda_enable_pads[] = { + /* HDA_BIT_CLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* HDA_SDOUT */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* HDA_SDIN0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + + /* SOC_DMIC_CLK1 */ + PAD_CFG_NF(GPP_S06, NONE, DEEP, NF5), + /* SOC_DMIC_DATA1 */ + PAD_CFG_NF(GPP_S07, NONE, DEEP, NF5), + + PAD_NC(GPP_D09, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_S00, NONE), + PAD_NC(GPP_S01, NONE), + PAD_NC(GPP_S02, NONE), + PAD_NC(GPP_S03, NONE), + PAD_NC(GPP_S04, NONE), + PAD_NC(GPP_S05, NONE), +}; + +/* + * WWAN: power sequence requires three stages: + * step 1: 3.3V power, FCP# (Full Card Power), RST#, and PERST# off + * step 2: deassert FCP# + * step 3: deassert RST# first, and then PERST#. + * NOTE: Since PERST# is gated by platform reset, PERST# deassertion will happen + * at much later time and time between RST# and PERSET# is guaranteed. + */ +static const struct pad_config pre_mem_wwan_pwr_seq1_pads[] = { + /* GPP_A09: SOC_WWAN_OFF#_SW */ + PAD_CFG_GPO(GPP_A09, 0, PLTRST), + /* GPP_B20: SOC_WWAN_RST# */ + PAD_CFG_GPO(GPP_B20, 0, PLTRST), + /* GPP_D03: SOC_WWAN_PCIE_RST# */ + PAD_CFG_GPO(GPP_D03, 0, PLTRST), +}; + +static const struct pad_config pre_mem_wwan_pwr_seq2_pads[] = { + /* GPP_A09: SOC_WWAN_OFF#_SW */ + PAD_CFG_GPO(GPP_A09, 1, PLTRST), +}; + +static const struct pad_config wwan_pwr_seq3_pads[] = { + /* GPP_D03: SOC_WWAN_PCIE_RST# */ + PAD_CFG_GPO(GPP_D03, 1, PLTRST), + /* GPP_B20: SOC_WWAN_RST# */ + PAD_CFG_GPO(GPP_B20, 1, PLTRST), + /* GPP_E02: SOC_WWAN_WAKE2#_R */ + PAD_CFG_GPI_SCI_LOW(GPP_E02, NONE, DEEP, LEVEL), +}; + +static const struct pad_config wwan_disable_pads[] = { + /* GPP_A09: SOC_WWAN_OFF#_SW */ + PAD_NC(GPP_A09, NONE), + /* GPP_D03: SOC_WWAN_PCIE_RST# */ + PAD_NC(GPP_D03, NONE), + /* GPP_B20: SOC_WWAN_RST# */ + PAD_NC(GPP_B20, NONE), + /* GPP_A10: SOC_WWAN_RA_DIS#_SW */ + PAD_NC(GPP_A10, NONE), + /* GPP_E02: SOC_WWAN_WAKE2#_R */ + PAD_NC(GPP_E02, NONE), +}; + +static const struct pad_config bridge_disable_pads[] = { + /* GPP_D18: CLKREQ_PCIE#6 */ + PAD_NC(GPP_D18, NONE), +}; + +void fw_config_configure_pre_mem_gpio(void) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } + + if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT))) + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq1_pads); + + /* + * NOTE: We place WWAN sequence 2 here. According to the WWAN FIBOCOM + * FM350-GL datasheet, the minimum time requirement (Tpr: time between 3.3V + * and FCP#) is '0'. Therefore, it will be fine even though there is no + * GPIO configured for other PADs via fw_config to have the time delay + * introduced in between sequence 1 and 2. Also, FCP# was not the last PAD + * configured in sequence 1. Although the Tpr is '0' in the datasheet, three + * stages are preserved at this time to guarantee the sequence shown in the + * datasheet timing diagram. + */ + if (!fw_config_probe(FW_CONFIG(WWAN, WWAN_ABSENT))) + GPIO_CONFIGURE_PADS(pre_mem_wwan_pwr_seq2_pads); +} + +void fw_config_gpio_padbased_override(struct pad_config *padbased_table) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is not provisioned, Exiting\n"); + return; + } + + if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256M_CG_HDA))) + GPIO_PADBASED_OVERRIDE(padbased_table, hda_enable_pads); + + if (fw_config_probe(FW_CONFIG(WWAN, WWAN_PRESENT))) { + GPIO_PADBASED_OVERRIDE(padbased_table, wwan_pwr_seq3_pads); + } else { + GPIO_PADBASED_OVERRIDE(padbased_table, wwan_disable_pads); + } + + if (fw_config_probe(FW_CONFIG(BRIDGE, BRIDGE_HAYDEN))) { + GPIO_PADBASED_OVERRIDE(padbased_table, bridge_disable_pads); + } + +} diff --git a/src/mainboard/google/fatcat/variants/francka/overridetree.cb b/src/mainboard/google/fatcat/variants/francka/overridetree.cb index e38b186..5e37b87 100644 --- a/src/mainboard/google/fatcat/variants/francka/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/francka/overridetree.cb @@ -1,7 +1,297 @@ -chip soc/intel/pantherlake +fw_config + field PDC_CONTROL 0 1 + option PDC_RTS 0 + option PDC_TI 1 + end + field AUDIO 3 5 + option AUDIO_ALC256M_CG_HDA 0 + option AUDIO_ALC721_SNDW 1 + option AUDIO_CS42L43_CS35L56_SNDW 2 + option AUDIO_ALC722_ALC1320_SNDW 3 + end + field BRIDGE 6 7 + option BRIDGE_HAYDEN 0 + option BRIDGE_BARLOW 1 + option BRIDGE_GOTHIC 2 + end + field WWAN 8 + option WWAN_PRESENT 0 + option WWAN_ABSENT 1 + end +end +chip soc/intel/pantherlake + register "max_dram_speed_mts" = "7467" + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-A Port A0 + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port A1 + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C1 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # USB HUB (USB2 Camera) + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # CNVi BT or discrete BT + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #0 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3.2 x1 Type-A Con #1 + + register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + register "tcss_cap_policy[2]" = "TCSS_TYPE_C_PORT_FULL_FUN" + register "tcss_cap_policy[3]" = "TCSS_TYPE_C_PORT_FULL_FUN" + + # Enable EDP in PortA + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + }" + + # TCSS USB3 + register "tcss_aux_ori" = "1" + + register "serial_io_i2c_mode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoPci, + }" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| I2C1 | TPM(TI50) Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C4 | Touchscreen, Touchpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + device domain 0 on + device ref igpu on end + + device ref iaa off end + + device ref tbt_pcie_rp2 on end + device ref tbt_pcie_rp3 on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 2)" + device ref tcss_usb3_port3 on end + end + end + end + end + + device ref tcss_dma1 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port2 as dfp[0].typec_port + device generic 0 on end + end + chip drivers/intel/usb4/retimer + register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port3 as dfp[1].typec_port + device generic 0 on end + end + end + + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 0"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(4, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "group" = "ACPI_PLD_GROUP(5, 1)" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A16)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 0"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port2 on end + end + end + end + end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end # CNVi + # NOTE: i2c0 is function 0; hence it needs to be enabled when any of i2c1-5 is enabled. + # TPM device is under i2c3. Therefore, i2c0 needs to be enabled anyways. + device ref i2c0 on end + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_H11_IRQ)" + device i2c 50 on end + end + end # #I2C1 + device ref i2c4 on + chip drivers/i2c/hid + register "generic.hid" = ""ILTK0001"" + register "generic.desc" = ""ILITEK Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E01_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B08)" + register "generic.reset_delay_ms" = "200" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B18)" + register "generic.enable_delay_ms" = "12" + register "generic.has_power_resource" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 41 on end + end + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_EDGE_LOW(GPP_E18_IRQ)" + register "wake" = "GPE0_DW2_18" + register "probed" = "1" + device i2c 15 on end + end + end # I2C4 + + device ref pcie_rp2 on + probe WWAN WWAN_PRESENT + register "pcie_rp[PCIE_RP(2)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "5" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" + device generic 0 alias rp2_rtd3 on end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A09)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B20)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D03)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E02)" + register "add_acpi_dma_property" = "true" + use rp2_rtd3 as rtd3dev + device generic 0 on end + end + end # WWAN + device ref pcie_rp3 on + # Enable PCH PCIE x1 slot using CLK 2 + register "pcie_rp[PCIE_RP(3)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A08)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end # SD Card + device ref pcie_rp9 on + register "pcie_rp[PCIE_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" + register "srcclk_pin" = "1" + device generic 0 on end + end + end # M.2 SSD + + device ref smbus on end + device ref npk on end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on + probe AUDIO AUDIO_ALC256M_CG_HDA + end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F18_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F16)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H03)" + register "enable_delay_ms" = "3" + device spi 0 hidden end + end # FPMCU + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85116?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a50ca095922cdd67c3f2b13e4727608c3644d86 Gerrit-Change-Number: 85116 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[XS] Change in coreboot[main]: mb/google/fatcat/var/francka: Configure Kconfig for francka
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85115?usp=email ) Change subject: mb/google/fatcat/var/francka: Configure Kconfig for francka ...................................................................... mb/google/fatcat/var/francka: Configure Kconfig for francka 1. Select BOARD_GOOGLE_BASEBOARD_FATCAT for francka. 2. Set VARIANT_DIR to BOARD_GOOGLE_FRANCKA for francka. 3. Set TMP I2C bus to 0x01 for francka. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/Kconfig 1 file changed, 4 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/85115/1 diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig index 04ea54d..8f93969 100644 --- a/src/mainboard/google/fatcat/Kconfig +++ b/src/mainboard/google/fatcat/Kconfig @@ -68,7 +68,7 @@ select BOARD_GOOGLE_MODEL_FATCAT config BOARD_GOOGLE_FRANCKA - select BOARD_GOOGLE_MODEL_FATCAT + select BOARD_GOOGLE_BASEBOARD_FATCAT if BOARD_GOOGLE_FATCAT_COMMON @@ -103,7 +103,8 @@ config DRIVER_TPM_I2C_BUS hex - default 0x03 + default 0x03 if BOARD_GOOGLE_MODEL_FATCAT + default 0x01 if BOARD_GOOGLE_FRANCKA config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP @@ -145,6 +146,7 @@ config VARIANT_DIR string default "fatcat" if BOARD_GOOGLE_MODEL_FATCAT + default "francka" if BOARD_GOOGLE_FRANCKA config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" -- To view, visit https://review.coreboot.org/c/coreboot/+/85115?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5890a1f02ef88c591973c71a2adb2bba889733e7 Gerrit-Change-Number: 85115 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com>

1 0

[M] Change in coreboot[main]: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters
by Eric Lai (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85114?usp=email ) Change subject: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/telith/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85114/comment/cf04b9ca_60c9d22c?us… : PS1, Line 175: 5V > 5V NTC is used to detect the temperature of 5V power supply IC Please add in the code. or use "Power Supply" -- To view, visit https://review.coreboot.org/c/coreboot/+/85114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e Gerrit-Change-Number: 85114 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 07:24:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

1 0

[L] Change in coreboot[main]: mb/google/fatcat/var/francka: Update gpio settings
by Ian Feng (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Amanda Hwang, Dtrain Hsu, Paul Menzel, Pranava Y N, Subrata Banik. Hello Amanda Hwang, Pranava Y N, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85037?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Subrata Banik, Verified+1 by build bot (Jenkins) Change subject: mb/google/fatcat/var/francka: Update gpio settings ...................................................................... mb/google/fatcat/var/francka: Update gpio settings Configure GPIOs according to schematics_20241112. BUG=b:377819511 TEST=emerge-fatcat coreboot Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h A src/mainboard/google/fatcat/variants/francka/Makefile.mk A src/mainboard/google/fatcat/variants/francka/gpio.c M src/mainboard/google/fatcat/variants/francka/include/variant/gpio.h 4 files changed, 468 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85037/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/85037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I759df174a47a08319c1ada649d8bfb6f64b5aecd Gerrit-Change-Number: 85037 Gerrit-PatchSet: 10 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters
by Kun Liu (Code Review) 13 Nov '24

13 Nov '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Kun Liu has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85114?usp=email ) Change subject: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 1: (1 comment) File src/mainboard/google/brya/variants/telith/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85114/comment/51e1f205_3cb902ba?us… : PS1, Line 175: 5V > what is 5V? 5V NTC is used to detect the temperature of 5V power supply IC -- To view, visit https://review.coreboot.org/c/coreboot/+/85114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e Gerrit-Change-Number: 85114 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 13 Nov 2024 07:19:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com>

1 0

[M] Change in coreboot[main]: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters
by Eric Lai (Code Review) 12 Nov '24

12 Nov '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Kun Liu, Nick Vaccaro, Subrata Banik. Eric Lai has posted comments on this change by Kun Liu. ( https://review.coreboot.org/c/coreboot/+/85114?usp=email ) Change subject: mb/google/nissa/var/telith: Add 6W and 15W DPTF parameters ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85114?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cb44a707d7a87f5caaf259b069a21826f5c0a2e Gerrit-Change-Number: 85114 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 13 Nov 2024 06:40:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit November 2024