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Change subject: [DNM] treewide: Prepare mode switch code for dynamically generated paging
......................................................................
[DNM] treewide: Prepare mode switch code for dynamically generated paging
Make the long mode entry code generic to prepare for dynamically
generated page tables. entry64.inc now expects the caller to load
the page tables' address into the EAX register.
The mode switch assembly now stashes the previous page table address to
restore after the protected mode call is incomplete. Follow-up changes
will program/use dynamically generated tables for long mode calls,
the SIPI vector and SMM stub.
While we're here, fix qemu-x86 code to only get page table address and
include entry64.inc for 64-bit environments.
This is not a functional change.
Untested.
Change-Id: I1ef7c8bee0c38395d5436f6479f11b3a4208f53e
Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
M src/cpu/intel/car/core2/cache_as_ram.S
M src/cpu/intel/car/non-evict/cache_as_ram.S
M src/cpu/intel/car/p4-netburst/cache_as_ram.S
M src/cpu/qemu-x86/cache_as_ram_bootblock.S
M src/cpu/x86/64bit/entry64.inc
M src/cpu/x86/64bit/mode_switch.S
M src/cpu/x86/64bit/mode_switch2.S
M src/cpu/x86/64bit/pt.S
M src/cpu/x86/sipi_vector.S
M src/cpu/x86/smm/smm_stub.S
M src/soc/amd/common/block/cpu/noncar/pre_c.S
M src/soc/intel/common/block/cpu/car/cache_as_ram.S
12 files changed, 39 insertions(+), 8 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/79226/2
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Benjamin Doron has uploaded a new patch set (#6) to the change originally created by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/59874?usp=email )
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Change subject: arch/x86/c_start.S: Add proper x86_64 code
......................................................................
arch/x86/c_start.S: Add proper x86_64 code
Don't truncate upper bits in assembly code and thus allow loading
of ramstage above 4GiB.
Tested on qemu with cbmem_top set to TOUUD.
Change-Id: Ifc9b45f69d0b7534b2faacaad0d099cef2667478
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
Co-authored-by: Benjamin Doron <benjamin.doron(a)9elements.com>
---
M src/arch/x86/c_start.S
1 file changed, 24 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/59874/6
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Hello Felix Singer, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: mb/google/poppy: Use chipset dt reference names
......................................................................
mb/google/poppy: Use chipset dt reference names
Use the references from the chipset devicetree as this makes the
comments superfluous.
Built all variants with BUILD_TIMELESS=1 and the resulting binaries
remain the same.
Change-Id: I22bcde2dea726f47f8d64a762ca147efde0b610d
Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de>
---
M src/mainboard/google/poppy/variants/atlas/devicetree.cb
M src/mainboard/google/poppy/variants/baseboard/devicetree.cb
M src/mainboard/google/poppy/variants/nami/devicetree.cb
M src/mainboard/google/poppy/variants/nautilus/devicetree.cb
M src/mainboard/google/poppy/variants/nocturne/devicetree.cb
M src/mainboard/google/poppy/variants/rammus/devicetree.cb
M src/mainboard/google/poppy/variants/soraka/devicetree.cb
7 files changed, 380 insertions(+), 380 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79439/5
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Change subject: stoneyridge: Set the SPI read speed as 66MHz
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
Is this still needed, or can it be abandoned?
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Change subject: soc/amd/common/psp: Support PSP SMI handler
......................................................................
Patch Set 31:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/65523/comment/1b38cd4c_f044a9d4 :
PS31, Line 16: See AMD document 55570 revision 3.16 for additional details.
Is this public or NDA? Please mention this both here and below.
File src/soc/amd/common/block/psp/Kconfig:
https://review.coreboot.org/c/coreboot/+/65523/comment/e5442879_baf0fa17 :
PS31, Line 23: default n
This can probably be left out. By adding it, the default gets set, and nothing loaded after this can change it. If this line is not included, other Kconfig files loaded afterwards have the opportunity to set the default. If nothing sets it, the default value is 'n'.
Typically, if you want a default of 'n' it's best just to leave out the default line.
File src/soc/amd/common/block/psp/psp_def.h:
https://review.coreboot.org/c/coreboot/+/65523/comment/1ce20564_ca8ff616 :
PS31, Line 32:
Nit: Add a couple more tabs?
File src/soc/amd/common/block/psp/psp_gen2.c:
https://review.coreboot.org/c/coreboot/+/65523/comment/495fcd38_104025a7 :
PS31, Line 119: static bool is_valid_psp_spi_id(u64 id)
Put these in a separate file that's only pulled in when we're using PSP SPI code?
File src/soc/amd/common/block/psp/psp_p2c.c:
https://review.coreboot.org/c/coreboot/+/65523/comment/f29d84b0_9d3b4b3d :
PS31, Line 2: #include <device/mmio.h>
Nit: add an additional line under the SPDX header?
File src/soc/amd/common/block/spi/Kconfig:
https://review.coreboot.org/c/coreboot/+/65523/comment/d9309e5e_b0430e22 :
PS23, Line 104: SOC_AMD_COMMON_BLOCK_SPI_ALT
> This is when there is alternative SPIROM (dual SPIROM), which contains a backup of original SPI or a […]
So this isn't SMM specific? Can it go into a separate commit?
File src/soc/amd/stoneyridge/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/65523/comment/fb44a4b9_4d6bc038 :
PS31, Line 74:
Align
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Change subject: commonlib/fsp_relocate: Fix Coverity Issues
......................................................................
Patch Set 4:
(2 comments)
File src/commonlib/fsp_relocate.c:
https://review.coreboot.org/c/coreboot/+/68637/comment/026df7c5_cc166dee :
PS4, Line 230: offset_limit = roffset + rsize;
> Fixes issue reported as below: […]
As with below, this doesn't fix the problem that the roffset and rsize are not sanity checked before using them.
https://review.coreboot.org/c/coreboot/+/68637/comment/ff102579_ef2a815f :
PS4, Line 258: ptr = &pe_base[aoff];
> Fixes the below reported Coverity issue. […]
This doesn't verify the value though, so while it may get around the coverity warning, it doesn't "fix" it.
To fix the problem, you need to make sure that aoff is a reasonable value before using it as the offset.
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Change subject: Makefile.inc: Enable Wold-style-declaration command option
......................................................................
Patch Set 13: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71892/comment/2c5b5d88_d01937d1 :
PS12, Line 8:
> Add: […]
Done
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Change subject: Makefile.inc: Enable Wold-style-declaration command option
......................................................................
Makefile.inc: Enable Wold-style-declaration command option
Warn for obsolescent usages, according to the C Standard, in a
declaration. For example, warn if storage-class specifiers like static
are not the first things in a declaration.
Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/71892/13
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Change subject: Makefile.inc: Enable Wold-style-declaration command option
......................................................................
Patch Set 12: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71892/comment/97af7c00_550639f6 :
PS12, Line 8:
Add:
Warn for obsolescent usages, according to the C Standard, in a declaration. For example, warn if storage-class specifiers like static are not the first things in a declaration.
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Change subject: mb/google/brox: Disable package c state demotion
......................................................................
Patch Set 4: Code-Review+2
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