coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79760?usp=email ) Change subject: nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB ...................................................................... nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB MRC.bin doesn't write BANDTIMERS_SNB register, so drop the write. The bits written were targeting a reserved range, so assume it didn't do anything useful. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I920aabd60831c791188af976914553787cc0ff18 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79760/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f5e290..c62e1cd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2871,7 +2871,6 @@ mchbar_setbits32(MC_INIT_STATE_G, 1 << 0); mchbar_setbits32(MC_INIT_STATE_G, 1 << 7); - mchbar_write32(BANDTIMERS_SNB, 0xfa); /* Find a populated channel */ FOR_ALL_POPULATED_CHANNELS -- To view, visit https://review.coreboot.org/c/coreboot/+/79760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I920aabd60831c791188af976914553787cc0ff18 Gerrit-Change-Number: 79760 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79759?usp=email ) Change subject: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG ...................................................................... nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG A register dump between native and MRC.bin raminit showed a difference in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses. Tested on Lenovo X220: Still boots and works fine. Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/79759/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2e49675..3f5e290 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2833,7 +2833,10 @@ } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); - mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); + if (IS_SANDY_CPU(ctrl->cpu)) + mchbar_write32(PM_DLL_CONFIG, 0x000330f0); + else + mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Gerrit-Change-Number: 79759 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79758?usp=email ) Change subject: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode ...................................................................... nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79758/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c2a3051..2e49675 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,26 +667,32 @@ } /* Obtain optimal power down mode for current configuration */ -static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl, int channel) { + int slotrank; + if (ctrl->tXP > 8) return PDM_NONE; if (ctrl->tXPDLL > 32) return PDM_PPD; + FOR_ALL_POPULATED_RANKS + if (!ctrl->info.dimm[channel][slotrank >> 1].flags.dll_off_mode) + return PDM_APD_PPD; + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) return PDM_DLL_OFF; return PDM_APD_PPD; } -static u32 make_mr0(ramctr_timing *ctrl, u8 rank) +static u32 make_mr0(ramctr_timing *ctrl, int channel, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum power_down_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl, channel); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; @@ -715,7 +721,7 @@ static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, channel, rank)); } static odtmap get_ODT(ramctr_timing *ctrl, int channel) @@ -2818,13 +2824,13 @@ }; tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); - } - /* 64 DCLKs until idle, decision per rank */ - mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); + /* 64 DCLKs until idle, decision per rank */ + r32 = get_power_down_mode(ctrl, channel) << 8 | 64; + mchbar_write32(PM_PDWN_CONFIG_ch(channel), r32); - FOR_ALL_CHANNELS mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); + } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); -- To view, visit https://review.coreboot.org/c/coreboot/+/79758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Gerrit-Change-Number: 79758 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2024