coreboot-gerrit January 2024

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
by Arthur Heymans (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79758?usp=email ) Change subject: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Gerrit-Change-Number: 79758 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Jan 2024 09:28:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge ...................................................................... nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge On Sandy Bridge the MRC.bin sets bit SRT in register TC_MR2_SHADOW as well as it's currently done on Ivy Bridge. Tested on Lenovo X220: Still boots and works fine. Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79784/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 16751b9..2033043 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -783,6 +783,8 @@ int srt = 0; if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; + else if (IS_SANDY_CPU(ctrl->cpu)) + srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; u16 mr2reg = 0; mr2reg |= pasr; -- To view, visit https://review.coreboot.org/c/coreboot/+/79784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Gerrit-Change-Number: 79784 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79783?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis ...................................................................... nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis Improve mixed DIMM configurations by setting MR2 on per DIMM basis instead of using the common denominator. Drop now unused variables and bump the MRC_CACHE revision counter. The same is done on MRC.bin. Tested on Lenovo X220: Still boots and works fine. Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79783/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 085292b..f026043 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -200,9 +200,6 @@ memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap)); - ctrl->extended_temperature_range = 1; - ctrl->auto_self_refresh = 1; - FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; @@ -273,10 +270,6 @@ if (!dimm->flags.is_ecc) can_use_ecc = false; - ctrl->auto_self_refresh &= dimm->flags.asr; - - ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh; - ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot); printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index de24400..16751b9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -778,15 +778,16 @@ const u16 pasr = 0; const u16 cwl = ctrl->CWL - 5; const odtmap odt = get_ODT(ctrl, channel); + struct dimm_attr_ddr3_st *const dimm = &ctrl->info.dimm[channel][rank/2]; int srt = 0; if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) - srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; u16 mr2reg = 0; mr2reg |= pasr; mr2reg |= cwl << 3; - mr2reg |= ctrl->auto_self_refresh << 6; + mr2reg |= dimm->flags.asr << 6; mr2reg |= srt << 7; mr2reg |= (odt.rttwr / 60) << 9; @@ -795,7 +796,7 @@ /* Program MR2 shadow */ u32 reg32 = mchbar_read32(TC_MR2_SHADOW_ch(channel)); - reg32 &= 3 << 14 | 3 << 6; + reg32 &= 1 << (rank / 2 + 14) | 1 << (rank / 2 + 6); reg32 |= mr2reg & ~(3 << 6); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ee7c525..3303646 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -305,7 +305,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 enum power_down_mode { PDM_NONE = 0, @@ -410,9 +410,6 @@ int edge_offset[3]; int tx_dq_offset[3]; - int extended_temperature_range; - int auto_self_refresh; - int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; -- To view, visit https://review.coreboot.org/c/coreboot/+/79783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55 Gerrit-Change-Number: 79783 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Add tCPDED corner case
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79762?usp=email ) Change subject: nb/intel/sandybridge/raminit: Add tCPDED corner case ...................................................................... nb/intel/sandybridge/raminit: Add tCPDED corner case tCPDED is always 1, except for steppings earlier than SandyBridge D0. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79762/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 50c0fb4..de24400 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -172,7 +172,7 @@ .tXPDLL = MIN(ctrl->tXPDLL, 31), .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, - .tCPDED = 2, + .tCPDED = 1, .tPRPDEN = 1, }; @@ -2822,7 +2822,10 @@ union tc_othp_reg tc_othp = { .raw = mchbar_read32(TC_OTHP_ch(channel)), }; - tc_othp.tCPDED = 1; + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) < SNB_STEP_D0) + tc_othp.tCPDED = 2; + else + tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); /* 64 DCLKs until idle, decision per rank */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Gerrit-Change-Number: 79762 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Only write register on IvyBridge
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79761?usp=email ) Change subject: nb/intel/sandybridge/raminit: Only write register on IvyBridge ...................................................................... nb/intel/sandybridge/raminit: Only write register on IvyBridge Only write register WMM_READ_CONFIG on Ivy Bridge as it's reserved on Sandy Bridge. Tested on Lenovo X220: Still boots and runs fine. Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79761/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c62e1cd..50c0fb4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2815,8 +2815,8 @@ int t3_ns; u32 r32; - /* FIXME: This register only exists on Ivy Bridge */ - mchbar_write32(WMM_READ_CONFIG, 0x46); + if (IS_IVY_CPU(ctrl->cpu)) + mchbar_write32(WMM_READ_CONFIG, 0x46); FOR_ALL_CHANNELS { union tc_othp_reg tc_othp = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Gerrit-Change-Number: 79761 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79760?usp=email ) Change subject: nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB ...................................................................... nb/intel/sandybridge/raminit: Drop write to BANDTIMERS_SNB MRC.bin doesn't write BANDTIMERS_SNB register, so drop the write. The bits written were targeting a reserved range, so assume it didn't do anything useful. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I920aabd60831c791188af976914553787cc0ff18 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/79760/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3f5e290..c62e1cd 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2871,7 +2871,6 @@ mchbar_setbits32(MC_INIT_STATE_G, 1 << 0); mchbar_setbits32(MC_INIT_STATE_G, 1 << 7); - mchbar_write32(BANDTIMERS_SNB, 0xfa); /* Find a populated channel */ FOR_ALL_POPULATED_CHANNELS -- To view, visit https://review.coreboot.org/c/coreboot/+/79760?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I920aabd60831c791188af976914553787cc0ff18 Gerrit-Change-Number: 79760 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79759?usp=email ) Change subject: nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG ...................................................................... nb/intel/sandybridge/raminit: Update PM_DLL_CONFIG A register dump between native and MRC.bin raminit showed a difference in the PM_DLL_CONFIG register. Use the same value as MRC.bin uses. Tested on Lenovo X220: Still boots and works fine. Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/79759/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 2e49675..3f5e290 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2833,7 +2833,10 @@ } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); - mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); + if (IS_SANDY_CPU(ctrl->cpu)) + mchbar_write32(PM_DLL_CONFIG, 0x000330f0); + else + mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); FOR_ALL_CHANNELS { switch (ctrl->rankmap[channel]) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79759?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf6334814c5748e5a3691a572213f433c79f382d Gerrit-Change-Number: 79759 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79758?usp=email ) Change subject: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode ...................................................................... nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79758/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c2a3051..2e49675 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,26 +667,32 @@ } /* Obtain optimal power down mode for current configuration */ -static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl, int channel) { + int slotrank; + if (ctrl->tXP > 8) return PDM_NONE; if (ctrl->tXPDLL > 32) return PDM_PPD; + FOR_ALL_POPULATED_RANKS + if (!ctrl->info.dimm[channel][slotrank >> 1].flags.dll_off_mode) + return PDM_APD_PPD; + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) return PDM_DLL_OFF; return PDM_APD_PPD; } -static u32 make_mr0(ramctr_timing *ctrl, u8 rank) +static u32 make_mr0(ramctr_timing *ctrl, int channel, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum power_down_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl, channel); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; @@ -715,7 +721,7 @@ static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, channel, rank)); } static odtmap get_ODT(ramctr_timing *ctrl, int channel) @@ -2818,13 +2824,13 @@ }; tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); - } - /* 64 DCLKs until idle, decision per rank */ - mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); + /* 64 DCLKs until idle, decision per rank */ + r32 = get_power_down_mode(ctrl, channel) << 8 | 64; + mchbar_write32(PM_PDWN_CONFIG_ch(channel), r32); - FOR_ALL_CHANNELS mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); + } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); -- To view, visit https://review.coreboot.org/c/coreboot/+/79758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Gerrit-Change-Number: 79758 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit January 2024