coreboot-gerrit January 2024

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[M] Change in coreboot[main]: mb/google/fizz: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79327?usp=email ) Change subject: mb/google/fizz: Make use of chipset devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Gerrit-Change-Number: 79327 Gerrit-PatchSet: 4 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:56:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/razer: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79326?usp=email ) Change subject: mb/razer: Make use of chipset devicetree ...................................................................... mb/razer: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting binary remains the same. Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 17 insertions(+), 44 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index f88c99d..1323164 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,16 +170,12 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # Thermal Subsystem - device pci 08.0 off end # Gaussian Mixture Model - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera - device pci 15.0 on end # I2C Controller #0 - device pci 15.1 on + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref i2c0 on end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" @@ -188,33 +184,13 @@ register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end - end # I2C Controller #1 - device pci 15.2 off end # I2C Controller #2 - device pci 15.3 off end # I2C Controller #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C Controller #4 - device pci 19.1 off end # I2C Controller #5 - device pci 19.2 off end # UART #2 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 off end # Serial IO UART0 - device pci 1e.6 off end # SDXC - device pci 1f.0 on # LPC + end + device ref heci1 on end + device ref uart2 on end + device ref pcie_rp1 on end + device ref pcie_rp5 on end + device ref pcie_rp9 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -236,12 +212,9 @@ device pnp 6e.18 off end device pnp 6e.19 off end end #superio/ite/it8528e - end # LPC Bridge - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Gerrit-Change-Number: 79326 Gerrit-PatchSet: 5 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/razer: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79326?usp=email ) Change subject: mb/razer: Make use of chipset devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Gerrit-Change-Number: 79326 Gerrit-PatchSet: 4 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:39:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/intel/kblrvp: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79325?usp=email ) Change subject: mb/intel/kblrvp: Make use of chipset devicetree ...................................................................... mb/intel/kblrvp: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 5 files changed, 59 insertions(+), 86 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b015fc6..b282657 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -111,50 +111,23 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref uart2 on end + device ref i2c4 on end + device ref pcie_rp1 on end + device ref pcie_rp9 on end + device ref uart0 on end + device ref emmc on end + device ref sdxc on end + device ref smbus on end + device ref fast_spi on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 9d6dd99..b580e76 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -107,14 +107,14 @@ }" device domain 0 on - device pci 04.0 off end # SA thermal subsystem - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.2 off end # I2C #4 - device pci 1e.4 off end # eMMC - device pci 1e.6 off end # SDCard - device pci 1f.3 on end # Intel HDA - device pci 1f.6 on end # GbE + device ref sa_thermal off end + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref i2c4 off end + device ref emmc off end + device ref sdxc off end + device ref hda on end + device ref gbe on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 4a1c67b..b7c4395 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -113,18 +113,18 @@ }" device domain 0 on - device pci 05.0 on end # SA IMGU - device pci 14.3 on end # Camera - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 - device pci 1d.0 on end # PCI Express Port 9 x1 WLAN - device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG - device pci 1f.0 on + device ref imgu on end + device ref cio on end + device ref pcie_rp1 on end # x4 SLOT1 + device ref pcie_rp5 on end # x1 SLOT2/LAN + device ref pcie_rp6 on end # x1 SLOT3 + device ref pcie_rp9 on end # x1 WLAN + device ref pcie_rp10 on end # x1 WIGIG + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end - end # LPC Interface - device pci 1f.3 on end # Intel HDA + end + device ref hda on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index f7baaa8..c5b7e94 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -155,17 +155,17 @@ device cpu_cluster 0 on end device domain 0 on - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1f.0 on + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end - end # LPC Interface + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 71deaa5..2291c63 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -160,21 +160,21 @@ }" device domain 0 on - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.2 off end # I2C #4 - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1e.4 off end # eMMC - device pci 1e.6 off end # SDXC - device pci 1f.0 on + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref i2c4 off end + device ref pcie_rp1 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref emmc off end + device ref sdxc off end + device ref lpc_espi on #chip drivers/pc80/tpm # device pnp 0c31.0 on end #end - end # LPC Interface - device pci 1f.6 on end # GbE + end + device ref gbe on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Gerrit-Change-Number: 79325 Gerrit-PatchSet: 6 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/intel/kblrvp: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79325?usp=email ) Change subject: mb/intel/kblrvp: Make use of chipset devicetree ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Some of the variant overridetrees have a duplicated configuration to the common devicetree, but they can be cleaned up in a follow-up patch. Otherwise it looks good to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/79325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Gerrit-Change-Number: 79325 Gerrit-PatchSet: 5 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mainboard/amd/birman: Add Birmanplus board variant support for Phoeni...
by Anand Vaikar (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Paul Menzel. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79283?usp=email ) Change subject: mainboard/amd/birman: Add Birmanplus board variant support for Phoenix SOC ...................................................................... Patch Set 6: (1 comment) File src/mainboard/amd/birman/variants/birmanplus/port_descriptors.c: https://review.coreboot.org/c/coreboot/+/79283/comment/f76d3ac5_352f8a8f : PS5, Line 153: printk(BIOS_NOTICE, : "Display connector type couldn't be determined. Disabling DDI1.\n"); > This sounds like error level, and also should be elaborated on, that there is something wrong with t […] this indicates that there was an issue with reading the connector type. System will continue to boot and user action is generally not required unless there is an issue with getting video. -- To view, visit https://review.coreboot.org/c/coreboot/+/79283?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I40f196d8a662d19e424511febca24edb88d686dd Gerrit-Change-Number: 79283 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Jan 2024 09:18:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/glinda: Update the maximum CPU threads for glinda
by Anand Vaikar (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Paul Menzel, ritul guru. Anand Vaikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79509?usp=email ) Change subject: soc/amd/glinda: Update the maximum CPU threads for glinda ...................................................................... Patch Set 6: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79509/comment/e65a4186_e5aa130d : PS1, Line 7: Update the MAX_CPUS config option for glinda > Please be more specific. Done https://review.coreboot.org/c/coreboot/+/79509/comment/2ab975f9_48248d8f : PS1, Line 8: > Please elaborate. Done Patchset: PS6: Addressed comments. -- To view, visit https://review.coreboot.org/c/coreboot/+/79509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Gerrit-Change-Number: 79509 Gerrit-PatchSet: 6 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Jan 2024 08:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value
by Eric Lai (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Matt Chen, Shou-Chieh Hsu, Simon Yang. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79740?usp=email ) Change subject: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Gerrit-Change-Number: 79740 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 07:20:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value
by Rex Chou (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Eric Lai, Matt Chen, Shou-Chieh Hsu, Simon Yang. Rex Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79740?usp=email ) Change subject: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Gerrit-Change-Number: 79740 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 07:16:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value
by Simon Yang (Code Review) 02 Jan '24

02 Jan '24

Simon Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79740?usp=email ) Change subject: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Gerrit-Change-Number: 79740 Gerrit-PatchSet: 1 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 02 Jan 2024 07:05:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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