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Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
......................................................................
mb/intel/mtlrvp: add 512KB SI_EC FMAP region
This patch introduces the 512KB SI_EC FMAP region for storing the EC
firmware, a necessary addition to support EC chips without internal
flash memory.
As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction
with the Microchip EC1723, and the changes are verified.
Cq-Depend: chrome-internal:6691498
Cq-Depend: chrome-internal:6741356
BUG=b:289783489
TEST=build "emerge-rex coreboot chromeos-bootimage" is successful.
changes are verified.
EC Log:
23-11-06 17:46:49.564 --- UART initialized after reboot ---
23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3,
os:f660f7,cmsis:42cf18,picolibc:6669e4]
23-11-06 17:46:54.609 D: Power state: S5 --> S5S4
23-11-06 17:46:54.620 D: Power state: S5S4 --> S4
23-11-06 17:46:54.620 D: Power state: S4 --> S4S3
23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087
23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0
Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84
Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com>
---
M src/mainboard/intel/mtlrvp/chromeos.fmd
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/10
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Hello Balaji Manigandan, Deepti Deshatty, Kapil Porwal, Krishna P Bhat D, Subrata Banik, Vijay P Hiremath, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Vijay P Hiremath, Verified+1 by build bot (Jenkins)
Change subject: mb/intel/mtlrvp: define a new config for Chrome EC
......................................................................
mb/intel/mtlrvp: define a new config for Chrome EC
Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for
Chrome ECs utilizing an external shared SPI flash.
BUG=b:289783489
TEST=emerge-rex coreboot chromeos-bootimage is successful
Cq-Depend: chrome-internal:6691498
Cq-Depend: chrome-internal:6741356
Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f
Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com>
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 16 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/79211/6
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Change subject: vendorcode/google/chromeos: Use unsigned int for "factory_config"
......................................................................
Patch Set 1:
(1 comment)
File src/vendorcode/google/chromeos/tpm_factory_config.c:
https://review.coreboot.org/c/coreboot/+/79769/comment/ef9a69ed_5443893c :
PS1, Line 27: rc = tlcl_cr50_get_factory_config(&factory_config);
> This function should assert `factory_config != CHROMEOS_ERROR` after this call also, to catch any ch […]
Acknowledged
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Verified+1 by build bot (Jenkins)
Change subject: vendorcode/google/chromeos: Use unsigned int for "factory_config"
......................................................................
vendorcode/google/chromeos: Use unsigned int for "factory_config"
This patch ensures `chromeos_get_factory_config()` returns an
unsigned integer value because factory config represents
bit-fields to determine the Chromebook Plus branding.
Additionally, introduced safety measures to catch future
"factory_config" bit-field exhaustion.
BUG=b:317880956
TEST=Able to verify that google/screebo is branded as
Chromebook Plus.
Change-Id: I3021b8646de4750b4c8e2a2981f42500894fa2d0
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/vendorcode/google/chromeos/chromeos.h
M src/vendorcode/google/chromeos/tpm_factory_config.c
2 files changed, 15 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/79769/2
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Hello Balaji Manigandan, Eric Lai, Kapil Porwal, Krishna P Bhat D, Subrata Banik, Vijay P Hiremath, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#8).
Change subject: mb/intel/mtlrvp: add 512KB SI_EC FMAP region
......................................................................
mb/intel/mtlrvp: add 512KB SI_EC FMAP region
This patch introduces the 512KB SI_EC FMAP region for storing the EC
firmware, a necessary addition to support EC chips without internal
flash memory.
As a testing platform, the MTLRVP Chrome SKU is utilized in conjunction
with the Microchip EC1723, and the changes are verified.
Cq-Depend: chrome-internal:6691498
Cq-Depend: chrome-internal:6741356
BUG=b:289783489
TEST=build "emerge-rex coreboot chromeos-bootimage" is successful.
changes are verified.
EC Log:
23-11-06 17:46:49.564 --- UART initialized after reboot ---
23-11-06 17:46:49.564 [Image: RO, mtlrvpp_m1723_v3.5.142816-ec:6596a3,os:f660f7,cmsis:42cf18,picolibc:6669e4 2023-11-03 23:01:58 root@cssdesk-voxel]
23-11-06 17:46:54.609 D: Power state: S5 --> S5S4
23-11-06 17:46:54.620 D: Power state: S5S4 --> S4
23-11-06 17:46:54.620 D: Power state: S4 --> S4S3
23-11-06 17:46:54.642 I: power state 10 = S3S0, in 0x0087
23-11-06 17:46:54.642 ec:~>: Power state: S3S0 --> S0
Change-Id: I788dbeaad05e5d6904fb2c7c681a0bf653dc7d84
Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com>
---
M src/mainboard/intel/mtlrvp/chromeos.fmd
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/79209/8
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Change subject: lib/lzmadecode: Allow for 8 byte reads on 64bit
......................................................................
Patch Set 2: Code-Review+2
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Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS3:
> I found out why S3 didn't work for me, and it was not your patch. […]
(fixed by CB:78205)
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Change subject: vboot: Add firmware PCR support
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79437/comment/2e18dfff_14fdf10b :
PS6, Line 24: to 10 (and we plan to use PCR 12 for kernel version).
> double-extension prevention for PCR0 is a very special case. […]
Done.
Removed the usage of PCR12, and combined them into the PCR10.
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I'd like you to reexamine a change. Please visit
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Change subject: vboot: Add firmware PCR support
......................................................................
vboot: Add firmware PCR support
To verify the boot chain, we will need to extend the PCR with the
firmware version. And the server will be able to attest the firmware
version of devices.
The "firmware version" here is the RW firmware anti-rollback version,
determined by the ChromeOS's signing infra, and will be verified in
vb2api_fw_phase3, by comparing it with the version stored in the TPM.
This version will be increased when there is critical vulnerability
in the RW firmware.
According to [1], PCRs 8-15 usage is defined by Static OS. Therefore
PCR_FW_VER is chosen to be within that range. Ideally the existing
PCR_BOOT_MODE and PCR_HWID should also be allocated in the same range,
but unfortunately it's too late to fix them. Because PCRs 11 and 13
have been used for other purposes in ChromeOS, here PCR_FW_VER is set
to 10.
[1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05…
BUG=b:248610274
TEST=Boot the device, and check the PCR 10
BRANCH=none
Signed-off-by: Yi Chou <yich(a)google.com>
Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61
---
M src/security/tpm/Kconfig
M src/security/vboot/tpm_common.c
M src/security/vboot/vboot_logic.c
3 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/79437/7
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