coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT
by Matt DeVillier (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79566?usp=email ) Change subject: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/79566/comment/1b5b6919_baf7b4b0 : PS3, Line 322: non-fixed APMC SMI command port what exactly does non-fixed mean here? dynamically assigned by another firmware component? -- To view, visit https://review.coreboot.org/c/coreboot/+/79566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Gerrit-Change-Number: 79566 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 02 Jan 2024 16:11:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API to read factory config
by Subrata Banik (Code Review) 02 Jan '24

02 Jan '24

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79737?usp=email ) Change subject: vendorcode/google/chromeos: Add API to read factory config ...................................................................... Patch Set 8: (1 comment) File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/79737/comment/8e1853ac_4291ddf9 : PS8, Line 7: int64_t > I don't think it's a good idea to make this signed everywhere, it's not a signed number, it's a bit field. Even if the top bit will never be allocated, making it signed is confusing. > > You can still use `~(uint64_t)0` as a sentinel value even if it's an unsigned number (e.g. like `UNDEFINED_FW_CONFIG`). good suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/79737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Gerrit-Change-Number: 79737 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 02 Jan 2024 15:08:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vendorcode/google/chromeos: Add API to read factory config
by Julius Werner (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Subrata Banik. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79737?usp=email ) Change subject: vendorcode/google/chromeos: Add API to read factory config ...................................................................... Patch Set 8: (1 comment) File src/vendorcode/google/chromeos/tpm_factory_config.c: https://review.coreboot.org/c/coreboot/+/79737/comment/d90e81ca_4a4b2b2a : PS8, Line 7: int64_t I don't think it's a good idea to make this signed everywhere, it's not a signed number, it's a bit field. Even if the top bit will never be allocated, making it signed is confusing. You can still use `~(uint64_t)0` as a sentinel value even if it's an unsigned number (e.g. like `UNDEFINED_FW_CONFIG`). -- To view, visit https://review.coreboot.org/c/coreboot/+/79737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I34f47c9a94972534cda656ef624ef12ed5ddeb06 Gerrit-Change-Number: 79737 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 14:53:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: vboot: Add firmware PCR support
by Julius Werner (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Andrey Pronin, Christian Walter, Paul Menzel, Yi Chou, Yu-Ping Wu. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79437?usp=email ) Change subject: vboot: Add firmware PCR support ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79437/comment/286c0ffe_2e1da777 : PS6, Line 24: to 10 (and we plan to use PCR 12 for kernel version). > hmmm, those were discussed in go/cros-arm-widevine-cert […] Well, I don't really see anything specifically talking about two separate PCRs in that doc. I think this is just a matter of us all starting with different assumptions and never really talking about it. I had always assumed we were talking about a single PCR (because the limited number of PCRs was mentioned as a potential concern earlier). Let's add +Andrey to see what he thinks. Double-extend should no longer be a concern on future boards (especially not on Arm boards, it had only ever been an issue on x86). Even if it ever came up again we could still add a different hack to Ti50 that just counts the amount of times the PCR is extended and stops it after 2, so it's not like we'd be potentially locking out such workarounds completely. But it shouldn't be necessary anyway. -- To view, visit https://review.coreboot.org/c/coreboot/+/79437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Gerrit-Change-Number: 79437 Gerrit-PatchSet: 6 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Yi Chou <yich(a)google.com> Gerrit-Attention: Andrey Pronin <apronin(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 14:28:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Yi Chou <yich(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/fizz: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79327?usp=email ) Change subject: mb/google/fizz: Make use of chipset devicetree ...................................................................... mb/google/fizz: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79327 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/fizz/variants/endeavour/overridetree.cb M src/mainboard/google/fizz/variants/fizz/overridetree.cb M src/mainboard/google/fizz/variants/karma/overridetree.cb 4 files changed, 54 insertions(+), 74 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 46069ce..44fc014 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -307,10 +307,9 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on chip drivers/usb/acpi register "desc" = ""Root Hub"" register "type" = "UPC_TYPE_HUB" @@ -362,78 +361,59 @@ end end end - end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera - device pci 15.0 on end # I2C #0 - device pci 15.1 off end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 on end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 - device pci 19.2 off end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - # PCI Express Port 3 for LAN, will be swapped to port 1 by FSP - device pci 1c.2 on + end + device ref thermal on end + device ref i2c0 on end + device ref i2c2 on end + device ref heci1 on end + device ref sata on end + device ref uart2 on end + device ref i2c5 on end + device ref pcie_rp1 on end + device ref pcie_rp3 on + # LAN, will be swapped to port 1 by FSP chip drivers/net register "customized_leds" = "0x0fa5" register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end register "device_index" = "0" end - end # PCI Express Port 3 - device pci 1c.3 on + end + device ref pcie_rp4 on + # WLAN chip drivers/wifi/generic register "wake" = "GPE0_PCI_EXP" device pci 00.0 on end end - end # PCI Express Port 4 for WLAN - device pci 1c.4 on end # PCI Express Port 5 for NVMe - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on # PCI Express Port 9 for 2nd LAN + end + device ref pcie_rp5 on end # NVMe + device ref pcie_rp9 on + # 2nd LAN chip drivers/net register "customized_leds" = "0x0fa5" register "device_index" = "1" device pci 00.0 on end end - end # PCI Express Port 9 for BtoB - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 on end # PCI Express Port 11 - device pci 1d.3 on end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 on + end + device ref pcie_rp11 on end + device ref pcie_rp12 on end + device ref uart0 on end + device ref gspi0 on chip drivers/spi/acpi register "hid" = "ACPI_DT_NAMESPACE_HID" register "compat_string" = ""google,cr50"" register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E0_IRQ)" device spi 0 on end end - end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 off end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on + end + device ref sdxc on end + device ref lpc_espi on chip ec/google/chromeec device pnp 0c09.0 on end end - end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end diff --git a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb index 07ed7bc..989b2406 100644 --- a/src/mainboard/google/fizz/variants/endeavour/overridetree.cb +++ b/src/mainboard/google/fizz/variants/endeavour/overridetree.cb @@ -77,7 +77,7 @@ }" device domain 0 on - device pci 14.0 on + device ref south_xhci on chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi @@ -128,8 +128,8 @@ device usb 3.5 off end end end - end # USB xHCI - device pci 15.3 on + end + device ref i2c3 on chip drivers/i2c/generic register "hid" = "ACPI_DT_NAMESPACE_HID" register "desc" = ""Chrontel 7322"" @@ -146,8 +146,8 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_HIGH(GPP_A20)" device i2c 76 on end end - end # I2C #3 - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""10EC5663"" register "name" = ""RT53"" @@ -155,12 +155,12 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" device i2c 13 on end end - end # I2C #5 - device pci 1c.6 on end # PCI Express Port 7 for TPU1 - device pci 1c.7 on end # PCI Express Port 8 for TPU0 - device pci 1d.0 on end # PCI Express Port 9 for POE LAN - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 + end + device ref pcie_rp7 on end # TPU1 + device ref pcie_rp8 on end # TPU0 + device ref pcie_rp9 on end # POE LAN + device ref pcie_rp10 off end + device ref pcie_rp11 off end + device ref pcie_rp12 off end end end diff --git a/src/mainboard/google/fizz/variants/fizz/overridetree.cb b/src/mainboard/google/fizz/variants/fizz/overridetree.cb index b4eea38..e17d148 100644 --- a/src/mainboard/google/fizz/variants/fizz/overridetree.cb +++ b/src/mainboard/google/fizz/variants/fizz/overridetree.cb @@ -8,7 +8,7 @@ register "SaGv" = "SaGv_FixedHigh" device domain 0 on - device pci 14.0 on + device ref south_xhci on chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi @@ -33,8 +33,8 @@ end end end - end # USB xHCI - device pci 19.1 on + end + device ref i2c5 on chip drivers/i2c/generic register "hid" = ""10EC5663"" register "name" = ""RT53"" @@ -42,6 +42,6 @@ register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D9)" device i2c 13 on end end - end # I2C #5 + end end end diff --git a/src/mainboard/google/fizz/variants/karma/overridetree.cb b/src/mainboard/google/fizz/variants/karma/overridetree.cb index 1dba50c..d1dc46f 100644 --- a/src/mainboard/google/fizz/variants/karma/overridetree.cb +++ b/src/mainboard/google/fizz/variants/karma/overridetree.cb @@ -22,7 +22,7 @@ }" device domain 0 on - device pci 14.0 on + device ref south_xhci on chip drivers/usb/acpi device usb 0.0 on chip drivers/usb/acpi @@ -57,8 +57,8 @@ end end end - end # USB xHCI - device pci 19.1 on + end + device ref i2c5 on chip drivers/generic/max98357a register "hid" = ""MX98357A"" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" @@ -82,7 +82,7 @@ register "mic_amp_in_sel" = ""diff"" device i2c 1a on end end - end # I2C #5 - device pci 1e.6 off end # SDCard + end + device ref sdxc off end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Gerrit-Change-Number: 79327 Gerrit-PatchSet: 5 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/google/fizz: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79327?usp=email ) Change subject: mb/google/fizz: Make use of chipset devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79327?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7752819091e2a75c8d818f7d0cf90eabc11c4759 Gerrit-Change-Number: 79327 Gerrit-PatchSet: 4 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:56:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/razer: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79326?usp=email ) Change subject: mb/razer: Make use of chipset devicetree ...................................................................... mb/razer: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built razer/blade_stealth_kbl with BUILD_TIMELESS=1 and the resulting binary remains the same. Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79326 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 1 file changed, 17 insertions(+), 44 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index f88c99d..1323164 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -170,16 +170,12 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # Thermal Subsystem - device pci 08.0 off end # Gaussian Mixture Model - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 14.3 off end # Camera - device pci 15.0 on end # I2C Controller #0 - device pci 15.1 on + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref i2c0 on end + device ref i2c1 on chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Synaptics Touchpad"" @@ -188,33 +184,13 @@ register "hid_desc_reg_offset" = "0x20" device i2c 0x2c on end end - end # I2C Controller #1 - device pci 15.2 off end # I2C Controller #2 - device pci 15.3 off end # I2C Controller #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # I2C Controller #4 - device pci 19.1 off end # I2C Controller #5 - device pci 19.2 off end # UART #2 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 off end # Serial IO UART0 - device pci 1e.6 off end # SDXC - device pci 1f.0 on # LPC + end + device ref heci1 on end + device ref uart2 on end + device ref pcie_rp1 on end + device ref pcie_rp5 on end + device ref pcie_rp9 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -236,12 +212,9 @@ device pnp 6e.18 off end device pnp 6e.19 off end end #superio/ite/it8528e - end # LPC Bridge - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 on end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + end + device ref hda on end + device ref smbus on end + device ref fast_spi on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Gerrit-Change-Number: 79326 Gerrit-PatchSet: 5 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/razer: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79326?usp=email ) Change subject: mb/razer: Make use of chipset devicetree ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79326?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ffda6ee37e146e894a271c553e998a269c19294 Gerrit-Change-Number: 79326 Gerrit-PatchSet: 4 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:39:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/intel/kblrvp: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79325?usp=email ) Change subject: mb/intel/kblrvp: Make use of chipset devicetree ...................................................................... mb/intel/kblrvp: Make use of chipset devicetree Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Built all variants with BUILD_TIMELESS=1 and the resulting binaries remain the same. Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Signed-off-by: Marvin Evers <marvin.evers(a)stud.hs-bochum.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79325 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 5 files changed, 59 insertions(+), 86 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb index b015fc6..b282657 100644 --- a/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/kblrvp/variants/baseboard/devicetree.cb @@ -111,50 +111,23 @@ device cpu_cluster 0 on end device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Integrated Graphics Device - device pci 04.0 on end # SA thermal subsystem - device pci 14.0 on end # USB xHCI - device pci 14.1 off end # USB xDCI (OTG) - device pci 14.2 on end # Thermal Subsystem - device pci 15.0 on end # I2C #0 - device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT Redirection - device pci 16.4 off end # Management Engine Interface 3 - device pci 17.0 off end # SATA - device pci 19.0 on end # UART #2 - device pci 19.1 off end # I2C #5 - device pci 19.2 on end # I2C #4 - device pci 1c.0 on end # PCI Express Port 1 - device pci 1c.1 off end # PCI Express Port 2 - device pci 1c.2 off end # PCI Express Port 3 - device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 - device pci 1c.5 off end # PCI Express Port 6 - device pci 1c.6 off end # PCI Express Port 7 - device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 - device pci 1d.1 off end # PCI Express Port 10 - device pci 1d.2 off end # PCI Express Port 11 - device pci 1d.3 off end # PCI Express Port 12 - device pci 1e.0 on end # UART #0 - device pci 1e.1 off end # UART #1 - device pci 1e.2 off end # GSPI #0 - device pci 1e.3 off end # GSPI #1 - device pci 1e.4 on end # eMMC - device pci 1e.5 off end # SDIO - device pci 1e.6 on end # SDCard - device pci 1f.0 on end # LPC Interface - device pci 1f.1 on end # P2SB - device pci 1f.2 on end # Power Management Controller - device pci 1f.3 off end # Intel HDA - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # PCH SPI - device pci 1f.6 off end # GbE + device ref igpu on end + device ref sa_thermal on end + device ref south_xhci on end + device ref thermal on end + device ref i2c0 on end + device ref i2c1 on end + device ref i2c2 on end + device ref i2c3 on end + device ref heci1 on end + device ref uart2 on end + device ref i2c4 on end + device ref pcie_rp1 on end + device ref pcie_rp9 on end + device ref uart0 on end + device ref emmc on end + device ref sdxc on end + device ref smbus on end + device ref fast_spi on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 9d6dd99..b580e76 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -107,14 +107,14 @@ }" device domain 0 on - device pci 04.0 off end # SA thermal subsystem - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.2 off end # I2C #4 - device pci 1e.4 off end # eMMC - device pci 1e.6 off end # SDCard - device pci 1f.3 on end # Intel HDA - device pci 1f.6 on end # GbE + device ref sa_thermal off end + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref i2c4 off end + device ref emmc off end + device ref sdxc off end + device ref hda on end + device ref gbe on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 4a1c67b..b7c4395 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -113,18 +113,18 @@ }" device domain 0 on - device pci 05.0 on end # SA IMGU - device pci 14.3 on end # Camera - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN - device pci 1c.5 on end # PCI Express Port 6 x1 SLOT3 - device pci 1d.0 on end # PCI Express Port 9 x1 WLAN - device pci 1d.1 on end # PCI Express Port 10 x1 WIGIG - device pci 1f.0 on + device ref imgu on end + device ref cio on end + device ref pcie_rp1 on end # x4 SLOT1 + device ref pcie_rp5 on end # x1 SLOT2/LAN + device ref pcie_rp6 on end # x1 SLOT3 + device ref pcie_rp9 on end # x1 WLAN + device ref pcie_rp10 on end # x1 WIGIG + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end - end # LPC Interface - device pci 1f.3 on end # Intel HDA + end + device ref hda on end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index f7baaa8..c5b7e94 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -155,17 +155,17 @@ device cpu_cluster 0 on end device domain 0 on - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1c.5 on end # PCI Express Port 6 - device pci 1f.0 on + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref pcie_rp6 on end + device ref lpc_espi on chip drivers/pc80/tpm device pnp 0c31.0 on end end - end # LPC Interface + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 71deaa5..2291c63 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -160,21 +160,21 @@ }" device domain 0 on - device pci 15.2 off end # I2C #2 - device pci 15.3 off end # I2C #3 - device pci 17.0 on end # SATA - device pci 19.2 off end # I2C #4 - device pci 1c.0 off end # PCI Express Port 1 - device pci 1c.2 on end # PCI Express Port 3 - device pci 1c.3 on end # PCI Express Port 4 - device pci 1c.4 on end # PCI Express Port 5 - device pci 1e.4 off end # eMMC - device pci 1e.6 off end # SDXC - device pci 1f.0 on + device ref i2c2 off end + device ref i2c3 off end + device ref sata on end + device ref i2c4 off end + device ref pcie_rp1 off end + device ref pcie_rp3 on end + device ref pcie_rp4 on end + device ref pcie_rp5 on end + device ref emmc off end + device ref sdxc off end + device ref lpc_espi on #chip drivers/pc80/tpm # device pnp 0c31.0 on end #end - end # LPC Interface - device pci 1f.6 on end # GbE + end + device ref gbe on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Gerrit-Change-Number: 79325 Gerrit-PatchSet: 6 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: mb/intel/kblrvp: Make use of chipset devicetree
by Felix Singer (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Marvin Evers. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79325?usp=email ) Change subject: mb/intel/kblrvp: Make use of chipset devicetree ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Patchset: PS5: Some of the variant overridetrees have a duplicated configuration to the common devicetree, but they can be cleaned up in a follow-up patch. Otherwise it looks good to me. -- To view, visit https://review.coreboot.org/c/coreboot/+/79325?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1fd5f2a1c8adb5f379d7f3d0b54dca9c3ee6e2b3 Gerrit-Change-Number: 79325 Gerrit-PatchSet: 5 Gerrit-Owner: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 11:32:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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