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[XS] Change in coreboot[master]: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML
by Kevin Yang (Code Review) 04 Jan '24

04 Jan '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79780?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML ...................................................................... mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot chromeos-bootimage Change-Id: I1a5c96cf2b0ee151773bd5a692e7e56780a121ae Signed-off-by: kevin.yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79780/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index f77c501..315f8ce 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4ABAM-ML diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index 36ca69b..64cdb85 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H54G46CYRBX267 0 (0000) +CXDB4ABAM-ML 1 (0001) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 31df0df..4a3926b 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -12,3 +12,4 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AA-MGCR H54G46CYRBX267 +CXDB4ABAM-ML \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/79780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a5c96cf2b0ee151773bd5a692e7e56780a121ae Gerrit-Change-Number: 79780 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML
by Kevin Yang (Code Review) 04 Jan '24

04 Jan '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79779?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML ...................................................................... mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot chromeos-bootimage Change-Id: I90687dded59511464a7a3d3fa8cecb3d3ec33760 Signed-off-by: kevin.yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79779/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index f77c501..315f8ce 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4ABAM-ML diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index 36ca69b..64cdb85 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H54G46CYRBX267 0 (0000) +CXDB4ABAM-ML 1 (0001) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 31df0df..4a3926b 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -12,3 +12,4 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AA-MGCR H54G46CYRBX267 +CXDB4ABAM-ML \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/79779?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I90687dded59511464a7a3d3fa8cecb3d3ec33760 Gerrit-Change-Number: 79779 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: mb/google/cherry: use common configure_display
by Yidi Lin (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79778?usp=email ) Change subject: mb/google/cherry: use common configure_display ...................................................................... mb/google/cherry: use common configure_display TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/common/display.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/ddp.c M src/soc/mediatek/mt8195/include/soc/ddp.h A src/soc/mediatek/mt8195/include/soc/dsi.h 6 files changed, 28 insertions(+), 40 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79778/1 diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index c1593ca..e751956 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -7,13 +7,10 @@ #include <device/device.h> #include <device/mmio.h> #include <ec/google/chromeec/ec.h> -#include <edid.h> -#include <framebuffer_info.h> #include <gpio.h> #include <soc/bl31.h> -#include <soc/ddp.h> +#include <soc/display.h> #include <soc/dpm.h> -#include <soc/dptx.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mtcmos.h> @@ -72,41 +69,16 @@ gpio_output(GPIO_EN_PP3300_DISP_X, 1); } -static bool configure_display(void) +static struct panel_description panel = { + .configure_panel_backlight = configure_panel_backlight, + .power_on = power_on_panel, + .disp_path = DISP_PATH_EDP, + .orientation = LB_FB_ORIENTATION_NORMAL, +}; + +struct panel_description *get_active_panel(void) { - struct edid edid; - struct fb_info *info; - const char *name; - - printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); - - mtcmos_display_power_on(); - mtcmos_protect_display_bus(); - configure_panel_backlight(); - power_on_panel(); - - mtk_ddp_init(); - mdelay(200); - - if (mtk_edp_init(&edid) < 0) { - printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); - return false; - } - name = edid.ascii_string; - if (name[0] == '\0') - name = "unknown name"; - printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, - edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, - edid.mode.refresh); - - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - - mtk_ddp_mode_set(&edid); - info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); - if (info) - fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); - - return true; + return &panel; } static void configure_i2s(void) diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index e3051b4..10c5833 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -16,6 +16,13 @@ return -1; } +__weak int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, const u8 *init_commands) +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + int configure_display(void) { struct edid edid; diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 73ea6fa..56a10bc 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c index 6277fa4..2bd95a2 100644 --- a/src/soc/mediatek/mt8195/ddp.c +++ b/src/soc/mediatek/mt8195/ddp.c @@ -150,7 +150,7 @@ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; diff --git a/src/soc/mediatek/mt8195/include/soc/ddp.h b/src/soc/mediatek/mt8195/include/soc/ddp.h index 3394490..f3fefda 100644 --- a/src/soc/mediatek/mt8195/include/soc/ddp.h +++ b/src/soc/mediatek/mt8195/include/soc/ddp.h @@ -367,6 +367,6 @@ }; void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path); #endif diff --git a/src/soc/mediatek/mt8195/include/soc/dsi.h b/src/soc/mediatek/mt8195/include/soc/dsi.h new file mode 100644 index 0000000..0fd65b9 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dsi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_DSI_H +#define SOC_MEDIATEK_MT8195_DSI_H + +#include <soc/dsi_common.h> + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Gerrit-Change-Number: 79778 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[L] Change in coreboot[main]: mb/google/corsola: use common configure_display
by Yidi Lin (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79777?usp=email ) Change subject: mb/google/corsola: use common configure_display ...................................................................... mb/google/corsola: use common configure_display TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/corsola/boardid.c D src/mainboard/google/corsola/display.c M src/mainboard/google/corsola/mainboard.c A src/mainboard/google/corsola/panel.c R src/mainboard/google/corsola/panel.h M src/mainboard/google/corsola/panel_anx7625.c M src/mainboard/google/corsola/panel_ps8640.c M src/mainboard/google/corsola/panel_starmie.c M src/soc/mediatek/common/display.c M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/include/soc/ddp.h 13 files changed, 129 insertions(+), 168 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79777/1 diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index dce226f..5483167 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -19,8 +19,8 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c -ramstage-y += display.c ramstage-y += mainboard.c +ramstage-y += panel.c ramstage-y += panel_anx7625.c ramstage-y += panel_ps8640.c ramstage-y += regulator.c diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c index 59c9f5c..443c3d1 100644 --- a/src/mainboard/google/corsola/boardid.c +++ b/src/mainboard/google/corsola/boardid.c @@ -6,7 +6,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/auxadc.h> -#include "display.h" +#include "panel.h" /* board_id is provided by ec/google/chromeec/ec_boardid.c */ diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c deleted file mode 100644 index c7a6578..0000000 --- a/src/mainboard/google/corsola/display.c +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boardid.h> -#include <cbfs.h> -#include <console/console.h> -#include <device/i2c_simple.h> -#include <edid.h> -#include <gpio.h> -#include <soc/ddp.h> -#include <soc/dsi.h> -#include <soc/gpio_common.h> -#include <soc/mtcmos.h> - -#include "display.h" -#include "gpio.h" - -void aw37503_init(unsigned int bus) -{ - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x14, 0x1F, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x01, 0x14, 0x1F, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x4C, 0xFF, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x03, 0x43, 0xFF, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x00, 0xFF, 0); -} - -bool is_pmic_aw37503(unsigned int bus) -{ - u8 vendor_id; - return (!i2c_read_field(bus, PMIC_AW37503_SLAVE, - 0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01); -} - -static void backlight_control(void) -{ - /* Disable backlight before turning on bridge */ - gpio_output(GPIO_AP_EDP_BKLTEN, 0); - gpio_output(GPIO_BL_PWM_1V8, 0); - /* For staryu variants, GPIO_EN_PP3300_DISP_X is controlled in - mipi_panel_power_on() */ - if (!CONFIG(BOARD_GOOGLE_STARYU_COMMON)) - gpio_output(GPIO_EN_PP3300_DISP_X, 1); -} - -struct panel_description *get_panel_from_cbfs(struct panel_description *desc) -{ - char cbfs_name[64]; - static union { - u8 raw[4 * 1024]; - struct panel_serializable_data s; - } buffer; - - if (!desc->name) - return NULL; - - snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) - desc->s = &buffer.s; - else - printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); - - return desc->s ? desc : NULL; -} - -static struct panel_description *get_active_panel(void) -{ - /* Board-specific exceptions */ - if (CONFIG(BOARD_GOOGLE_STEELIX) && board_id() < 2) /* Early builds use PS8640 */ - return get_ps8640_description(); - - if (CONFIG(DRIVER_ANALOGIX_ANX7625)) - return get_anx7625_description(); - - if (CONFIG(DRIVER_PARADE_PS8640)) - return get_ps8640_description(); - - /* MIPI panels */ - return get_panel_description(); -} - -int configure_display(void) -{ - /* Set up backlight control pins as output pin and power-off by default */ - backlight_control(); - - const struct panel_description *panel = get_active_panel(); - - if (!panel) - return -1; - - printk(BIOS_INFO, "%s: Starting display init\n", __func__); - - if (panel->power_on) - panel->power_on(); - - struct edid edid = panel->s->edid; - const char *name = edid.ascii_string; - if (name[0] == '\0') - name = "unknown name"; - printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, - edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, - edid.mode.refresh); - - mtcmos_display_power_on(); - mtcmos_protect_display_bus(); - - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_init(); - u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM | - MIPI_DSI_MODE_EOT_PACKET); - - if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, - panel->s->init) < 0) { - printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); - return -1; - } - - if (panel->post_power_on && panel->post_power_on(BRIDGE_I2C, &edid) < 0) { - printk(BIOS_ERR, "%s: Failed to post power on bridge\n", __func__); - return -1; - } - - mtk_ddp_mode_set(&edid); - struct fb_info *info = fb_new_framebuffer_info_from_edid(&edid, - (uintptr_t)0); - if (info) - fb_set_orientation(info, panel->orientation); - - return 0; -} diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 37f3a70..5c2abc8 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -6,13 +6,14 @@ #include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> +#include <soc/display.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/spm.h> #include <soc/usb.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void configure_alc1019(void) { diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c new file mode 100644 index 0000000..71f154d --- /dev/null +++ b/src/mainboard/google/corsola/panel.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio_common.h> +#include <soc/mtcmos.h> + +#include "gpio.h" +#include "panel.h" + +void aw37503_init(unsigned int bus) +{ + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x14, 0x1F, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x01, 0x14, 0x1F, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x4C, 0xFF, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x03, 0x43, 0xFF, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x00, 0xFF, 0); +} + +bool is_pmic_aw37503(unsigned int bus) +{ + u8 vendor_id; + return (!i2c_read_field(bus, PMIC_AW37503_SLAVE, + 0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01); +} + +void backlight_control(void) +{ + /* Set up backlight control pins as output pin and power-off by default */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); +} + +struct panel_description *get_panel_from_cbfs(struct panel_description *desc) +{ + char cbfs_name[64]; + static union { + u8 raw[4 * 1024]; + struct panel_serializable_data s; + } buffer; + + if (!desc->name) + return NULL; + + snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); + if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) + desc->s = &buffer.s; + else + printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); + + return desc->s ? desc : NULL; +} + +struct panel_description *get_active_panel(void) +{ + /* Board-specific exceptions */ + if (CONFIG(BOARD_GOOGLE_STEELIX) && board_id() < 2) /* Early builds use PS8640 */ + return get_ps8640_description(); + + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + return get_anx7625_description(); + + if (CONFIG(DRIVER_PARADE_PS8640)) + return get_ps8640_description(); + + /* MIPI panels */ + return get_panel_description(); +} diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/panel.h similarity index 70% rename from src/mainboard/google/corsola/display.h rename to src/mainboard/google/corsola/panel.h index 7631bb9..ba2097d 100644 --- a/src/mainboard/google/corsola/display.h +++ b/src/mainboard/google/corsola/panel.h @@ -3,26 +3,17 @@ #ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ #define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ -#include <edid.h> -#include <mipi/panel.h> +#include <soc/display.h> #include <soc/i2c.h> #define BRIDGE_I2C I2C0 #define PMIC_AW37503_SLAVE 0x3E #define PMIC_I2C_BUS I2C6 -struct panel_description { - void (*power_on)(void); /* Callback to turn on panel */ - int (*post_power_on)(u8 i2c_bus, struct edid *edid); - const char *name; /* Panel name in CBFS */ - struct panel_serializable_data *s; - enum lb_fb_orientation orientation; -}; - void aw37503_init(unsigned int bus); bool is_pmic_aw37503(unsigned int bus); -int configure_display(void); uint32_t panel_id(void); +void backlight_control(void); /* Return the mipi panel description from given panel id */ struct panel_description *get_panel_description(void); diff --git a/src/mainboard/google/corsola/panel_anx7625.c b/src/mainboard/google/corsola/panel_anx7625.c index 7b50e47..2ff0ed2 100644 --- a/src/mainboard/google/corsola/panel_anx7625.c +++ b/src/mainboard/google/corsola/panel_anx7625.c @@ -7,8 +7,8 @@ #include <gpio.h> #include <soc/i2c.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void bridge_anx7625_power_on(void) { @@ -23,39 +23,45 @@ gpio_output(GPIO_EDPBRDG_RST_L, 1); } -static int bridge_anx7625_get_edid(u8 i2c_bus, struct edid *edid) +static int bridge_anx7625_get_edid(const struct panel_description *panel) { - if (anx7625_init(i2c_bus) < 0) { + if (anx7625_init(BRIDGE_I2C) < 0) { printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); return -1; } - if (anx7625_dp_get_edid(i2c_bus, edid) < 0) { + if (anx7625_dp_get_edid(BRIDGE_I2C, &panel->s->edid) < 0) { printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); return -1; } return 0; } -static int bridge_anx7625_post_power_on(u8 i2c_bus, struct edid *edid) +static int bridge_anx7625_post_power_on(const struct panel_description *panel) { - return anx7625_dp_start(i2c_bus, edid); + return anx7625_dp_start(BRIDGE_I2C, &panel->s->edid); +} + +static void panel_power_on(void) +{ + /* Turn on the panel */ + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + bridge_anx7625_power_on(); } static struct panel_serializable_data anx7625_data; static struct panel_description anx7625_bridge = { .s = &anx7625_data, + .configure_panel_backlight = backlight_control, + .power_on = panel_power_on, + .get_edid = bridge_anx7625_get_edid, .post_power_on = bridge_anx7625_post_power_on, + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_NORMAL, }; struct panel_description *get_anx7625_description(void) { mtk_i2c_bus_init(BRIDGE_I2C, I2C_SPEED_FAST); - bridge_anx7625_power_on(); - if (bridge_anx7625_get_edid(BRIDGE_I2C, &anx7625_bridge.s->edid) < 0) { - printk(BIOS_ERR, "Can't get panel's edid\n"); - return NULL; - } return &anx7625_bridge; } diff --git a/src/mainboard/google/corsola/panel_ps8640.c b/src/mainboard/google/corsola/panel_ps8640.c index bb1e4eb..6a87c73 100644 --- a/src/mainboard/google/corsola/panel_ps8640.c +++ b/src/mainboard/google/corsola/panel_ps8640.c @@ -8,8 +8,8 @@ #include <soc/i2c.h> #include <soc/regulator.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void bridge_ps8640_power_on(void) { @@ -45,15 +45,22 @@ gpio_output(GPIO_EDPBRDG_RST_L, 1); } -static int bridge_ps8640_get_edid(u8 i2c_bus, struct edid *edid) +static void panel_power_on(void) +{ + /* Turn on the panel */ + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + bridge_ps8640_power_on(); +} + +static int bridge_ps8640_get_edid(const struct panel_description *panel) { const u8 chip = 0x8; - if (ps8640_init(i2c_bus, chip) < 0) { + if (ps8640_init(BRIDGE_I2C, chip) < 0) { printk(BIOS_ERR, "%s: Can't init PS8640 bridge\n", __func__); return -1; } - if (ps8640_get_edid(i2c_bus, chip, edid) < 0) { + if (ps8640_get_edid(BRIDGE_I2C, chip, &panel->s->edid) < 0) { printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); return -1; } @@ -64,16 +71,15 @@ static struct panel_description ps8640_bridge = { .s = &ps8640_data, + .configure_panel_backlight = backlight_control, + .power_on = panel_power_on, + .get_edid = bridge_ps8640_get_edid, + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_NORMAL, }; struct panel_description *get_ps8640_description(void) { mtk_i2c_bus_init(BRIDGE_I2C, I2C_SPEED_FAST); - bridge_ps8640_power_on(); - if (bridge_ps8640_get_edid(BRIDGE_I2C, &ps8640_bridge.s->edid) < 0) { - printk(BIOS_ERR, "Can't get panel's edid\n"); - return NULL; - } return &ps8640_bridge; } diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index 55e9dbf..28d3e86 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -6,8 +6,8 @@ #include <soc/regulator.h> #include <soc/tps65132s.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void mipi_panel_power_on(void) { @@ -51,20 +51,26 @@ /* K&D panel vendor and ILI9882T chip, K&D and STA panel are identical except manufacturer_name. */ [6] = { + .configure_panel_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_ILI9882T", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, /* STA panel vendor and ILI9882T chip */ [9] = { + .configure_panel_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_ILI9882T", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, /* STA panel vendor and HIMAX83102_J02 chip */ [10] = { + .configure_panel_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_HIMAX83102_J02", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, }; diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index 79651d5..e3051b4 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -10,6 +10,12 @@ #include <soc/dsi.h> #include <soc/mtcmos.h> +__weak int mtk_edp_init(struct edid *edid) +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + int configure_display(void) { struct edid edid; diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 8fe923f..3a3cc07 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c @@ -53,6 +54,7 @@ ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include BL31_MAKEARGS += PLAT=mt8186 diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c index 6706ed7..5a5f544 100644 --- a/src/soc/mediatek/mt8186/ddp.c +++ b/src/soc/mediatek/mt8186/ddp.c @@ -141,7 +141,7 @@ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h index e66563d..76ca6e1 100644 --- a/src/soc/mediatek/mt8186/include/soc/ddp.h +++ b/src/soc/mediatek/mt8186/include/soc/ddp.h @@ -255,6 +255,6 @@ static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Gerrit-Change-Number: 79777 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/mediatek: a common implmentation to configure display
by Yidi Lin (Code Review) 04 Jan '24

04 Jan '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79776?usp=email ) Change subject: soc/mediatek: a common implmentation to configure display ...................................................................... soc/mediatek: a common implmentation to configure display The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to soc/common/display.c and refacts `struct panel_description` to generalize the sequences of configure_display(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/geralt/Makefile.inc M src/mainboard/google/geralt/mainboard.c M src/mainboard/google/geralt/panel.h M src/mainboard/google/geralt/panel_geralt.c R src/soc/mediatek/common/display.c M src/soc/mediatek/common/include/soc/ddp_common.h A src/soc/mediatek/common/include/soc/display.h M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/ddp.h 9 files changed, 50 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79776/1 diff --git a/src/mainboard/google/geralt/Makefile.inc b/src/mainboard/google/geralt/Makefile.inc index 2b1f313..e954309 100644 --- a/src/mainboard/google/geralt/Makefile.inc +++ b/src/mainboard/google/geralt/Makefile.inc @@ -20,7 +20,6 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c -ramstage-y += display.c ramstage-y += mainboard.c ramstage-y += panel.c ramstage-y += regulator.c diff --git a/src/mainboard/google/geralt/mainboard.c b/src/mainboard/google/geralt/mainboard.c index 6bb8380..a24070d 100644 --- a/src/mainboard/google/geralt/mainboard.c +++ b/src/mainboard/google/geralt/mainboard.c @@ -3,13 +3,13 @@ #include <bootmode.h> #include <device/device.h> #include <soc/bl31.h> +#include <soc/display.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mt6359p.h> #include <soc/mtcmos.h> #include <soc/usb.h> -#include "display.h" #include "gpio.h" #define AFE_SE_SECURE_CON (AUDIO_BASE + 0x17a8) diff --git a/src/mainboard/google/geralt/panel.h b/src/mainboard/google/geralt/panel.h index 71cecdf..3d0fafd 100644 --- a/src/mainboard/google/geralt/panel.h +++ b/src/mainboard/google/geralt/panel.h @@ -3,23 +3,11 @@ #ifndef __MAINBOARD_GOOGLE_GERALT_PANEL_H__ #define __MAINBOARD_GOOGLE_GERALT_PANEL_H__ -#include <boot/coreboot_tables.h> -#include <mipi/panel.h> -#include <soc/ddp.h> - -struct panel_description { - const char *name; - struct panel_serializable_data *s; - void (*power_on)(void); - void (*configure_panel_backlight)(void); - enum disp_path_sel disp_path; - bool pwm_ctrl_gpio; -}; +#include <soc/display.h> void configure_mipi_pwm_backlight(void); void fill_lp_backlight_gpios(struct lb_gpios *gpios); uint32_t panel_id(void); struct panel_description *get_panel_description(uint32_t panel_id); -struct panel_description *get_active_panel(void); #endif diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 2ca95be..9453981 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -53,6 +53,7 @@ .name = "BOE_TV110C9M_LL0", .power_on = power_on_mipi_boe_tv110c9m_ll0, .configure_panel_backlight = configure_mipi_pwm_backlight, + .orientation = LB_FB_ORIENTATION_BOTTOM_UP, .disp_path = DISP_PATH_MIPI, .pwm_ctrl_gpio = true, }, diff --git a/src/mainboard/google/geralt/display.c b/src/soc/mediatek/common/display.c similarity index 78% rename from src/mainboard/google/geralt/display.c rename to src/soc/mediatek/common/display.c index 68a0a22..79651d5 100644 --- a/src/mainboard/google/geralt/display.c +++ b/src/soc/mediatek/common/display.c @@ -4,23 +4,19 @@ #include <delay.h> #include <edid.h> #include <framebuffer_info.h> -#include <gpio.h> #include <soc/ddp.h> +#include <soc/display.h> #include <soc/dptx.h> #include <soc/dsi.h> -#include <soc/gpio_common.h> #include <soc/mtcmos.h> -#include "display.h" -#include "gpio.h" -#include "panel.h" - int configure_display(void) { struct edid edid; struct fb_info *info; const char *name; struct panel_description *panel = get_active_panel(); + if (!panel) return -1; @@ -29,8 +25,10 @@ mtcmos_display_power_on(); mtcmos_protect_display_bus(); - panel->configure_panel_backlight(); - panel->power_on(); + if (panel->configure_panel_backlight) + panel->configure_panel_backlight(); + if (panel->power_on) + panel->power_on(); mtk_ddp_init(); @@ -40,8 +38,10 @@ printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); return -1; } - } else { + if (panel->get_edid && panel->get_edid(panel) < 0) + return -1; + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | MIPI_DSI_MODE_LPM | @@ -54,6 +54,11 @@ printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); return -1; } + + if (panel->post_power_on && panel->post_power_on(panel) < 0) { + printk(BIOS_ERR, "%s: Failed to post power on bridge\n", __func__); + return -1; + } } name = edid.ascii_string; @@ -68,7 +73,7 @@ mtk_ddp_mode_set(&edid, panel->disp_path); info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); if (info) - fb_set_orientation(info, LB_FB_ORIENTATION_BOTTOM_UP); + fb_set_orientation(info, panel->orientation); return 0; } diff --git a/src/soc/mediatek/common/include/soc/ddp_common.h b/src/soc/mediatek/common/include/soc/ddp_common.h index 43893f7..a7edc05 100644 --- a/src/soc/mediatek/common/include/soc/ddp_common.h +++ b/src/soc/mediatek/common/include/soc/ddp_common.h @@ -139,4 +139,10 @@ void color_start(u32 width, u32 height); void ovl_layer_config(u32 fmt, u32 bpp, u32 width, u32 height); +enum disp_path_sel { + DISP_PATH_NONE = 0, + DISP_PATH_EDP, + DISP_PATH_MIPI, +}; + #endif diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h new file mode 100644 index 0000000..7de577a --- /dev/null +++ b/src/soc/mediatek/common/include/soc/display.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DISPLAY_H__ +#define __SOC_MEDIATEK_COMMON_DISPLAY_H__ + +#include <commonlib/coreboot_tables.h> +#include <mipi/panel.h> +#include <soc/ddp.h> + +struct panel_description { + const char *name; + struct panel_serializable_data *s; + void (*configure_panel_backlight)(void); + void (*power_on)(void); + int (*get_edid)(const struct panel_description *panel); + int (*post_power_on)(const struct panel_description *panel); + enum lb_fb_orientation orientation; + enum disp_path_sel disp_path; + bool pwm_ctrl_gpio; +}; + +int configure_display(void); +struct panel_description *get_active_panel(void); + +#endif diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 6a643b0..4731fab 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h index da14a2c..1f167db 100644 --- a/src/soc/mediatek/mt8188/include/soc/ddp.h +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -282,12 +282,6 @@ SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, }; -enum disp_path_sel { - DISP_PATH_NONE = 0, - DISP_PATH_EDP, - DISP_PATH_MIPI, -}; - void mtk_ddp_init(void); void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel); -- To view, visit https://review.coreboot.org/c/coreboot/+/79776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Gerrit-Change-Number: 79776 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/intel/mtlrvp: define a new config for Chrome EC
by Subrata Banik (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Eric Lai, Felix Singer, Kapil Porwal, Krishna P Bhat D, Paul Menzel. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79211?usp=email ) Change subject: mb/intel/mtlrvp: define a new config for Chrome EC ...................................................................... Patch Set 9: (6 comments) File src/mainboard/intel/mtlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/79211/comment/0f6594a0_dbf835b3 : PS9, Line 29: select BOARD_EXT_EC_SPECIFIC_OPTIONS select BOARD_MTLRVP_EC_GOOGLE_CHROMEEC_COMMON https://review.coreboot.org/c/coreboot/+/79211/comment/d46394da_5c804fda : PS9, Line 33: select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON select BOARD_MTLRVP_EC_GOOGLE_CHROMEEC_COMMON https://review.coreboot.org/c/coreboot/+/79211/comment/d901e170_a6dad16f : PS9, Line 38: select SOC_INTEL_METEORLAKE_PRE_PRODUCTION_SILICON select BOARD_MTLRVP_EC_GOOGLE_CHROMEEC_COMMON https://review.coreboot.org/c/coreboot/+/79211/comment/ab1cdddb_2485260c : PS9, Line 47: BOARD_MTLRVP_EC_GOOGLE_CHROMEEC_COMMON why not below platform selects this config directly BOARD_INTEL_MTLRVP_P_EXT_EC BOARD_INTEL_MTLRVP4ES_P_EXT_EC BOARD_INTEL_MTLRVP_P_MCHP https://review.coreboot.org/c/coreboot/+/79211/comment/fa480619_22dbaaa4 : PS9, Line 114: MTL_CHROME_EC_SHARED_SPI please move this change into a specific CL where you are adding the support for shared SPI https://review.coreboot.org/c/coreboot/+/79211/comment/646d26b6_54f4bbf8 : PS9, Line 121: select BOARD_MTLRVP_EC_GOOGLE_CHROMEEC_COMMON you don't need this selection. follow my comment above -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 9 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 05:06:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: add fw splash screen timestamp
by Subrata Banik (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Andrey Petrov, Paz Zcharya, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79789?usp=email ) Change subject: drivers/intel/fsp2_0: add fw splash screen timestamp ...................................................................... Patch Set 1: (1 comment) File src/drivers/intel/fsp2_0/graphics.c: https://review.coreboot.org/c/coreboot/+/79789/comment/1b358ffc_9e6d6337 : PS1, Line 119: timestamp_add_now(TS_SPLASH_SCREEN_VISIBLE); https://github.com/coreboot/coreboot/blob/3329e8893eaef8637b3ebdcf3b46e8adc… function is a FSP-S API which is responsible to render the FW splash screen during the execution of FSP. fsp_report_framebuffer_info() is just one API which we parse post FSP-S to know if GFX has been init or not. adding timestamp won't mean anything here. -- To view, visit https://review.coreboot.org/c/coreboot/+/79789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie2a0a0591ceeee08a147fc54ad3aee4f602933c9 Gerrit-Change-Number: 79789 Gerrit-PatchSet: 1 Gerrit-Owner: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 05:03:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: util/ifdtool: Add support for disabling GPR0
by Subrata Banik (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Krishna P Bhat D, Reka Norman, Stefan Reinauer. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79788?usp=email ) Change subject: util/ifdtool: Add support for disabling GPR0 ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79788?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iee13ce0b702b3c7a443501cb4fc282580869d03a Gerrit-Change-Number: 79788 Gerrit-PatchSet: 1 Gerrit-Owner: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Reka Norman <rekanorman(a)google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 05:00:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/intel/mtlrvp: define a new config for Chrome EC
by Vijay P Hiremath (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Balaji Manigandan, Deepti Deshatty, Eric Lai, Felix Singer, Kapil Porwal, Krishna P Bhat D, Paul Menzel, Subrata Banik. Vijay P Hiremath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79211?usp=email ) Change subject: mb/intel/mtlrvp: define a new config for Chrome EC ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 9 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 04:55:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/intel/mtlrvp: define a new config for Chrome EC
by Deepti Deshatty (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Balaji Manigandan, Eric Lai, Felix Singer, Kapil Porwal, Krishna P Bhat D, Paul Menzel, Subrata Banik, Vijay P Hiremath. Deepti Deshatty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79211?usp=email ) Change subject: mb/intel/mtlrvp: define a new config for Chrome EC ...................................................................... Patch Set 9: (1 comment) File src/mainboard/intel/mtlrvp/Kconfig: https://review.coreboot.org/c/coreboot/+/79211/comment/e675e4ed_1feafd61 : PS7, Line 47: GOOGLE > Prefix that with BOARD_MTLRVP_ Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79211?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0b85cc48d5cefadb52edbb27bf6cf370b27c395f Gerrit-Change-Number: 79211 Gerrit-PatchSet: 9 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 03:35:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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