coreboot-gerrit January 2024

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Dtrain Hsu (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Eric Lai, Kenny Pan, Nick Vaccaro, Paul Menzel, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Dtrain Hsu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Do you need modify Makefile.inc for ROM stage? -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 09:40:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: util/lint: Remove the extra `\` in lint-stable-003-whitespace
by Ruihai Zhou (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79782?usp=email to look at the new patch set (#2). Change subject: util/lint: Remove the extra `\` in lint-stable-003-whitespace ...................................................................... util/lint: Remove the extra `\` in lint-stable-003-whitespace A following error occurred when I commit, it seems that the extra `\` is unnecessary. File Binary file src/mainboard/google/guybrush/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/skyrim/data.apcb matches has lines ending with whitespace. File Binary file src/mainboard/google/zork/data.apcb matches has lines ending with whitespace. test failed Signed-off-by: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b --- M util/lint/lint-stable-003-whitespace 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/79782/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Gerrit-Change-Number: 79782 Gerrit-PatchSet: 2 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: util/lint: Remove the extra `\` in lint-stable-003-whitespace
by Ruihai Zhou (Code Review) 04 Jan '24

04 Jan '24

Ruihai Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79782?usp=email ) Change subject: util/lint: Remove the extra `\` in lint-stable-003-whitespace ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/79782?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I315a37ccc3c6ebb67f7a250402549761c699dd1b Gerrit-Change-Number: 79782 Gerrit-PatchSet: 1 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 09:24:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
by Felix Singer (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Angel Pons, Felix Held, Jonathon Hall. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77670?usp=email ) Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77670/comment/539d8841_0c16f776 : PS5, Line 9: e633d370 Add "commit" before the hash so that Gerrit makes it a link. -- To view, visit https://review.coreboot.org/c/coreboot/+/77670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61 Gerrit-Change-Number: 77670 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Jan 2024 09:14:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Refine power-down mode logic
by Angel Pons (Code Review) 04 Jan '24

04 Jan '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47746 ) Change subject: nb/intel/sandybridge: Refine power-down mode logic ...................................................................... nb/intel/sandybridge: Refine power-down mode logic When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 41 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/47746/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3d..9cd522f 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -99,6 +99,15 @@ hex default 0x0 +config RAMINIT_ALWAYS_ALLOW_DLL_OFF + bool "Also enable memory DLL-off mode on desktops and servers" + default n + help + If enabled, allow enabling DLL-off mode for platforms other than + mobile. Saves power at the expense of higher exit latencies. Has + no effect on mobile platforms, where DLL-off is always allowed. + Power down is disabled for stability when running at high clocks. + config RAMINIT_ENABLE_ECC bool "Enable ECC if supported" default y diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b06734c..d533ca8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -688,11 +688,29 @@ iosav_run_once(channel); } +/* Obtain optimal power down mode for current configuration */ +static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +{ + if (ctrl->tXP > 8) + return PDM_NONE; + + if (ctrl->tXPDLL > 32) + return PDM_PPD; + + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) + return PDM_DLL_OFF; + + return PDM_APD_PPD; +} + static u32 make_mr0(ramctr_timing *ctrl, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; + + const enum pdwm_mode power_down = get_power_down_mode(ctrl); + + const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { @@ -712,8 +730,8 @@ mr0reg |= (mch_cas & 0xe) << 3; mr0reg |= mch_wr << 9; - /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg |= !is_mobile << 12; + /* Precharge PD - Use slow exit when DLL-off is used - mostly power-saving feature */ + mr0reg |= !slow_exit << 12; return mr0reg; } @@ -2830,8 +2848,6 @@ /* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { - const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; - int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; @@ -2848,12 +2864,8 @@ MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; } - if (is_mobile) - /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; - else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; + /* 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; FOR_ALL_CHANNELS MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 050aa70..80d3074 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -273,6 +273,15 @@ */ #define MRC_CACHE_VERSION 5 +enum pdwm_mode { + PDM_NONE = 0, + PDM_APD = 1, + PDM_PPD = 2, + PDM_APD_PPD = 3, + PDM_DLL_OFF = 6, + PDM_APD_DLL_OFF = 7, +}; + typedef struct odtmap_st { u16 rttwr; u16 rttnom; -- To view, visit https://review.coreboot.org/c/coreboot/+/47746 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Gerrit-Change-Number: 47746 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/mediatek: a common implmentation to configure display
by Paul Menzel (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79776?usp=email ) Change subject: soc/mediatek: a common implmentation to configure display ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79776/comment/08574524_d55e5621 : PS1, Line 7: a common implmentation to configure display Please make it a statement by adding a verb (in imperative mood). Maybe: > Implement common display configuration or > Add common implementation to configure display -- To view, visit https://review.coreboot.org/c/coreboot/+/79776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Gerrit-Change-Number: 79776 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 07:55:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
by Paul Menzel (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Angel Pons, Felix Held, Jonathon Hall. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77670?usp=email ) Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77670/comment/b289dd5b_3a2c60f5 : PS5, Line 9: e633d370 Please add the summary in () after the hash. -- To view, visit https://review.coreboot.org/c/coreboot/+/77670?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61 Gerrit-Change-Number: 77670 Gerrit-PatchSet: 5 Gerrit-Owner: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 04 Jan 2024 07:50:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/prodrive/hermes: Change UART from hidden to on
by Patrick Rudolph (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Christian Walter. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79786?usp=email ) Change subject: mb/prodrive/hermes: Change UART from hidden to on ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: Does uart_fill_ssdt() still generate valid ACPI code for UART2? I don't see how code in src/soc/intel/common/block/uart/uart.c actually works using a "generic device". The code was originally written for an UART PCI device... -- To view, visit https://review.coreboot.org/c/coreboot/+/79786?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If24e1bf920c0b3edaefb4e20af66e33f4ddc1f3f Gerrit-Change-Number: 79786 Gerrit-PatchSet: 2 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 07:11:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML
by Kevin Yang (Code Review) 04 Jan '24

04 Jan '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79781?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML ...................................................................... mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot chromeos-bootimage Change-Id: Ic5b12baeedef8a247340aa6a9e88c82de38c2247 Signed-off-by: kevin.yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/79781/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index f77c501..315f8ce 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4ABAM-ML diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index 36ca69b..64cdb85 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H54G46CYRBX267 0 (0000) +CXDB4ABAM-ML 1 (0001) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 31df0df..4a3926b 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -12,3 +12,4 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AA-MGCR H54G46CYRBX267 +CXDB4ABAM-ML \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/79781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5b12baeedef8a247340aa6a9e88c82de38c2247 Gerrit-Change-Number: 79781 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML
by Kevin Yang (Code Review) 04 Jan '24

04 Jan '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79780?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML ...................................................................... mb/google/dedede/var/beadrix: Generate new SPD ID for CXDB4ABAM-ML Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=beadrix emerge-dedede coreboot chromeos-bootimage Change-Id: I1a5c96cf2b0ee151773bd5a692e7e56780a121ae Signed-off-by: kevin.yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79780/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index f77c501..315f8ce 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4ABAM-ML diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index 36ca69b..64cdb85 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H54G46CYRBX267 0 (0000) +CXDB4ABAM-ML 1 (0001) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 31df0df..4a3926b 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -12,3 +12,4 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AA-MGCR H54G46CYRBX267 +CXDB4ABAM-ML \ No newline at end of file -- To view, visit https://review.coreboot.org/c/coreboot/+/79780?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a5c96cf2b0ee151773bd5a692e7e56780a121ae Gerrit-Change-Number: 79780 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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