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Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77670/comment/1fe24282_de4f3d63 :
PS5, Line 9: e633d370
> Add "commit" before the hash so that Gerrit makes it a link.
Done
https://review.coreboot.org/c/coreboot/+/77670/comment/b598c611_35a92e94 :
PS5, Line 9: e633d370
> Please add the summary in () after the hash.
Done
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Hello Angel Pons, Felix Held, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
......................................................................
mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
Since commit e633d370 (soc/intel/cometlake: Enable early caching of
RAMTOP region), cmos.layout for Cannon Lake boards must have a ramtop
entry, add it.
Change-Id: I2bf71f2dd79f2e1e2e13f62a3e08103336bbad61
Signed-off-by: Jonathon Hall <jonathon.hall(a)puri.sm>
---
M src/mainboard/purism/librem_cnl/variants/librem_mini/cmos.layout
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/77670/6
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Hello Patrick Rudolph, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/prodrive/hermes: Change UART from hidden to on
......................................................................
mb/prodrive/hermes: Change UART from hidden to on
If the generic device is hidden coreboot errors with '[EMERG]
GENERIC: 0.0 missing resource: 10'. Enabling it solves the issue.
Change-Id: If24e1bf920c0b3edaefb4e20af66e33f4ddc1f3f
Signed-off-by: Christian Walter <christian.walter(a)9elements.com>
---
M src/mainboard/prodrive/hermes/devicetree.cb
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79786/3
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Change subject: drivers/intel/fsp2_0: add fw splash screen timestamp
......................................................................
Abandoned
fsp_report_framebuffer_info() is just one API which we parse post FSP-S to know if GFX has been init or not. adding timestamp won't mean anything here.
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Change subject: device/pciexp_device.c: Fix setting Max Payload Size
......................................................................
Patch Set 11:
(1 comment)
File src/device/pciexp_device.c:
https://review.coreboot.org/c/coreboot/+/77338/comment/01fb5d9b_c01bac3a :
PS10, Line 645: pciexp_limit_max_payload_ctl(dev->bus->dev, pciexp_configured_max_payload(dev), cap);
> Now traversing the topology in a loop and updating the Max Payload Size up to the root port each tim […]
@Krystian, since this is your comment, could you please take another look and verify whether your concern has been addressed?
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Change subject: mb/intel/mtlrvp: define a new config for Chrome EC
......................................................................
Patch Set 10: Code-Review+1
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Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS2:
> Add ROM stage in Makefile.inc.
good catch!
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Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
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Patch Set 3: Code-Review+2
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Change subject: mb/intel/mtlrvp: enable external shared SPI config
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/intel/mtlrvp/Kconfig:
https://review.coreboot.org/c/coreboot/+/79824/comment/88c250b4_54f12408 :
PS1, Line 112: help
introduce MTL_CHROME_EC_SHARED_SPI part of this CL ?
https://review.coreboot.org/c/coreboot/+/79211/10/src/mainboard/intel/mtlrv…
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