coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3043 discussions

[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Matt DeVillier (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Dtrain Hsu, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 3 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 16:04:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79566?usp=email ) Change subject: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/79566/comment/e5170d6a_6a9d5b1f : PS3, Line 322: non-fixed APMC SMI command port > on intel the io port is hard-wired while on amd the io port can be configured would it make things clearer when replacing 'non-fixed' with 'configurable'? -- To view, visit https://review.coreboot.org/c/coreboot/+/79566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Gerrit-Change-Number: 79566 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 15:35:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: vboot: Add firmware PCR support
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79437?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: vboot: Add firmware PCR support ...................................................................... vboot: Add firmware PCR support To verify the boot chain, we will need to extend the PCR with the firmware version. And the server will be able to attest the firmware version of devices. The "firmware version" here is the RW firmware anti-rollback version, determined by the ChromeOS's signing infra, and will be verified in vb2api_fw_phase3, by comparing it with the version stored in the TPM. This version will be increased when there is critical vulnerability in the RW firmware. According to [1], PCRs 8-15 usage is defined by Static OS. Therefore PCR_FW_VER is chosen to be within that range. Ideally the existing PCR_BOOT_MODE and PCR_HWID should also be allocated in the same range, but unfortunately it's too late to fix them. Because PCRs 11 and 13 have been used for other purposes in ChromeOS, here PCR_FW_VER is set to 10. [1] https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClient_PFP_r1p05… BUG=b:248610274 TEST=Boot the device, and check the PCR 10 BRANCH=none Signed-off-by: Yi Chou <yich(a)google.com> Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79437 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/security/tpm/Kconfig M src/security/vboot/tpm_common.c M src/security/vboot/vboot_logic.c 3 files changed, 13 insertions(+), 2 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index e129f51..5eb5837 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -165,6 +165,10 @@ int default 2 +config PCR_FW_VER + int + default 10 + # PCR for measuring data which changes during runtime # e.g. CMOS, NVRAM... config PCR_RUNTIME_DATA diff --git a/src/security/vboot/tpm_common.c b/src/security/vboot/tpm_common.c index c330cc2..997c4e9 100644 --- a/src/security/vboot/tpm_common.c +++ b/src/security/vboot/tpm_common.c @@ -8,7 +8,7 @@ #define TPM_PCR_BOOT_MODE "VBOOT: boot mode" #define TPM_PCR_GBB_HWID_NAME "VBOOT: GBB HWID" -#define TPM_PCR_MINIMUM_DIGEST_SIZE 20 +#define TPM_PCR_FIRMWARE_VERSION "VBOOT: firmware ver" tpm_result_t vboot_setup_tpm(struct vb2_context *ctx) { @@ -54,6 +54,10 @@ case HWID_DIGEST_PCR: return tpm_extend_pcr(pcr, algo, buffer, vb2_digest_size(algo), TPM_PCR_GBB_HWID_NAME); + /* firmware version */ + case FIRMWARE_VERSION_PCR: + return tpm_extend_pcr(pcr, algo, buffer, vb2_digest_size(algo), + TPM_PCR_FIRMWARE_VERSION); default: return TPM_CB_FAIL; } diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index 93a188c..f98b083 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -190,7 +190,10 @@ rc = vboot_extend_pcr(ctx, CONFIG_PCR_BOOT_MODE, BOOT_MODE_PCR); if (rc) return rc; - return vboot_extend_pcr(ctx, CONFIG_PCR_HWID, HWID_DIGEST_PCR); + rc = vboot_extend_pcr(ctx, CONFIG_PCR_HWID, HWID_DIGEST_PCR); + if (rc) + return rc; + return vboot_extend_pcr(ctx, CONFIG_PCR_FW_VER, FIRMWARE_VERSION_PCR); } #define EC_EFS_BOOT_MODE_VERIFIED_RW 0x00 -- To view, visit https://review.coreboot.org/c/coreboot/+/79437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I601ad31e8c893a8e9ae1a9cdd27193edce10ec61 Gerrit-Change-Number: 79437 Gerrit-PatchSet: 8 Gerrit-Owner: Yi Chou <yich(a)google.com> Gerrit-Reviewer: Andrey Pronin <apronin(a)chromium.org> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Pronin <apronin(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: Documentation: Update internal URL's
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79785?usp=email ) Change subject: Documentation: Update internal URL's ...................................................................... Documentation: Update internal URL's Update URL's to point to head rather than the deprecated refs/heads/master. Change-Id: I16f0c087762ff049115b67de3ac0b881aa4e4b40 Signed-off-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79785 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M Documentation/mainboard/ocp/deltalake.md M README.md 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index d0573f3..d4c0656 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -222,4 +222,4 @@ [All about u-root]: https://github.com/linuxboot/book/tree/master/u-root [u-root]: https://u-root.org/ [ChromeOS VPD]: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md -[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… +[src/mainboard/ocp/deltalake/vpd.h]: https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD/src/mainboard/o… diff --git a/README.md b/README.md index eef5eb6..677d62d 100644 --- a/README.md +++ b/README.md @@ -30,7 +30,7 @@ instance](https://review.coreboot.org/). The code may be browsed via [coreboot's Gitiles -instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master). +instance](https://review.coreboot.org/plugins/gitiles/coreboot/+/HEAD). The coreboot project also maintains a [mirror](https://github.com/coreboot/coreboot) of the project on github. -- To view, visit https://review.coreboot.org/c/coreboot/+/79785?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I16f0c087762ff049115b67de3ac0b881aa4e4b40 Gerrit-Change-Number: 79785 Gerrit-PatchSet: 3 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79740?usp=email ) Change subject: driver/wifi: DDR RFIM _DSM method function 3 report incorrect value ...................................................................... driver/wifi: DDR RFIM _DSM method function 3 report incorrect value The DDR RFIM _DSM method function 3 need to return: - 0: Enable DDR RFIM feature. - 1: Disable DDR RFIM feature. BUG=b:302084312 TEST=Build, dump SSDT to check _DSM function 3 return value Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Signed-off-by: Simon Yang <simon1.yang(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79740 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/drivers/wifi/generic/acpi.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved Rex Chou: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index f55fca7..f37a084 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -144,7 +144,7 @@ static void wifi_dsm_ddrrfim_func3_cb(void *ptr) { const bool is_cnvi_ddr_rfim_enabled = *(bool *)ptr; - acpigen_write_return_integer(is_cnvi_ddr_rfim_enabled ? 1 : 0); + acpigen_write_return_integer(is_cnvi_ddr_rfim_enabled ? 0 : 1); } static void (*wifi_dsm_callbacks[])(void *) = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79740?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I642c56a9c3160cdb41b254dc75e126cacf905b14 Gerrit-Change-Number: 79740 Gerrit-PatchSet: 2 Gerrit-Owner: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt Chen <matt.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[main]: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79566?usp=email ) Change subject: arch/x86: introduce HAVE_CONFIGURABLE_APMC_SMI_PORT ...................................................................... Patch Set 3: (1 comment) File src/arch/x86/Kconfig: https://review.coreboot.org/c/coreboot/+/79566/comment/c817893d_092e67c7 : PS3, Line 322: non-fixed APMC SMI command port > what exactly does non-fixed mean here? dynamically assigned by another firmware component? on intel the io port is hard-wired while on amd the io port can be configured -- To view, visit https://review.coreboot.org/c/coreboot/+/79566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaceb61b0f2a630d7afe2e0780b6a2a9806ea62f9 Gerrit-Change-Number: 79566 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 14:21:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79758?usp=email ) Change subject: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode ...................................................................... nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode In DDR3 DLL-Off mode is an optional feature advertised by SPD. Honor the SPD and only use DLL-Off mode when all DIMMs on the same channel indicate support for it. The same is done on MRC.bin. Tested on Lenovo X220: Still boots fine. Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79758 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 14 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c2a3051..2e49675 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -667,26 +667,32 @@ } /* Obtain optimal power down mode for current configuration */ -static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl) +static enum power_down_mode get_power_down_mode(ramctr_timing *ctrl, int channel) { + int slotrank; + if (ctrl->tXP > 8) return PDM_NONE; if (ctrl->tXPDLL > 32) return PDM_PPD; + FOR_ALL_POPULATED_RANKS + if (!ctrl->info.dimm[channel][slotrank >> 1].flags.dll_off_mode) + return PDM_APD_PPD; + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) return PDM_DLL_OFF; return PDM_APD_PPD; } -static u32 make_mr0(ramctr_timing *ctrl, u8 rank) +static u32 make_mr0(ramctr_timing *ctrl, int channel, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const enum power_down_mode power_down = get_power_down_mode(ctrl); + const enum power_down_mode power_down = get_power_down_mode(ctrl, channel); const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; @@ -715,7 +721,7 @@ static void dram_mr0(ramctr_timing *ctrl, u8 rank, int channel) { - write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, rank)); + write_mrreg(ctrl, channel, rank, 0, make_mr0(ctrl, channel, rank)); } static odtmap get_ODT(ramctr_timing *ctrl, int channel) @@ -2818,13 +2824,13 @@ }; tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); - } - /* 64 DCLKs until idle, decision per rank */ - mchbar_write32(PM_PDWN_CONFIG, get_power_down_mode(ctrl) << 8 | 64); + /* 64 DCLKs until idle, decision per rank */ + r32 = get_power_down_mode(ctrl, channel) << 8 | 64; + mchbar_write32(PM_PDWN_CONFIG_ch(channel), r32); - FOR_ALL_CHANNELS mchbar_write32(PM_TRML_M_CONFIG_ch(channel), 0x00000aaa); + } mchbar_write32(PM_BW_LIMIT_CONFIG, 0x5f7003ff); mchbar_write32(PM_DLL_CONFIG, 0x00073000 | ctrl->mdll_wake_delay); -- To view, visit https://review.coreboot.org/c/coreboot/+/79758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Gerrit-Change-Number: 79758 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl
by Felix Held (Code Review) 04 Jan '24

04 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79653?usp=email ) Change subject: soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl ...................................................................... soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/mainboard/amd/bilby/dsdt.asl M src/mainboard/amd/mandolin/dsdt.asl M src/mainboard/google/zork/dsdt.asl M src/soc/amd/picasso/acpi/soc.asl 4 files changed, 39 insertions(+), 77 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl index dd42608..57ee5d6 100644 --- a/src/mainboard/amd/bilby/dsdt.asl +++ b/src/mainboard/amd/bilby/dsdt.asl @@ -14,25 +14,7 @@ ) { /* Start of ASL file */ #include <acpi/dsdt_top.asl> - #include <globalnvs.asl> - /* Power state notification to ALIB */ - #include <pnot.asl> - - /* Contains the supported sleep states for this chipset */ - #include <soc/amd/common/acpi/sleepstates.asl> - - /* Contains _SWS methods */ - #include <soc/amd/common/acpi/acpi_wake_source.asl> - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe the SOC */ - #include <soc.asl> - - } /* End \_SB scope */ + #include <soc.asl> } /* End of ASL file */ diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl index dd42608..57ee5d6 100644 --- a/src/mainboard/amd/mandolin/dsdt.asl +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -14,25 +14,7 @@ ) { /* Start of ASL file */ #include <acpi/dsdt_top.asl> - #include <globalnvs.asl> - /* Power state notification to ALIB */ - #include <pnot.asl> - - /* Contains the supported sleep states for this chipset */ - #include <soc/amd/common/acpi/sleepstates.asl> - - /* Contains _SWS methods */ - #include <soc/amd/common/acpi/acpi_wake_source.asl> - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe the SOC */ - #include <soc.asl> - - } /* End \_SB scope */ + #include <soc.asl> } /* End of ASL file */ diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index dc4322d..4cb8506 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -18,26 +18,7 @@ Name(LIDS, 0) - #include <globalnvs.asl> - - /* Power state notification to ALIB */ - #include <pnot.asl> - - /* Contains the supported sleep states for this chipset */ - #include <soc/amd/common/acpi/sleepstates.asl> - - /* Contains _SWS methods */ - #include <soc/amd/common/acpi/acpi_wake_source.asl> - - /* System Bus */ - Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ - #include <arch/x86/acpi/globutil.asl> - - /* Describe the SOC */ - #include <soc.asl> - - } /* End \_SB scope */ + #include <soc.asl> /* Thermal handler */ #include <variant/acpi/thermal.asl> diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl index a958570..7c13f08 100644 --- a/src/soc/amd/picasso/acpi/soc.asl +++ b/src/soc/amd/picasso/acpi/soc.asl @@ -1,30 +1,47 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <soc/amd/common/acpi/pci_root.asl> +#include "globalnvs.asl" -ROOT_BRIDGE(PCI0) +/* Power state notification to ALIB */ +#include "pnot.asl" -Scope(PCI0) { - /* Describe the AMD Northbridge */ - #include "northbridge.asl" +/* Contains the supported sleep states for this chipset */ +#include <soc/amd/common/acpi/sleepstates.asl> - /* Describe the AMD Fusion Controller Hub */ - #include <soc/amd/common/acpi/lpc.asl> - #include <soc/amd/common/acpi/platform.asl> -} +/* Contains _SWS methods */ +#include <soc/amd/common/acpi/acpi_wake_source.asl> -/* PCI IRQ mapping for the Southbridge */ -#include "pci_int_defs.asl" +/* System Bus */ +Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> -/* Describe PCI INT[A-H] for the Southbridge */ -#include <soc/amd/common/acpi/pci_int.asl> + ROOT_BRIDGE(PCI0) -/* Describe the MMIO devices in the FCH */ -#include "mmio.asl" + Scope(PCI0) { + /* Describe the AMD Northbridge */ + #include "northbridge.asl" -/* Add GPIO library */ -#include <soc/amd/common/acpi/gpio_bank_lib.asl> + /* Describe the AMD Fusion Controller Hub */ + #include <soc/amd/common/acpi/lpc.asl> + #include <soc/amd/common/acpi/platform.asl> + } -#if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) -#include <soc/amd/common/acpi/dptc.asl> -#endif + /* PCI IRQ mapping for the Southbridge */ + #include "pci_int_defs.asl" + + /* Describe PCI INT[A-H] for the Southbridge */ + #include <soc/amd/common/acpi/pci_int.asl> + + /* Describe the MMIO devices in the FCH */ + #include "mmio.asl" + + /* Add GPIO library */ + #include <soc/amd/common/acpi/gpio_bank_lib.asl> + + #if CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC) + #include <soc/amd/common/acpi/dptc.asl> + #endif + +} /* End \_SB scope */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79653?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Gerrit-Change-Number: 79653 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[main]: soc/mediatek: Add common implmentation to configure display
by Yidi Lin (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79776?usp=email ) Change subject: soc/mediatek: Add common implmentation to configure display ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79776/comment/9f92606f_da2d8b32 : PS1, Line 7: a common implmentation to configure display > Please make it a statement by adding a verb (in imperative mood). Maybe: […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Gerrit-Change-Number: 79776 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Thu, 04 Jan 2024 14:00:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: soc/mediatek: Add common implmentation to configure display
by Yidi Lin (Code Review) 04 Jan '24

04 Jan '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79776?usp=email to look at the new patch set (#2). Change subject: soc/mediatek: Add common implmentation to configure display ...................................................................... soc/mediatek: Add common implmentation to configure display The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to soc/common/display.c and refacts `struct panel_description` to generalize the sequences of configure_display(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/geralt/Makefile.inc M src/mainboard/google/geralt/mainboard.c M src/mainboard/google/geralt/panel.h M src/mainboard/google/geralt/panel_geralt.c R src/soc/mediatek/common/display.c M src/soc/mediatek/common/include/soc/ddp_common.h A src/soc/mediatek/common/include/soc/display.h M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/ddp.h 9 files changed, 50 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79776/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Gerrit-Change-Number: 79776 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2024