coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Rex Chou (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Dtrain Hsu, Eric Lai, Kenny Pan, Nick Vaccaro, Paul Menzel, Shou-Chieh Hsu, Subrata Banik. Rex Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79764?usp=email ) Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79764/comment/25795dea_9ebe1fb7 : PS1, Line 2: rex_chou > Please use Rex Chou. […] Done https://review.coreboot.org/c/coreboot/+/79764/comment/34451045_4b7bb869 : PS1, Line 11: This will allow coreboot : to detect the presence of i2c touchscreens during ACPI SSDT generation : (implemented in a subsequent commit). : > is true? removed https://review.coreboot.org/c/coreboot/+/79764/comment/078ca293_78674d65 : PS1, Line 18: Change-Id: I85f2bee58582c0f56331d20a2984a3079c967be4 : Signed-off-by: rex_chou <rex_chou(a)compal.corp-partner.google.com> : : Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 : > Two Change-Id tags? "Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690" is the correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 02 Jan 2024 01:56:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing
by Rex Chou (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: Dtrain Hsu, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Subrata Banik. Hello Dtrain Hsu, Eric Lai, Kenny Pan, Nick Vaccaro, Shou-Chieh Hsu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79764?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/craaskov: Implement touchscreen power sequencing ...................................................................... mb/google/nissa/var/craaskov: Implement touchscreen power sequencing For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:317746281 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Signed-off-by: Rex Chou <rex_chou(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/gpio.c 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79764/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79764?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3ca2e2d12a86eaae9e37870a2541c0287e354690 Gerrit-Change-Number: 79764 Gerrit-PatchSet: 2 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/rex/var/karis: Enhance CNVi and PCIe switching
by Tyler Wang (Code Review) 02 Jan '24

02 Jan '24

Attention is currently required from: David Wu, Dinesh Gehlot, Eran Mitrani, Jack Lai, Jakub Czapiga, Kapil Porwal, Mac Chiang, Tarun, Tyler Wang. Hello David Wu, Dinesh Gehlot, Eran Mitrani, Jack Lai, Jakub Czapiga, Kapil Porwal, Mac Chiang, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79765?usp=email to look at the new patch set (#3). Change subject: mb/google/rex/var/karis: Enhance CNVi and PCIe switching ...................................................................... mb/google/rex/var/karis: Enhance CNVi and PCIe switching 1. Set PCIe related GPIOs to NC if fw_config use "WIFI_CNVI". 2. Set CNVi related GPIOs to NC if fw_config use "WIFI_PCIE". 3. Remove "ALC5650_NO_AMP_I2S" case in fw_config_gpio_padbased_override(). bt_i2s_enable_pads should not relevant to audio codec/amp, and it is already enabled in "WIFI_CNVI" case. BUG=b:312099281 TEST=Build and test on karis Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Signed-off-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> --- M src/mainboard/google/rex/variants/karis/fw_config.c 1 file changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/79765/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79765?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1a32f1a38ae33cf992b80a3408aa8e2fa3ddab0 Gerrit-Change-Number: 79765 Gerrit-PatchSet: 3 Gerrit-Owner: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jack Lai <jack.lai(a)intel.corp-partner.google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: mb/dell: Add Dell Precision M4800 (Haswell)
by Justin Wu (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Paul Menzel. Justin Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79755?usp=email ) Change subject: mb/dell: Add Dell Precision M4800 (Haswell) ...................................................................... Patch Set 4: (3 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/79755/comment/5bf6a19d_e6d64f53 : PS3, Line 9: workstation > Is it a laptop? Correct, it is indeed a laptop. Maybe we could call it a mobile workstation? https://review.coreboot.org/c/coreboot/+/79755/comment/9f15df36_60de4542 : PS3, Line 38: - Physical Wireless switch > What does that mean? Wifi does not work, but the system things it’s still enabled? I should clarify that these two commits are necessary for wifi to work: https://review.coreboot.org/c/coreboot/+/79011/1 and https://review.coreboot.org/c/coreboot/+/77534/7. Without them, I believe I observed that the kernel detects the wifi card but can't enable it. Patchset: PS3: > Welcome to coreboot, and thank you for this great contribution. Thank you for the warm welcome. -- To view, visit https://review.coreboot.org/c/coreboot/+/79755?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I49870b28be943dcb1932909f9d3ec4207cc11436 Gerrit-Change-Number: 79755 Gerrit-PatchSet: 4 Gerrit-Owner: Justin Wu <jxw5883(a)runbox.io> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Mon, 01 Jan 2024 19:28:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification
by Subrata Banik (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79291?usp=email ) Change subject: soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79291?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I382e62a765dbf2027c4ac54d6eb19a9542a8c302 Gerrit-Change-Number: 79291 Gerrit-PatchSet: 10 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Jan 2024 16:11:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode
by Arthur Heymans (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons, Patrick Rudolph. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79758?usp=email ) Change subject: nb/intel/sandybridge/raminit: Honor SPD's dll_off_mode ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79758?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ief4bfb9e045cad7ff9953f6fda248586ea951a52 Gerrit-Change-Number: 79758 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 01 Jan 2024 09:28:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79784?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge ...................................................................... nb/intel/sandybridge/raminit: Set SRT on Sandy Bridge On Sandy Bridge the MRC.bin sets bit SRT in register TC_MR2_SHADOW as well as it's currently done on Ivy Bridge. Tested on Lenovo X220: Still boots and works fine. Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79784/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 16751b9..2033043 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -783,6 +783,8 @@ int srt = 0; if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; + else if (IS_SANDY_CPU(ctrl->cpu)) + srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; u16 mr2reg = 0; mr2reg |= pasr; -- To view, visit https://review.coreboot.org/c/coreboot/+/79784?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2773d3ae8c6c48193a23174086f62617335a7af Gerrit-Change-Number: 79784 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79783?usp=email ) Change subject: nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis ...................................................................... nb/intel/sandybridge/raminit: Set MR2 on per DIMM basis Improve mixed DIMM configurations by setting MR2 on per DIMM basis instead of using the common denominator. Drop now unused variables and bump the MRC_CACHE revision counter. The same is done on MRC.bin. Tested on Lenovo X220: Still boots and works fine. Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_common.h 3 files changed, 5 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79783/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 085292b..f026043 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -200,9 +200,6 @@ memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap)); - ctrl->extended_temperature_range = 1; - ctrl->auto_self_refresh = 1; - FOR_ALL_CHANNELS { ctrl->channel_size_mb[channel] = 0; @@ -273,10 +270,6 @@ if (!dimm->flags.is_ecc) can_use_ecc = false; - ctrl->auto_self_refresh &= dimm->flags.asr; - - ctrl->extended_temperature_range &= dimm->flags.ext_temp_refresh; - ctrl->rankmap[channel] |= ((1 << dimm->ranks) - 1) << (2 * slot); printk(BIOS_DEBUG, "channel[%d] rankmap = 0x%x\n", channel, diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index de24400..16751b9 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -778,15 +778,16 @@ const u16 pasr = 0; const u16 cwl = ctrl->CWL - 5; const odtmap odt = get_ODT(ctrl, channel); + struct dimm_attr_ddr3_st *const dimm = &ctrl->info.dimm[channel][rank/2]; int srt = 0; if (IS_IVY_CPU(ctrl->cpu) && ctrl->tCK >= TCK_1066MHZ) - srt = ctrl->extended_temperature_range && !ctrl->auto_self_refresh; + srt = dimm->flags.ext_temp_refresh && !dimm->flags.asr; u16 mr2reg = 0; mr2reg |= pasr; mr2reg |= cwl << 3; - mr2reg |= ctrl->auto_self_refresh << 6; + mr2reg |= dimm->flags.asr << 6; mr2reg |= srt << 7; mr2reg |= (odt.rttwr / 60) << 9; @@ -795,7 +796,7 @@ /* Program MR2 shadow */ u32 reg32 = mchbar_read32(TC_MR2_SHADOW_ch(channel)); - reg32 &= 3 << 14 | 3 << 6; + reg32 &= 1 << (rank / 2 + 14) | 1 << (rank / 2 + 6); reg32 |= mr2reg & ~(3 << 6); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index ee7c525..3303646 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -305,7 +305,7 @@ /* * WARNING: Do not forget to increase MRC_CACHE_VERSION when the saved data is changed! */ -#define MRC_CACHE_VERSION 5 +#define MRC_CACHE_VERSION 6 enum power_down_mode { PDM_NONE = 0, @@ -410,9 +410,6 @@ int edge_offset[3]; int tx_dq_offset[3]; - int extended_temperature_range; - int auto_self_refresh; - int rank_mirror[NUM_CHANNELS][NUM_SLOTRANKS]; struct ram_rank_timings timings[NUM_CHANNELS][NUM_SLOTRANKS]; -- To view, visit https://review.coreboot.org/c/coreboot/+/79783?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia60d1c01b79be2ac18ca6cc90109f817d1624c55 Gerrit-Change-Number: 79783 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Add tCPDED corner case
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79762?usp=email ) Change subject: nb/intel/sandybridge/raminit: Add tCPDED corner case ...................................................................... nb/intel/sandybridge/raminit: Add tCPDED corner case tCPDED is always 1, except for steppings earlier than SandyBridge D0. Tested on Lenovo X220: Still boots and runs fine. Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79762/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 50c0fb4..de24400 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -172,7 +172,7 @@ .tXPDLL = MIN(ctrl->tXPDLL, 31), .tXP = MIN(ctrl->tXP, 7), .tAONPD = ctrl->tAONPD, - .tCPDED = 2, + .tCPDED = 1, .tPRPDEN = 1, }; @@ -2822,7 +2822,10 @@ union tc_othp_reg tc_othp = { .raw = mchbar_read32(TC_OTHP_ch(channel)), }; - tc_othp.tCPDED = 1; + if (IS_SANDY_CPU(ctrl->cpu) && (ctrl->cpu & 0xf) < SNB_STEP_D0) + tc_othp.tCPDED = 2; + else + tc_othp.tCPDED = 1; mchbar_write32(TC_OTHP_ch(channel), tc_othp.raw); /* 64 DCLKs until idle, decision per rank */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79762?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5294173c02f06c601fdb13ed785ee33d7a4e3eca Gerrit-Change-Number: 79762 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: nb/intel/sandybridge/raminit: Only write register on IvyBridge
by Patrick Rudolph (Code Review) 01 Jan '24

01 Jan '24

Attention is currently required from: Angel Pons. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79761?usp=email ) Change subject: nb/intel/sandybridge/raminit: Only write register on IvyBridge ...................................................................... nb/intel/sandybridge/raminit: Only write register on IvyBridge Only write register WMM_READ_CONFIG on Ivy Bridge as it's reserved on Sandy Bridge. Tested on Lenovo X220: Still boots and runs fine. Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79761/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c62e1cd..50c0fb4 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2815,8 +2815,8 @@ int t3_ns; u32 r32; - /* FIXME: This register only exists on Ivy Bridge */ - mchbar_write32(WMM_READ_CONFIG, 0x46); + if (IS_IVY_CPU(ctrl->cpu)) + mchbar_write32(WMM_READ_CONFIG, 0x46); FOR_ALL_CHANNELS { union tc_othp_reg tc_othp = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79761?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie14ea06d744b1a8368d32803c6c1ccfb1262532e Gerrit-Change-Number: 79761 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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