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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: use common AMD MADT code
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79885?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use common AMD MADT code ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79885/comment/a2c0e3d3_b40284b2 : PS1, Line 13: TEST=TODO still need to test this one, but expect it to work -- To view, visit https://review.coreboot.org/c/coreboot/+/79885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Gerrit-Change-Number: 79885 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Tue, 09 Jan 2024 21:27:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: use common AMD MADT code
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79885?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use common AMD MADT code ...................................................................... soc/amd/stoneyridge/acpi: use common AMD MADT code Now that Stoneyridge also reports the GNB IOAPIC on the domain and with the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we ca switch over to using this common code on Stoneyridge too. TEST=TODO Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If4ce71a47827e144c4d4991152101650904901f2 --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79885/1 diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index dadda8d..b823d02 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -18,6 +18,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM select SOC_AMD_COMMON_BLOCK_ACPIMMIO_PM_IO_ACCESS diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dc7ef5f..9dd8d72 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -22,13 +22,6 @@ #include <soc/southbridge.h> #include <soc/northbridge.h> -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/79885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Gerrit-Change-Number: 79885 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79884?usp=email ) Change subject: soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain ...................................................................... soc/amd/stoneyridge/northbridge: report GNB IOAPIC in domain Move the GNB IOAPIC resource from being reported in the GNB PCI device to the domain and use IOMMU_IOAPIC_IDX as resource index, so that the common AMD MADT code will be able to find the resource. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 --- M src/soc/amd/stoneyridge/northbridge.c 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/79884/1 diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index bf2f992..2b6ba45 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -43,9 +43,6 @@ * the CPU_CLUSTER. */ mmconf_resource(dev, idx++); - - /* NB IOAPIC2 resource */ - mmio_range(dev, idx++, IO_APIC2_ADDR, 0x1000); } /** @@ -301,6 +298,10 @@ /* Low top usable RAM -> Low top RAM (bottom pci mmio hole) */ reserved_ram_from_to(dev, idx++, mem_useable, tom); + /* NB IOAPIC2 resource. IOMMU_IOAPIC_IDX is used as index, so that the common AMD MADT + code can find this resource */ + mmio_range(dev, IOMMU_IOAPIC_IDX, IO_APIC2_ADDR, 0x1000); + /* If there is memory above 4GiB */ if (high_tom >> 32) { /* 4GiB -> high top usable */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79884?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6e9aaf4a3fa2c5b0266fd9fb8254285f8555317 Gerrit-Change-Number: 79884 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: drop wrong comment in MADT code
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79883?usp=email ) Change subject: soc/amd/stoneyridge/acpi: drop wrong comment in MADT code ...................................................................... soc/amd/stoneyridge/acpi: drop wrong comment in MADT code The IOAPIC structure that this function created is for the IOAPIC in the GNB and not the one in the FCH which is called Kern in this SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 --- M src/soc/amd/stoneyridge/acpi.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/79883/1 diff --git a/src/soc/amd/stoneyridge/acpi.c b/src/soc/amd/stoneyridge/acpi.c index dc050cf..dc7ef5f 100644 --- a/src/soc/amd/stoneyridge/acpi.c +++ b/src/soc/amd/stoneyridge/acpi.c @@ -24,7 +24,6 @@ unsigned long acpi_fill_madt(unsigned long current) { - /* Write Kern IOAPIC, only one */ current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, IO_APIC2_ADDR); return current; -- To view, visit https://review.coreboot.org/c/coreboot/+/79883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6eec02578f2b2e8b8c10dad7eeecff961ef45e76 Gerrit-Change-Number: 79883 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79862?usp=email ) Change subject: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h ...................................................................... soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to amdblocks/ioapic.h which is both a more logical place for it to be and this is also a preparation to use the common AMD MADT code for the Stoneyridge SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 --- M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/acpi/madt.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/common/block/include/amdblocks/ioapic.h M src/soc/amd/genoa_poc/domain.c 5 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79862/1 diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 814f514..140968c 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -3,7 +3,6 @@ #include <acpi/acpi_ivrs.h> #include <amdblocks/acpi.h> #include <amdblocks/cpu.h> -#include <amdblocks/data_fabric.h> #include <amdblocks/ioapic.h> #include <amdblocks/iommu.h> #include <arch/ioapic.h> diff --git a/src/soc/amd/common/block/acpi/madt.c b/src/soc/amd/common/block/acpi/madt.c index 14fab74b..b502053c 100644 --- a/src/soc/amd/common/block/acpi/madt.c +++ b/src/soc/amd/common/block/acpi/madt.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> -#include <amdblocks/data_fabric.h> +#include <amdblocks/ioapic.h> #include <device/device.h> unsigned long acpi_fill_madt(unsigned long current) diff --git a/src/soc/amd/common/block/include/amdblocks/data_fabric.h b/src/soc/amd/common/block/include/amdblocks/data_fabric.h index 3a08a20..9dbf5da 100644 --- a/src/soc/amd/common/block/include/amdblocks/data_fabric.h +++ b/src/soc/amd/common/block/include/amdblocks/data_fabric.h @@ -13,9 +13,6 @@ #define BROADCAST_FABRIC_ID 0xff -/* Index of IOAPIC resource associated with IOMMU */ -#define IOMMU_IOAPIC_IDX 0x20000120 - #define DF_MMIO_REG_OFFSET(instance) ((instance) * DF_MMIO_REG_SET_SIZE * sizeof(uint32_t)) /* The number of data fabric MMIO registers is SoC-specific */ diff --git a/src/soc/amd/common/block/include/amdblocks/ioapic.h b/src/soc/amd/common/block/include/amdblocks/ioapic.h index bd1c363..37f4b29 100644 --- a/src/soc/amd/common/block/include/amdblocks/ioapic.h +++ b/src/soc/amd/common/block/include/amdblocks/ioapic.h @@ -7,4 +7,7 @@ #define FCH_IOAPIC_ID 0 #define GNB_IOAPIC_ID 1 +/* Index of IOAPIC resource associated with IOMMU */ +#define IOMMU_IOAPIC_IDX 0x20000120 + #endif /* AMD_BLOCK_IOAPIC_H */ diff --git a/src/soc/amd/genoa_poc/domain.c b/src/soc/amd/genoa_poc/domain.c index 8ed95ab..f21cad5 100644 --- a/src/soc/amd/genoa_poc/domain.c +++ b/src/soc/amd/genoa_poc/domain.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <amdblocks/ioapic.h> #include <amdblocks/data_fabric.h> #include <amdblocks/root_complex.h> #include <amdblocks/smn.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/79862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Gerrit-Change-Number: 79862 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/amd/common/acpi: factor out common MADT code
by Felix Held (Code Review) 09 Jan '24

09 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79861?usp=email ) Change subject: soc/amd/common/acpi: factor out common MADT code ...................................................................... soc/amd/common/acpi: factor out common MADT code The acpi_fill_madt implementation from the Genoa PoC also works for the other AMD SoCs that select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN, so factor out this function to the common AMD ACPI code and change those other SoCs to use the new common functionality instead of having their own implementations. The old code on the single-domain SoCs used the GNB_IO_APIC_ADDR base address to create the MADT entry for the additional IOAPIC in the root complex. The new code iterates over all domains and looks for a resource with the IOMMU_IOAPIC_IDX index in each domain and if it finds it, it creates an MADT entry for that IOAPIC. This resource is created earlier in the boot process when the non-PCI resources are read from the IOHC registers and reported to the allocator. TEST=The resulting MADT doesn't change on Mandolin Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/acpi.c M src/soc/amd/common/block/acpi/Kconfig M src/soc/amd/common/block/acpi/Makefile.inc A src/soc/amd/common/block/acpi/madt.c M src/soc/amd/genoa_poc/Kconfig M src/soc/amd/genoa_poc/acpi.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/acpi.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/acpi.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/acpi.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi.c 15 files changed, 32 insertions(+), 58 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79861/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 9c15dd9..42a7bf3 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -35,6 +35,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index 4d2482d..ea895c9 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -18,15 +18,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/common/block/acpi/Kconfig b/src/soc/amd/common/block/acpi/Kconfig index 9355f7d..1553edc 100644 --- a/src/soc/amd/common/block/acpi/Kconfig +++ b/src/soc/amd/common/block/acpi/Kconfig @@ -30,6 +30,11 @@ config SOC_AMD_COMMON_BLOCK_ACPI_IVRS bool +config SOC_AMD_COMMON_BLOCK_ACPI_MADT + bool + help + TODO + config ACPI_SSDT_PSD_INDEPENDENT bool "Allow core p-state independent transitions" default y diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index a0d9290..763a3bc 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -12,6 +12,7 @@ ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE) += cpu_power_state.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_GPIO) += gpio.c ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_IVRS) += ivrs.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI_MADT) += madt.c romstage-y += elog.c ramstage-y += elog.c diff --git a/src/soc/amd/common/block/acpi/madt.c b/src/soc/amd/common/block/acpi/madt.c new file mode 100644 index 0000000..14fab74b --- /dev/null +++ b/src/soc/amd/common/block/acpi/madt.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <amdblocks/data_fabric.h> +#include <device/device.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + struct device *dev = NULL; + while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { + struct resource *res = probe_resource(dev, IOMMU_IOAPIC_IDX); + if (!res) + continue; + + current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, + res->base); + } + + return current; +} diff --git a/src/soc/amd/genoa_poc/Kconfig b/src/soc/amd/genoa_poc/Kconfig index 19ffe6c..09e04f3 100644 --- a/src/soc/amd/genoa_poc/Kconfig +++ b/src/soc/amd/genoa_poc/Kconfig @@ -17,6 +17,7 @@ select SOC_AMD_COMMON_BLOCK_ACPIMMIO select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H diff --git a/src/soc/amd/genoa_poc/acpi.c b/src/soc/amd/genoa_poc/acpi.c index d9b934f..7762e9d 100644 --- a/src/soc/amd/genoa_poc/acpi.c +++ b/src/soc/amd/genoa_poc/acpi.c @@ -6,29 +6,12 @@ #include <amdblocks/acpi.h> #include <amdblocks/acpimmio.h> #include <amdblocks/cpu.h> -#include <amdblocks/data_fabric.h> #include <arch/ioapic.h> #include <console/console.h> #include <device/device.h> #include <soc/acpi.h> #include <vendorcode/amd/opensil/genoa_poc/opensil.h> -/* TODO: this can go in a common place */ -unsigned long acpi_fill_madt(unsigned long current) -{ - struct device *dev = NULL; - while ((dev = dev_find_path(dev, DEVICE_PATH_DOMAIN)) != NULL) { - struct resource *res = probe_resource(dev, IOMMU_IOAPIC_IDX); - if (!res) - continue; - - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - res->base); - } - - return current; -} - void acpi_fill_fadt(acpi_fadt_t *fadt) { /* Fill in pm1_evt, pm1_cnt, pm_tmr, gpe0_blk from openSIL input structure */ diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a3b0ea6..9d71da4 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -36,6 +36,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 88cf688..a927f8b 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -21,14 +21,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index d5aae52..7192106 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 07f4d3e..80d407c 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -20,14 +20,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index d35ecc2..cd28725 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -38,6 +38,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ACPI_IVRS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index 9ed1159b..ce727a8 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -21,14 +21,6 @@ #include <types.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index ee5e130..f501398 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -30,6 +30,7 @@ select SOC_AMD_COMMON_BLOCK_ACPI_CPU_POWER_STATE select SOC_AMD_COMMON_BLOCK_ACPI_GPIO select SOC_AMD_COMMON_BLOCK_ACPI_IVRS + select SOC_AMD_COMMON_BLOCK_ACPI_MADT select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index c6aa83f..92f48df 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -24,14 +24,6 @@ #include <soc/southbridge.h> #include "chip.h" -unsigned long acpi_fill_madt(unsigned long current) -{ - current += acpi_create_madt_ioapic_from_hw((acpi_madt_ioapic_t *)current, - GNB_IO_APIC_ADDR); - - return current; -} - /* * Reference section 5.2.9 Fixed ACPI Description Table (FADT) * in the ACPI 3.0b specification. -- To view, visit https://review.coreboot.org/c/coreboot/+/79861?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258 Gerrit-Change-Number: 79861 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: [DNM] {arch,cpu}/x86: Support runtime page tables for SMM
by Benjamin Doron (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Jérémy Compostella. Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79865?usp=email ) Change subject: [DNM] {arch,cpu}/x86: Support runtime page tables for SMM ...................................................................... [DNM] {arch,cpu}/x86: Support runtime page tables for SMM ramstage generates page tables for SMM during MP init, so that they're available to smm_stub. However, this causes complications: the `page_tables` variable now points to SMM page tables. TODO: - It would be optimal to only map SMRAM and known resources. However, this causes a triple-fault. Will investigate. - Must confirm if SMM_DEFAULT_BASE is available, and if placing page tables there is optimal. - Finalise page table size. Change-Id: Ie9f4f9834da0e115758918f80f93264c8c487ec5 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/arch/x86/Makefile.inc M src/arch/x86/include/arch/mmu.h A src/arch/x86/mmu-smm.c M src/cpu/x86/smm/smm_module_loader.c M src/cpu/x86/smm/smm_stub.S M src/include/cpu/x86/smm.h 6 files changed, 111 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/79865/1 diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index bdd89bd..e7406a4 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -281,6 +281,7 @@ ramstage-$(CONFIG_HAVE_CF9_RESET) += cf9_reset.c all-$(CONFIG_ARCH_X86_MMU_PAGE_TABLES) += mmu.c ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += mmu-ramstage.c +ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_64) += mmu-smm.c rmodules_x86_32-y += memcpy.c rmodules_x86_32-y += memmove_32.c diff --git a/src/arch/x86/include/arch/mmu.h b/src/arch/x86/include/arch/mmu.h index 6df16aa..7ed19ea 100644 --- a/src/arch/x86/include/arch/mmu.h +++ b/src/arch/x86/include/arch/mmu.h @@ -88,6 +88,7 @@ #define PAT_UC_MINUS 7 void mmu_init_pre_cbmem(void); +void mmu_setup_smm_resources(uintptr_t page_tables, size_t page_tables_size, bool permanent); struct region; void mmu_init_region(struct region *r); diff --git a/src/arch/x86/mmu-smm.c b/src/arch/x86/mmu-smm.c new file mode 100644 index 0000000..6595580 --- /dev/null +++ b/src/arch/x86/mmu-smm.c @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/mmu.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/smm.h> +#include <device/resource.h> +#include <stdint.h> + +static void mmu_init_ranges(void *gp, struct device *dev, struct resource *res) +{ + uintptr_t smm_base; + size_t smm_size; + + if (!res->size || !IS_ALIGNED(res->size, 4 * KiB)) + return; + + smm_region(&smm_base, &smm_size); + if (res->base == smm_base) + return; + + const int addr_bits = MIN(cpu_phys_address_size(), BITS_PER_VA); + const uint64_t limit = 1ULL << addr_bits; + + if (res->size >= limit || res->base >= limit || (res->size + res->size) >= limit) + return; + + if (res->flags & IORESOURCE_CACHEABLE) + mmu_config_range(res->base, res->size, PAT_WB); + else if (res->flags & IORESOURCE_PREFETCH) + mmu_config_range(res->base, res->size, PAT_WT); + else if (res->flags & IORESOURCE_READONLY) + mmu_config_range(res->base, res->size, PAT_WP); + + /* Default mapping is UC, skip it */ +} + +void mmu_setup_smm_resources(uintptr_t page_tables, size_t page_tables_size, bool permanent) +{ + struct region r; + uintptr_t smm_base; + size_t smm_size; + + printk(BIOS_DEBUG, "MMU: Setup\n"); + + r.offset = page_tables; + r.size = page_tables_size; + mmu_init_region(&r); + + if (!permanent) { + /* smm_stub calls into ramstage:smm_do_relocation() */ + smm_base = 0; + smm_size = 4ULL * GiB; + } else { + /* BUGBUG: Broken! */ + smm_region(&smm_base, &smm_size); + + search_global_resources(IORESOURCE_MEM | IORESOURCE_ASSIGNED, + IORESOURCE_MEM | IORESOURCE_ASSIGNED, + mmu_init_ranges, 0); + } + + mmu_config_range(smm_base, smm_size, PAT_WB); + + printk(BIOS_DEBUG, "MMU: Setup done\n"); +} diff --git a/src/cpu/x86/smm/smm_module_loader.c b/src/cpu/x86/smm/smm_module_loader.c index f827e7b..3f27986 100644 --- a/src/cpu/x86/smm/smm_module_loader.c +++ b/src/cpu/x86/smm/smm_module_loader.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi_gnvs.h> +#include <arch/mmu.h> #include <cbmem.h> #include <commonlib/helpers.h> #include <commonlib/region.h> @@ -13,7 +14,12 @@ #include <string.h> #include <types.h> -#define SMM_CODE_SEGMENT_SIZE 0x10000 +#define SMM_CODE_SEGMENT_SIZE 0x10000 +#define RELOC_PAGE_TABLE_SIZE (6 * (4 * KiB)) +#define PERMANENT_PAGE_TABLE_SIZE (8 * (4 * KiB)) +_Static_assert(RELOC_PAGE_TABLE_SIZE <= (SMM_DEFAULT_BASE + SMM_DEFAULT_SIZE) \ + - (SMM_DEFAULT_BASE + SMM_ENTRY_OFFSET), \ + "page tables are too large"); /* * Components that make up the SMRAM: @@ -259,6 +265,7 @@ stub_params->stack_top = stack_top; stub_params->stack_size = g_stack_size; stub_params->c_handler = (uintptr_t)params->handler; + stub_params->smm_page_tables = params->smm_page_tables; /* This runs on the BSP. All the APs are its siblings */ struct cpu_info *info = cpu_info(); @@ -312,6 +319,13 @@ if (params->num_cpus == 0) params->num_cpus = CONFIG_MAX_CPUS; + // TODO/TEST: 0x30000 is available; SMM_DEFAULT_BASE is page-aligned + params->smm_page_tables = 0; + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + mmu_setup_smm_resources(smram, RELOC_PAGE_TABLE_SIZE, false); + params->smm_page_tables = smram; + } + printk(BIOS_SPEW, "%s: exit\n", __func__); return smm_module_setup_stub(smram, SMM_DEFAULT_SIZE, params); } @@ -353,8 +367,8 @@ region_end(&region)); } -/* STM + Handler + (Stub + Save state) * CONFIG_MAX_CPUS + stacks */ -#define SMM_REGIONS_ARRAY_SIZE (1 + 1 + CONFIG_MAX_CPUS * 2 + 1) +/* STM + Handler + (Stub + Save state) * CONFIG_MAX_CPUS + page tables + stacks */ +#define SMM_REGIONS_ARRAY_SIZE (1 + 1 + CONFIG_MAX_CPUS * 2 + 1 + 1) static int append_and_check_region(const struct region smram, const struct region region, @@ -398,6 +412,8 @@ * +-----------------+ * | smi handler | * | ... | + * +-----------------+ + * | page tables | * +-----------------+ <- cpu0 * | stub code | <- cpu1 * | stub code | <- cpu2 @@ -455,6 +471,24 @@ uintptr_t stub_segment_base = handler_base - SMM_CODE_SEGMENT_SIZE; + params->smm_page_tables = 0; + if (CONFIG(ARCH_RAMSTAGE_X86_64)) { + const size_t page_tables_size = PERMANENT_PAGE_TABLE_SIZE; + const uintptr_t page_tables_base = + ALIGN_DOWN(smram_top - stm_size - handler_size - page_tables_size, + 4 * KiB); + struct region page_tables = { + .offset = page_tables_base, + .size = page_tables_size + }; + if (append_and_check_region(smram, page_tables, region_list, "page tables")) + return -1; + mmu_setup_smm_resources(page_tables_base, page_tables_size, true); + params->smm_page_tables = page_tables_base; + + stub_segment_base -= ALIGN_DOWN(page_tables_size, 4 * KiB); + } + if (!smm_create_map(stub_segment_base, params->num_concurrent_save_states, params)) { printk(BIOS_ERR, "%s: Error creating CPU map\n", __func__); return -1; diff --git a/src/cpu/x86/smm/smm_stub.S b/src/cpu/x86/smm/smm_stub.S index 802dd92..26d3a2f 100644 --- a/src/cpu/x86/smm/smm_stub.S +++ b/src/cpu/x86/smm/smm_stub.S @@ -27,6 +27,8 @@ * into the table. */ apic_to_cpu_num: .fill CONFIG_MAX_CPUS,2,0xffff +smm_page_tables: +.long 0 .data /* Provide fallback stack to use when a valid CPU number cannot be found. */ @@ -196,7 +198,7 @@ mov %ecx, %edi /* Get page table address */ - movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + movl smm_page_tables, %eax /* entry64.inc preserves ebx, esi, edi, ebp */ #include <cpu/x86/64bit/entry64.inc> diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a240ac2..2cea625 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -114,6 +114,7 @@ * contiguous like the 1:1 mapping it is up to the caller of the stub * loader to adjust this mapping. */ u16 apic_id_to_cpu[CONFIG_MAX_CPUS]; + u32 smm_page_tables; } __packed; /* smm_handler_t is called with arg of smm_module_params pointer. */ @@ -162,6 +163,8 @@ size_t cpu_save_state_size; size_t num_concurrent_save_states; + uint32_t smm_page_tables; + smm_handler_t handler; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/79865?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9f4f9834da0e115758918f80f93264c8c487ec5 Gerrit-Change-Number: 79865 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: cpu/x86: Support runtime page tables on APs
by Benjamin Doron (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Jérémy Compostella. Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79864?usp=email ) Change subject: cpu/x86: Support runtime page tables on APs ...................................................................... cpu/x86: Support runtime page tables on APs APs should use the same page table as the BSP. Change-Id: I61aa44e5301aab7a4c127d58a7caf815d3a7d74d Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/sipi_vector.S 2 files changed, 6 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/79864/1 diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index d3af6ecc..bcf8205 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -7,6 +7,7 @@ #include <cpu/cpu.h> #include <cpu/intel/microcode.h> #include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> #include <cpu/x86/gdt.h> #include <cpu/x86/lapic.h> #include <cpu/x86/name.h> @@ -99,6 +100,7 @@ uint32_t msr_count; uint32_t c_handler; atomic_t ap_count; + uint32_t ap_page_tables; } __packed; /* This also needs to match the assembly code for saved MSR encoding. */ @@ -231,6 +233,7 @@ sp->per_cpu_segment_selector = per_cpu_segment_selector; sp->stack_size = CONFIG_AP_STACK_SIZE; sp->stack_top = (uintptr_t)ap_stack + ARRAY_SIZE(ap_stack); + sp->ap_page_tables = (uint32_t)read_cr3(); } static const unsigned int fixed_mtrrs[NUM_FIXED_MTRRS] = { diff --git a/src/cpu/x86/sipi_vector.S b/src/cpu/x86/sipi_vector.S index 401e8e2..57f37ec 100644 --- a/src/cpu/x86/sipi_vector.S +++ b/src/cpu/x86/sipi_vector.S @@ -39,6 +39,8 @@ .long 0 ap_count: .long 0 +ap_page_tables: +.long 0 #define CR0_CLEAR_FLAGS_CACHE_ENABLE (CR0_CD | CR0_NW) #define CR0_SET_FLAGS (CR0_CLEAR_FLAGS_CACHE_ENABLE | CR0_PE) @@ -223,7 +225,7 @@ #if ENV_X86_64 /* Get page table address */ - movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax + movl ap_page_tables, %eax /* entry64.inc preserves ebx, esi, edi, ebp */ #include <cpu/x86/64bit/entry64.inc> -- To view, visit https://review.coreboot.org/c/coreboot/+/79864?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I61aa44e5301aab7a4c127d58a7caf815d3a7d74d Gerrit-Change-Number: 79864 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: [DNM] cpu/x86/64bit/mode_switch2.S: Support runtime page tables
by Benjamin Doron (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Jérémy Compostella. Benjamin Doron has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79863?usp=email ) Change subject: [DNM] cpu/x86/64bit/mode_switch2.S: Support runtime page tables ...................................................................... [DNM] cpu/x86/64bit/mode_switch2.S: Support runtime page tables Try to get page table address from the `page_tables` variable in mmu.c. Fallback to hardcoded page tables in ROM. Untested. Change-Id: Ic964038fd4dd810015e6a355a171e49db648c8fe Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/cpu/x86/64bit/mode_switch2.S 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/79863/1 diff --git a/src/cpu/x86/64bit/mode_switch2.S b/src/cpu/x86/64bit/mode_switch2.S index cbd98a0..7376275 100644 --- a/src/cpu/x86/64bit/mode_switch2.S +++ b/src/cpu/x86/64bit/mode_switch2.S @@ -19,8 +19,12 @@ mov %esp, %ebp /* Get page table address */ + movl page_tables, %eax + cmp %eax, 0 + jne 1f movl $(CONFIG_ARCH_X86_64_PGTBL_LOC), %eax +1: /* Enter long mode, preserves ebx */ #include <cpu/x86/64bit/entry64.inc> -- To view, visit https://review.coreboot.org/c/coreboot/+/79863?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic964038fd4dd810015e6a355a171e49db648c8fe Gerrit-Change-Number: 79863 Gerrit-PatchSet: 1 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: arch/x86/mmu: Port armv8 MMU to x86_64
by Benjamin Doron (Code Review) 09 Jan '24

09 Jan '24

Attention is currently required from: Benjamin Doron. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79161?usp=email to look at the new patch set (#5). Change subject: arch/x86/mmu: Port armv8 MMU to x86_64 ...................................................................... arch/x86/mmu: Port armv8 MMU to x86_64 Add functions to set up page tables for long mode. In addition generate new page tables where necessary: - before CBMEM setup, if CBMEM is above 4GiB - after CBMEM setup, if CBMEM is above 4GiB - at end of BS_DEV_RESOURCES in CBMEM At end of BS_DEV_RESOURCES the memory map is fully known and the page tables can be properly generated based on the memory resources. This allows the CPU to access all DRAM and MMIO even beyond 4GiB. Right now there's no use case for this, but the code is necessary to: - Load stages above 4GiB - Load payloads above 4GiB - Install tables (like CBMEM/ACPI/SMBIOS) above 4GiB - allow coreboot PCI drivers to access BARs mapped above 4GiB Tested on prodrive/hermes: Still boots to payload. Doesn't affect existing x86_32 code. Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Co-authored-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/arch/x86/Kconfig M src/arch/x86/Makefile.inc A src/arch/x86/include/arch/mmu.h A src/arch/x86/mmu-ramstage.c A src/arch/x86/mmu-romstage.c A src/arch/x86/mmu.c M src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h M src/lib/imd_cbmem.c 8 files changed, 631 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79161/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79161?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6e8b46e65925823a84b8ccd647c7d6848aa20992 Gerrit-Change-Number: 79161 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-MessageType: newpatchset

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