coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Enable PIXA touchpad
by Ian Feng (Code Review) 10 Jan '24

10 Jan '24

Ian Feng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79872?usp=email ) Change subject: mb/google/nissa/var/craaskov: Enable PIXA touchpad ...................................................................... mb/google/nissa/var/craaskov: Enable PIXA touchpad Add PIXA touchpad for variants of craaskov. BUG=b:289962540 TEST=build craaskov firmware and test with PIXA touchpad Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craaskov/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/79872/1 diff --git a/src/mainboard/google/brya/variants/craaskov/overridetree.cb b/src/mainboard/google/brya/variants/craaskov/overridetree.cb index c9299de..cc4ce53 100644 --- a/src/mainboard/google/brya/variants/craaskov/overridetree.cb +++ b/src/mainboard/google/brya/variants/craaskov/overridetree.cb @@ -284,6 +284,15 @@ register "hid_desc_reg_offset" = "0x20" device i2c 2c on end end + chip drivers/i2c/hid + register "generic.hid" = ""PIXA2303"" + register "generic.desc" = ""PIXA Touchpad"" + register "generic.irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F14_IRQ)" + register "generic.wake" = "GPE0_DW2_14" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x20" + device i2c 0x68 on end + end end device ref pcie_rp7 off end device ref emmc on end -- To view, visit https://review.coreboot.org/c/coreboot/+/79872?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iccf19b275548f44aec00be8631590b8a7ad1aa23 Gerrit-Change-Number: 79872 Gerrit-PatchSet: 1 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part
by Kevin Yang (Code Review) 10 Jan '24

10 Jan '24

Kevin Yang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79887?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/79887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Gerrit-Change-Number: 79887 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 02:19:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
by Eric Lai (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Jianeng Ceng, Nick Vaccaro, Subrata Banik, Weimin Wu. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79858?usp=email ) Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/anraggar/variant.c: https://review.coreboot.org/c/coreboot/+/79858/comment/b831ff6c_b4c0fc76 : PS3, Line 9: if (fw_config_probe(FW_CONFIG(WIFI, WIFI_6E))) { please use get_wifi_sar_fw_config_filename -- To view, visit https://review.coreboot.org/c/coreboot/+/79858?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4 Gerrit-Change-Number: 79858 Gerrit-PatchSet: 3 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 02:03:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT config
by Eric Lai (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Shelley Chen, Subrata Banik, Tarun. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79860?usp=email ) Change subject: mb/google/rex: Remove redundant HAVE_FSP_LOGO_SUPPORT config ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79860?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I89bdd54cb73b11f74db2927a5eb86ab826c60517 Gerrit-Change-Number: 79860 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 02:00:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Enable FSP logo support by default
by Eric Lai (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Kapil Porwal, Shelley Chen, Subrata Banik, Tarun. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79859?usp=email ) Change subject: soc/intel/meteorlake: Enable FSP logo support by default ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79859?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b Gerrit-Change-Number: 79859 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 01:59:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part
by Kevin Yang (Code Review) 10 Jan '24

10 Jan '24

Kevin Yang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79887?usp=email ) Change subject: mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part ...................................................................... mb/google/dedede/var/beadrix: Generate SPD ID for supported memory part Add beadrix supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. CXMT CXDB4CBAM-ML-A BUG=b:278983561 TEST=Use part_id_gen to generate related settings Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Signed-off-by: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc M src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt M src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/79887/1 diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc index f77c501..d260b55 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc +++ b/src/mainboard/google/dedede/variants/beadrix/memory/Makefile.inc @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt SPD_SOURCES = SPD_SOURCES += spd/lp4x/set-1/spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D1NP-046 WT:B, K4U6E3S4AA-MGCR, H54G46CYRBX267 +SPD_SOURCES += spd/lp4x/set-1/spd-11.hex # ID = 1(0b0001) Parts = CXDB4CBAM-ML-A diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt index 36ca69b..ddbed1a 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/dram_id.generated.txt @@ -1,9 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! # Generated by: -# util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +# ./util/spd_tools/bin/part_id_gen JSL lp4x src/mainboard/google/dedede/variants/beadrix/memory/ src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt DRAM Part Name ID to assign MT53E512M32D1NP-046 WT:B 0 (0000) K4U6E3S4AA-MGCR 0 (0000) H54G46CYRBX267 0 (0000) +CXDB4CBAM-ML-A 1 (0001) diff --git a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt index 31df0df..2aa2814 100644 --- a/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt +++ b/src/mainboard/google/dedede/variants/beadrix/memory/mem_parts_used.txt @@ -12,3 +12,4 @@ MT53E512M32D1NP-046 WT:B K4U6E3S4AA-MGCR H54G46CYRBX267 +CXDB4CBAM-ML-A -- To view, visit https://review.coreboot.org/c/coreboot/+/79887?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3a6925395b52dc7aa5c0f93b8820099369db4dbf Gerrit-Change-Number: 79887 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Yang <kevin.yang(a)ecs.corp-partner.google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/brox: Switch EC INT and WAKE GPIOs
by Shelley Chen (Code Review) 10 Jan '24

10 Jan '24

Shelley Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79886?usp=email ) Change subject: mb/google/brox: Switch EC INT and WAKE GPIOs ...................................................................... mb/google/brox: Switch EC INT and WAKE GPIOs There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h 2 files changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79886/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Gerrit-Change-Number: 79886 Gerrit-PatchSet: 2 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: Switch EC INT and WAKE GPIOs
by Shelley Chen (Code Review) 10 Jan '24

10 Jan '24

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79886?usp=email ) Change subject: mb/google/brox: Switch EC INT and WAKE GPIOs ...................................................................... mb/google/brox: Switch EC INT and WAKE GPIOs There was a mistake in the gpio spreadsheet provided by the HW team and the GPIO assignments for the EC INT and WAKE signals got switched from what it was in the schematics. The correct assignments are: GPP_D0 = EC_PCH_INT_ODL GPP_D1 = EC_PCH_WAKE_ODL BUG=b:311450057,b:300690448 BRANCH=None TEST=emerge-brox coreboot Will try to boot OS image on device and see if there are any ec errors. Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c M src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h 2 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/79886/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 5c4f613..da70da1 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -139,10 +139,10 @@ /* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */ PAD_NC(GPP_C7, NONE), - /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_WAKE_ODL */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D0, NONE, DEEP, EDGE_SINGLE, INVERT), - /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_INT_ODL */ - PAD_CFG_GPI_INT(GPP_D1, NONE, PLTRST, LEVEL), + /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ + PAD_CFG_GPI_INT(GPP_D0, NONE, PLTRST, LEVEL), + /* GPP_D1 : [NF1: ISH_GP1 NF2: BK1 NF5: SBK1 NF6: USB_C_GPP_D1] ==> PCH_EC_PCH_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D1, NONE, DEEP, EDGE_SINGLE, INVERT), /* GPP_D2 : [NF1: ISH_GP2 NF2: BK2 NF5: SBK2 NF6: USB_C_GPP_D2] ==> ISH_ACCEL_DB_INT_L (NC) */ PAD_NC(GPP_D2, NONE), /* GPP_D3 : [NF1: ISH_GP3 NF2: BK3 NF5: SBK3 NF6: USB_C_GPP_D3] ==> ISH_ACCEL_MB_INT_L (NC) */ diff --git a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h index 54321e5..25226bc 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h +++ b/src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h @@ -8,8 +8,8 @@ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -/* EC wake is EC_PCH_INT which is routed to GPP_D1 pin */ -#define GPE_EC_WAKE GPE0_DW1_01 +/* EC wake is EC_PCH_INT which is routed to GPP_D0 pin */ +#define GPE_EC_WAKE GPE0_DW1_00 /* WP signal to PCH */ #define GPIO_PCH_WP GPP_E8 /* Used to gate SoC's SLP_S0# signal */ -- To view, visit https://review.coreboot.org/c/coreboot/+/79886?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I02057aeb5d82218dbbe4c939d4feb87a4d3da678 Gerrit-Change-Number: 79886 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Makefile.inc: Enable Wold-style-declaration command option
by Felix Singer (Code Review) 09 Jan '24

09 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71892?usp=email ) Change subject: Makefile.inc: Enable Wold-style-declaration command option ...................................................................... Makefile.inc: Enable Wold-style-declaration command option Warn for obsolescent usages, according to the C Standard, in a declaration. For example, warn if storage-class specifiers like static are not the first things in a declaration. Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71892 Reviewed-by: Martin L Roth <gaumless(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M Makefile.inc 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/Makefile.inc b/Makefile.inc index 44cd0ea..23f56a4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -498,6 +498,7 @@ CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -fstrict-aliasing -ffunction-sections -fdata-sections -fno-pie ifeq ($(CONFIG_COMPILER_GCC),y) +CFLAGS_common += -Wold-style-declaration # Don't add these GCC specific flags when running scan-build ifeq ($(CCC_ANALYZER_OUTPUT_FORMAT),) CFLAGS_common += -Wno-packed-not-aligned -- To view, visit https://review.coreboot.org/c/coreboot/+/71892?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida3fa59edb07e4105ef3cfb6a20cb29680699586 Gerrit-Change-Number: 71892 Gerrit-PatchSet: 14 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/nvidia: Put static keyword at the beginning of declarations
by Felix Singer (Code Review) 09 Jan '24

09 Jan '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79856?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/nvidia: Put static keyword at the beginning of declarations ...................................................................... soc/nvidia: Put static keyword at the beginning of declarations In order to comply with the more recent style of declarations, put the static keyword at the beginning. Fixes following GCC error when the related flag is set: error: 'static' is not at beginning of declaration [-Werror=old-style-declaration] Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79856 Reviewed-by: Julius Werner <jwerner(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/nvidia/tegra124/clock.c M src/soc/nvidia/tegra210/clock.c 2 files changed, 6 insertions(+), 6 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Julius Werner: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/nvidia/tegra124/clock.c b/src/soc/nvidia/tegra124/clock.c index f8a232f..0dae02d 100644 --- a/src/soc/nvidia/tegra124/clock.c +++ b/src/soc/nvidia/tegra124/clock.c @@ -80,7 +80,7 @@ * PLLU: 1 MHz < CF < 6 MHz, 480 MHz < VCO < 960 MHz * PLLDP: 12 MHz < CF < 38 MHz, 600 MHz < VCO < 1200 MHz * (values taken from Linux' drivers/clk/tegra/clk-tegra124.c). */ -struct { +static const struct { int khz; struct pllcx_dividers pllx; /* target: CONFIG_PLLX_KHZ */ struct pllcx_dividers pllc; /* target: 600 MHz */ @@ -89,7 +89,7 @@ struct pllu_dividers pllu; /* target; 960 MHz */ struct pllcx_dividers plldp; /* target; 270 MHz */ /* PLLDP treats p differently (OUT = VCO / (p + 1) for p < 6). */ -} static const osc_table[16] = { +} osc_table[16] = { [OSC_FREQ_12] = { .khz = 12000, .pllx = {.n = TEGRA_PLLX_KHZ / 12000, .m = 1, .p = 0}, diff --git a/src/soc/nvidia/tegra210/clock.c b/src/soc/nvidia/tegra210/clock.c index 95507e3..4433d7e 100644 --- a/src/soc/nvidia/tegra210/clock.c +++ b/src/soc/nvidia/tegra210/clock.c @@ -27,7 +27,7 @@ PLL_MAX_INDEX, }; -struct pll_reg_info { +static const struct pll_reg_info { u32 *base_reg; u32 *lock_enb_reg; u32 lock_enb_val; @@ -40,7 +40,7 @@ u32 kcp_shift:5; /* kcp bits location */ u32 kvco_shift:5; /* kvco bit location */ u32 rsvd:7; -} static const pll_reg_table[] = { +} pll_reg_table[] = { [PLLX_INDEX] = { .base_reg = CLK_RST_REG(pllx_base), .lock_enb_reg = CLK_RST_REG(pllx_misc), .lock_enb_val = PLLPAXS_MISC_LOCK_ENABLE, @@ -127,10 +127,10 @@ * PLLM is set up dynamically by clock_sdram(). * PLLP is hardwired to 408 MHz in HW (unless we set BASE_OVRD). */ -struct { +static struct { int khz; struct pll_fields plls[PLL_MAX_INDEX]; -} static osc_table[16] = { +} osc_table[16] = { [OSC_FREQ_12] = { .khz = 12000, .plls = { -- To view, visit https://review.coreboot.org/c/coreboot/+/79856?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida683319f7a0c428a9e4808821075abdd9fcb504 Gerrit-Change-Number: 79856 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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