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Change subject: [DNM] treewide: Prepare mode switch code for dynamically generated paging
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79226/comment/b54aef0d_6b136232 :
PS2, Line 23: Untested.
Need to test the mode switch code in particular.
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Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79853?usp=email )
Change subject: 3rdparty/vboot: Update submodule to upstream main
......................................................................
3rdparty/vboot: Update submodule to upstream main
Updating from commit id 7c3b60bb:
2023-12-21 20:34:49 +0000 - (firmware/2lib: Use SSE2 to speed-up Montgomery multiplication)
to commit id 32402941:
2024-01-08 19:53:43 +0000 - (treewide: Put the static keyword at the beginning of declarations)
This brings in 4 new commits:
32402941 treewide: Put the static keyword at the beginning of declarations
242d198b crossystem: Use external tool the clear the TPM
c8a0802f tests: Remove unnecessary vb2_verify_fw.c from TEST20_NAMES list
706088b8 tests: Test HW crypto RSA signature verification
Change-Id: I667376dfc3021fa6d213e3d89917ee228fd14a28
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79853
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Julius Werner <jwerner(a)chromium.org>
---
M 3rdparty/vboot
1 file changed, 1 insertion(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Julius Werner: Looks good to me, approved
diff --git a/3rdparty/vboot b/3rdparty/vboot
index 7c3b60b..3240294 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit 7c3b60bb667f917525b5472f6a34df6402d7fa58
+Subproject commit 32402941c0afdb5bf50d6e3c11548ecb1ac80544
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Change subject: cpu/x86/smm/smm_module_handler.c: Implement MP in SMM
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
It might be better to split cpu/x86/mp_init.c into a common file and stage-specific helpers.
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Change subject: mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS1:
> i'll have a look at it, but that sounds like the better solution to me
had a look at the stoney binarypi source and ran a test; setting FchParams->LegacyFree to 0 is the much better approach
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I'd like you to reexamine a change. Please visit
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Change subject: mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
......................................................................
mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
Tell binaryPI to not disable the LPC decodes for the IO ports used by
the serial ports on the Super I/O chip during the AmdInitReset binaryPI
entry point. Checked the Stoneyridge binaryPI source code which is
closely enough related to be reasonable sure that this option only
controls which LPC decode bits get cleared and won't have any other side
effects.
TEST=Now the full console output from the APU2 board gets printed on the
serial console.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Suggested-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
Change-Id: I91ef4423bd7bf6c1d7a175336f0f89479f2cde02
---
M src/mainboard/pcengines/apu2/BiosCallOuts.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/79852/3
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Change subject: drivers,nb/amd/*/state_machine: add platform_AfterInitReset
......................................................................
Abandoned
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Change subject: mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
......................................................................
mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
Tell binaryPI to not disable the LPC decodes for the IO ports used by
the serial ports on the Super I/O chip during the AmdInitReset binaryPI
entry point. Checked the Stoneyridge binaryPI source code which is
closely enough related to be reasonable sure that this option only
controls which LPC decode bits get cleared and won't have any other side
effects.
TEST=Now the full console output from the APU2 board gets printed on the
serial console.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I91ef4423bd7bf6c1d7a175336f0f89479f2cde02
---
M src/mainboard/pcengines/apu2/BiosCallOuts.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/79852/2
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Change subject: mb/emulation/qemu-{i440fx,q35}: Don't report ROM page tables as resource
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/79228/comment/f67e15f4_3f3270e6 :
PS1, Line 11:
> Is there any difference in the log messages?
I don't understand the point of the question. I'd assume so, but that doesn't change the intention of this patch.
If we're going since the start of this patch train, then, for a 64-bit build, CB:79161 will now log about physical memory that's backed by the page table.
If we're just considering this patch, then again, yes. The resource allocation code will no longer log about this resource. Being within ROM, the avoid_fixed_resources() code probably already had to avoid this region, so I don't know what the difference in logs *is*, but I don't think it matters at all anyways. (this is also only for 64-bit builds, per the `CONFIG()` macro in the code)
The intention here is that we no longer need to use *ROM* page tables once we have dynamically-generated *RAM* page tables, so, no need to advertise in ramstage that this is anything usable. By now, it's just some data that we happened to use before. Is this the confusion? I can add some of this paragraph to the commit message.
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Hello Fred Reitberger, Jason Glenesk, Matt DeVillier,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/amd/common/acpi: factor out common MADT code
......................................................................
soc/amd/common/acpi: factor out common MADT code
The acpi_fill_madt implementation from the Genoa PoC also works for the
other AMD SoCs that select SOC_AMD_COMMON_BLOCK_DATA_FABRIC_DOMAIN, so
factor out this function to the common AMD ACPI code and change those
other SoCs to use the new common functionality instead of having their
own implementations.
The old code on the single-domain SoCs used the GNB_IO_APIC_ADDR base
address to create the MADT entry for the additional IOAPIC in the root
complex. The new code iterates over all domains and looks for a resource
with the IOMMU_IOAPIC_IDX index in each domain and if it finds it, it
creates an MADT entry for that IOAPIC. This resource is created earlier
in the boot process when the non-PCI resources are read from the IOHC
registers and reported to the allocator.
TEST=The resulting MADT doesn't change on Mandolin
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I4cc0d3f30b4e6ba29542dcfde84ccac90820d258
---
M src/soc/amd/cezanne/Kconfig
M src/soc/amd/cezanne/acpi.c
M src/soc/amd/common/block/acpi/Kconfig
M src/soc/amd/common/block/acpi/Makefile.inc
A src/soc/amd/common/block/acpi/madt.c
M src/soc/amd/genoa_poc/Kconfig
M src/soc/amd/genoa_poc/acpi.c
M src/soc/amd/glinda/Kconfig
M src/soc/amd/glinda/acpi.c
M src/soc/amd/mendocino/Kconfig
M src/soc/amd/mendocino/acpi.c
M src/soc/amd/phoenix/Kconfig
M src/soc/amd/phoenix/acpi.c
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/acpi.c
15 files changed, 33 insertions(+), 58 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/79861/2
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Change subject: arch/x86/c_start.S: Add proper x86_64 code
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/59874/comment/ca76ea71_422121b1 :
PS2, Line 7: src/
> Could be removed.
Done
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