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Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
Patch Set 16: Code-Review+1
(2 comments)
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/78331/comment/4b022842_097fc5ff :
PS16, Line 1012: config RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G
I think this deserves a more positive naming. e.g. `ALWAYS_ALLOW_ABOVE_4G_ALLOCATION`.
https://review.coreboot.org/c/coreboot/+/78331/comment/61cf422e_0f44870a :
PS16, Line 1019: 32bit mode
Technically the incompatible mode is "flat protected mode", or we could
say "without paging". We do have some PAE code in coreboot, IIRC. So it's
actually possible to access above 4G.
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Change subject: soc/intel/xeon_sp: Allocate resources above 4G
......................................................................
Patch Set 10: Code-Review+1
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Hello Eric Lai, Nick Vaccaro, Subrata Banik, Weimin Wu,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/79858?usp=email
to look at the new patch set (#3).
Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
......................................................................
mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
1.In contrast to the MediaTek Wi-Fi module, the Intel Wi-Fi module needs
to load a SAR table.
2.Describe the FW_CONFIG probe for the settings.
- WIFI_6 for MTK Wi-Fi module MT7921L
- WIFI_6E for Intel Wi-Fi module AX211NGW
BUG=b:315418153
TEST=emerge-nissa coreboot
Change-Id: I37e8adc3de02707b2df541cc5e6f88083554eeb4
Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/variant.c
2 files changed, 17 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/79858/3
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
> Tested and revised for ArcherCity CRB (SPR-XCC) […]
Thanks for the testing! It's really nice to know that we finally have a
fully working version :)
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
Patch Set 17:
(8 comments)
Patchset:
PS17:
Hi Shuo, thanks for the update. I hope you enjoyed your holidays.
File src/soc/intel/xeon_sp/include/soc/chip_common.h:
https://review.coreboot.org/c/coreboot/+/78327/comment/e9500103_d638c109 :
PS17, Line 12: void soc_create_ioat_domains(struct bus * const bus, const STACK_RES * const sr);
No space after the asterisk, please. And the added `const` is not part of the
type (so it's meaningless to the caller and doesn't add information here).
(Where a const is placed is a subtle difference in syntax but a big difference
semantically. When it's about data pointed to, like in `const STACK_RES *`, it
becomes part of the type. When it's placed directly before the parameter name,
it applies to the variable in the function's body. The latter is meaningless
in a forward declaration and the compiler actually must ignore it.)
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/a69c4503_9c093b1d :
PS14, Line 75: if (sr->BusLimit - sr->BusBase + 1 < HQM1_BUS_OFFSET + HQM_RESERVED_BUS) {
I believe we still should check
```
if (sr->BusLimit - sr->BusBase + 1 < HQM_BUS_OFFSET + 1 + HQM_RESERVED_BUS)
```
for the non-optional parts.
File src/soc/intel/xeon_sp/spr/ioat.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/49743a05_09554929 :
PS17, Line 50: bus->max_subordinate = bus_limit;
> each domain will own 2 busses instead of 1.
Ack.
Thanks, I missed that the ACPI code does an implicit `1 + *_RESERVED_BUS`.
https://review.coreboot.org/c/coreboot/+/78327/comment/8b97c53a_096fa225 :
PS17, Line 92: assert(bus_limit <= sr->BusLimit)
We are dealing with input from another program, hence using assert()
seems wrong (note that the default setting for assertions is weak in coreboot,
so coreboot would continue with invalid hardware configuration).
https://review.coreboot.org/c/coreboot/+/78327/comment/d3aaec21_4b148d8a :
PS17, Line 95: CPM1
This is HQM.
https://review.coreboot.org/c/coreboot/+/78327/comment/456300cb_8c127a26 :
PS17, Line 109: create_ioat_domain(bus, domain_base, bus_base, bus_limit, 0, -1, mem64_base, mem64_limit);
> Make CPM1 and HQM1 optional on 3 accelerator SKUs where smaller bus range is provided. P.S. […]
Acknowledged
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/78327/comment/b9a88af2_7a389c7e :
PS17, Line 254:
> to review
Doesn't `stack_enabled` cover this? Looking at the code below it seems to me
that it was explicitly written such that we always have the device nodes in
the DSDT, even if they are not active.
I would prefer to discuss this in a separate patch.
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Change subject: mb/google/nissa/var/anraggar: add FW config to apply the wifi sar
......................................................................
Patch Set 2:
This change is ready for review.
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Change subject: soc/intel/meteorlake: Enable FSP logo support by default
......................................................................
Patch Set 1: Code-Review+1
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Change subject: soc/intel/meteorlake: Enable FSP logo support by default
......................................................................
soc/intel/meteorlake: Enable FSP logo support by default
Enables FSP logo support for Meteor Lake SoC config, covering
both Intel Meteor Lake RVP and ChromeOS devices.
Applies HAVE_FSP_LOGO_SUPPORT configuration only for platforms
with native FSP support.
Ensures successful builds and boots for google/rex and intel/mtlrvp.
BRANCH=firmware-rex-15709.B
TEST=Able to build and boot google/rex and intel/mtlrvp
Change-Id: Ic99bfdc2d33db48bdb015525981c1ef76df8203b
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/79859/1
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 5b78fdf..b5d2a9f 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -23,6 +23,7 @@
select GENERIC_GPIO_LIB
select HAVE_DEBUG_RAM_SETUP
select HAVE_FSP_GOP
+ select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP
select HAVE_HYPERTHREADING
select HAVE_INTEL_COMPLIANCE_TEST_MODE
select HAVE_SMI_HANDLER
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