Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Reka Norman, Tyler Wang, Peter Ou.
Vidya Gopalakrishnan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 )
Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71860/comment/e6e8dcdd_8f4fed4b
PS4, Line 231: probe THERMAL_SOLUTION THERMAL_SOLUTION_15W
Is Crassneto a fan based device? If so it will need the active policy table as well.
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Attention is currently required from: Jason Nien, Martin Roth.
Hello Jason Nien, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72694
to look at the new patch set (#2).
Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
......................................................................
mb/google/skyrim/var/frostflow: Override SPI flash bus speed
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version of the current phase.
BUG=b:260127676
TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed.
Observe that the boot time improved by 100 ms compared to 66 MHz SPI
flash bus speed.
firmware log:
SPI fast read speed: 100 MHz
At 66 MHz:
Total Time: 1,563,384
At 100 MHz:
Total Time: 1,462,570
Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
---
M src/mainboard/google/skyrim/Kconfig
1 file changed, 26 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/72694/2
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Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71965 )
Change subject: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
......................................................................
Patch Set 10:
(1 comment)
File src/soc/intel/xeon_sp/chip_common.c:
https://review.coreboot.org/c/coreboot/+/71965/comment/2b418aa6_2882e9de
PS2, Line 495: attach_iio_stacks
> Johnny, thanks for the validation. […]
I submitted patchset 10 for this. BTW the below lint errors need to be fixed in CB:72439.
I think SOC_INTEL_PCIE_64BIT_ALLOC and SOC_INTEL_HAS_BIOS_DONE_MSR should be moved from xeon_sp/spr/Kconfig to the common xeon_sp/Kconfig?
Check Kconfig files for errors (lint-stable-008-kconfig): #!!!!! Error: CONFIG() used on unknown value (SOC_INTEL_PCIE_64BIT_ALLOC) at src/soc/intel/xeon_sp/chip_common.c:410.
#!!!!! Error: CONFIG() used on unknown value (SOC_INTEL_HAS_BIOS_DONE_MSR) at src/soc/intel/xeon_sp/finalize.c:89.
# 2 errors
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Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72694 )
Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
......................................................................
mb/google/skyrim/var/frostflow: Override SPI flash bus speed
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version of the current phase.
BUG=b:260127676
TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed.
Observe that the boot time improved by 100 ms compared to 66 MHz SPI
flash bus speed.
firmware log:
SPI fast read speed: 100 MHz
At 66 MHz:
Total Time: 1,563,384
At 100 MHz:
Total Time: 1,462,570
Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09
Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com>
---
M src/mainboard/google/skyrim/Kconfig
1 file changed, 27 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/72694/1
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index d945474..55b6ece 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -157,6 +157,7 @@
config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD
hex
default 0x5 if BOARD_GOOGLE_SKYRIM
+ default 0x1 if BOARD_GOOGLE_FROSTFLOW
default 0xffffffff
help
Minimum board version starting which the Override EFS SPI Speed
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Attention is currently required from: Simon Chou, Johnny Lin, Christian Walter, Arthur Heymans.
Johnny Lin has uploaded a new patch set (#10) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71965 )
Change subject: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
......................................................................
soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
For some Xeon-SP (such as SPR-SP), more buses should be probed.
Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
---
M src/soc/intel/xeon_sp/chip_common.c
1 file changed, 57 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/71965/10
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Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik, Tim Wawrzynczak, Kane Chen.
Bora Guvendik has uploaded a new patch set (#4) to the change originally created by Selma Bensaid. ( https://review.coreboot.org/c/coreboot/+/68636 )
Change subject: mb/google/brya,skolas: disable Tccold Handshake
......................................................................
mb/google/brya,skolas: disable Tccold Handshake
The patch disables Tccold Handshake to prevent possible display
flicker issue for skolas board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Verify the build for skolas board
Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com>
Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/skolas/overridetree.cb
M src/mainboard/google/brya/variants/skolas4es/overridetree.cb
3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/68636/4
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Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
......................................................................
soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
This commit provides a dev tree setting for partners to enable/disable
TccoldHandshake for the sighting in doc:723158
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=compile ok and FSP UPD is config properly
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/68635/6
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