coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings
by Vidya Gopalakrishnan (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Reka Norman, Sumeet R Pawnikar, Tyler Wang, Peter Ou. Vidya Gopalakrishnan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 ) Change subject: mb/google/nissa/var/craask: Modify DPTF settings ...................................................................... Patch Set 5: Code-Review+1 (1 comment) Patchset: PS5: Looks good to me -- To view, visit https://review.coreboot.org/c/coreboot/+/71860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Gerrit-Change-Number: 71860 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 08:20:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings
by Paul Menzel (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Reka Norman, Vidya Gopalakrishnan, Sumeet R Pawnikar, Tyler Wang, Peter Ou. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 ) Change subject: mb/google/nissa/var/craask: Modify DPTF settings ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71860/comment/cf442333_7e583977 PS5, Line 9: Craasneto Shouldn’t that be mentioned in the prefix? https://review.coreboot.org/c/coreboot/+/71860/comment/cae7c824_b5edc1bb PS5, Line 9: Limit(PL) Please add a space before the (. https://review.coreboot.org/c/coreboot/+/71860/comment/c6c98859_61eaf879 PS5, Line 9: Add ADL-N 15W CPU Power Limit(PL) settings for Craasneto Where did you get the new information from? File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71860/comment/16b13595_34db7951 PS5, Line 25: option THERMAL_SOLUTION_15W 1 Where is that field defined or used? I am not finding it in the current source code of origin/master (commit b63eb4d172 (crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7)). -- To view, visit https://review.coreboot.org/c/coreboot/+/71860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Gerrit-Change-Number: 71860 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 08:19:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface for mtlrvp
by Harsha B R (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jamie Ryu. Hello Jamie Ryu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72706 to review the following change. Change subject: mb/intel/mtlrvp: Enable GSPI interface for mtlrvp ...................................................................... mb/intel/mtlrvp: Enable GSPI interface for mtlrvp This patch enables GSPI[1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to chromeOS. SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72706/1 diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8cdbeea..15c9557 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -36,6 +36,21 @@ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + }" + + register "serial_io_gspi_cs_mode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + + register "serial_io_gspi_cs_state" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + }" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -71,6 +86,7 @@ device ref i2c5 on end device ref shared_sram on end device ref uart0 on end + device ref gspi1 on end device ref smbus on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Gerrit-Change-Number: 72706 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings
by Ren Kuo (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Reka Norman, Vidya Gopalakrishnan, Sumeet R Pawnikar, Tyler Wang, Peter Ou. Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 ) Change subject: mb/google/nissa/var/craask: Modify DPTF settings ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71860/comment/e9b66a80_c76d15c5 PS4, Line 231: probe THERMAL_SOLUTION THERMAL_SOLUTION_15W > Is Crassneto a fan based device? If so it will need the active policy table as well. updated form thermal team's suggestion. -- To view, visit https://review.coreboot.org/c/coreboot/+/71860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Gerrit-Change-Number: 71860 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 08:05:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings
by Ren Kuo (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Reka Norman, Sumeet R Pawnikar, Tyler Wang, Peter Ou. Hello build bot (Jenkins), David Wu, Tarun Tuli, Kangheui Won, Reka Norman, Sumeet R Pawnikar, Vidya Gopalakrishnan, Tyler Wang, Peter Ou, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71860 to look at the new patch set (#5). Change subject: mb/google/nissa/var/craask: Modify DPTF settings ...................................................................... mb/google/nissa/var/craask: Modify DPTF settings Add ADL-N 15W CPU Power Limit(PL) settings for Craasneto BUG=b:265101768 TEST=emerge-nissa coreboot Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/craask/overridetree.cb 1 file changed, 92 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/71860/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/71860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Gerrit-Change-Number: 71860 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Reka Norman <rekanorman(a)chromium.org> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

1 0

[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/b9d9a33b_65a3f63a PS2, Line 9: Intel ArcherCity CRB is a dual socket CRB with Intel : Sapphire Rapids Scalable Processor chipset. The chipset : also includes EmmitsBurg PCH. > You cite an example, which is about the source code files, and not the commit message. […] Understood. Thanks for providing the information. -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 07:25:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Chou <simonchou(a)supermicro.com.tw> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel/xeon_sp/uncore.c: Support SPR-SP
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Simon Chou has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/71961 ) Change subject: soc/intel/xeon_sp/uncore.c: Support SPR-SP ...................................................................... Abandoned Obsoleted by [CB:72614], [CB:72615], [CB:72616], [CB:72617] -- To view, visit https://review.coreboot.org/c/coreboot/+/71961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d2acc1fe89bfb4486bec4f1e6488ad2d649a099 Gerrit-Change-Number: 71961 Gerrit-PatchSet: 6 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: abandon

1 0

[M] Change in coreboot[master]: soc/intel: Use common codeflow for MP init
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Nico Huber, Sean Rhodes, Tarun Tuli, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Lean Sheng Tan, Werner Zeh, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72604 ) Change subject: soc/intel: Use common codeflow for MP init ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/xeon_sp/cpx/cpu.c: https://review.coreboot.org/c/coreboot/+/72604/comment/bf8de427_81e8d5e9 PS2, Line 224: dev->link_list > Looks like this was broken like APL? If so, please mention that in the > commit message. :) Done. -- To view, visit https://review.coreboot.org/c/coreboot/+/72604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Gerrit-Change-Number: 72604 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 07:21:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: soc/intel: Use common codeflow for MP init
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Nico Huber, Sean Rhodes, Tarun Tuli, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Lean Sheng Tan, Werner Zeh, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72604 ) Change subject: soc/intel: Use common codeflow for MP init ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/apollolake/cpu.c: https://review.coreboot.org/c/coreboot/+/72604/comment/54c07b3d_d02e9546 PS2, Line 267: if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) : return; > > This seems to be here because APL and GLK use different paths. > > `cpu_bus_ops->init` used to bail out here on GLK (because the > > common code handled it). But now common code would indirectly > > call this function... > > > > I think we are in trouble here, because of the singleton global > > `mp_init_cpus` symbol. (soc/ code seems to be full of such single- > > tons... not sure if that's a good path to follow) > > > > If I understand things correctly, one way out of it would be > > to avoid the `.init` for GLK, or have a function there that > > calls mp_cpus_bus_init() conditionally. (Or figure out why APL > > still doesn't use common code, ofc.) > > I think APL did not need MP init to happen before calling FSP-S Done. Hooked up cpu ops in devicetree and used different ops for apl and glk -- To view, visit https://review.coreboot.org/c/coreboot/+/72604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Gerrit-Change-Number: 72604 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 07:21:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/apl: Hook up cpu ops in devicetree
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Sean Rhodes. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72705 ) Change subject: soc/intel/apl: Hook up cpu ops in devicetree ...................................................................... soc/intel/apl: Hook up cpu ops in devicetree This simplifies the code flow of the cpu init. APL can do CPU init after calling FSP-S, while GLK needs to afterwards. This is now reflected directly in the cpu ops rather than using CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT as a proxy. Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/chipset_apl.cb M src/soc/intel/apollolake/chipset_glk.cb M src/soc/intel/apollolake/cpu.c 4 files changed, 24 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/72705/1 diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 78fefb1..11e3a1e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -206,20 +206,24 @@ .acpi_fill_ssdt = ssdt_set_above_4g_pci, }; -static struct device_operations cpu_bus_ops = { +struct device_operations apl_cpu_bus_ops = { .read_resources = noop_read_resources, .set_resources = noop_set_resources, .init = apollolake_init_cpus, .acpi_fill_ssdt = generate_cpu_entries, }; +struct device_operations glk_cpu_bus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = generate_cpu_entries, +}; + static void enable_dev(struct device *dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; - else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) - dev->ops = &cpu_bus_ops; else if (dev->path.type == DEVICE_PATH_GPIO) block_gpio_enable(dev); } diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb index b4f1659..03a6776 100644 --- a/src/soc/intel/apollolake/chipset_apl.cb +++ b/src/soc/intel/apollolake/chipset_apl.cb @@ -1,5 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end + device cpu_cluster 0 on ops apl_cpu_bus_ops end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb index 07eecf5..c6f2db1 100644 --- a/src/soc/intel/apollolake/chipset_glk.cb +++ b/src/soc/intel/apollolake/chipset_glk.cb @@ -1,5 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end + device cpu_cluster 0 on ops glk_cpu_bus_ops end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index dba1923..7407415 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -271,8 +271,6 @@ void apollolake_init_cpus(struct device *dev) { - if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) - return; if (!dev->link_list) add_more_links(dev, 1); soc_init_cpus(dev->link_list); -- To view, visit https://review.coreboot.org/c/coreboot/+/72705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54 Gerrit-Change-Number: 72705 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-MessageType: newchange

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023