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[M] Change in coreboot[master]: soc/intel/apl: Move cpu cluster to chipset.cb
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Felix Singer, Sean Rhodes, Nico Huber, Maxim Polyakov, Werner Zeh. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72704 ) Change subject: soc/intel/apl: Move cpu cluster to chipset.cb ...................................................................... soc/intel/apl: Move cpu cluster to chipset.cb Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/up/squared/devicetree.cb M src/soc/intel/apollolake/chipset_apl.cb M src/soc/intel/apollolake/chipset_glk.cb 24 files changed, 12 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/72704/1 diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index eec90bc..7801b0d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2199ac0..d24e67b 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 7052497..f162519 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index bf40464..79da9fd 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 1ee9c38..45007f0 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 7c775ef..ec9ea9c1 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index ef361b0..a983807 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 45fb736..551fc60 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index add83fe..0a152b6 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index add83fe..0a152b6 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb index e77a172..b3f9a6e 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 7ce2480..a2a9df4 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -5,7 +5,6 @@ register "enable_vtd" = "1" register "dptf_enable" = "1" - device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 00.1 on end # DPTF diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index dad319e..a08f053 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b728438..b515170 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 4fae59e..56d93aa 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 586d65e..1c5f797 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 40739df..92bba65 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index c48eb5a..8223f68 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # 0:HS400(Default), 1:HS200, 2:DDR50 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index ce716a0..0a080c3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index 709d8e1..f1ace5a 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 96011ea..71932a6 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 867f3a5..4b0d5f7 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -20,7 +20,6 @@ # 0:HS400 (Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1" - device cpu_cluster 0 on end device domain 0 on subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb index 8a1b501..b4f1659 100644 --- a/src/soc/intel/apollolake/chipset_apl.cb +++ b/src/soc/intel/apollolake/chipset_apl.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb index 0043630..07eecf5 100644 --- a/src/soc/intel/apollolake/chipset_glk.cb +++ b/src/soc/intel/apollolake/chipset_glk.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF -- To view, visit https://review.coreboot.org/c/coreboot/+/72704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Gerrit-Change-Number: 72704 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel: Use common codeflow for MP init
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Nico Huber, Sean Rhodes, Tarun Tuli, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Lean Sheng Tan, Werner Zeh, Tim Chu. Hello Nico Huber, Tarun Tuli, Sean Rhodes, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Lean Sheng Tan, Werner Zeh, Tim Chu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72604 to look at the new patch set (#3). Change subject: soc/intel: Use common codeflow for MP init ...................................................................... soc/intel: Use common codeflow for MP init This fixes MP init on xeon_sp SoCs which was broken by 69cd729 (mb/*: Remove lapic from devicetree). Alderlake cpu code was linked in romstage but unused so drop it. Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/cpu.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/cannonlake/cpu.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/elkhartlake/cpu.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/meteorlake/cpu.c M src/soc/intel/skylake/cpu.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/skx/cpu.c 17 files changed, 34 insertions(+), 52 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/72604/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Gerrit-Change-Number: 72604 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
by Prashant Malani (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Nien, Martin Roth, Prashant Malani. Hello build bot (Jenkins), Jason Nien, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72654 to look at the new patch set (#2). Change subject: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes ...................................................................... mb/google/skyrim/var/winterhold: Add support for AP-driven muxes Add the platform ACPI devices needed for AP-driven Type-C mux and retimer programming. BUG=b:266218046 TEST=Tested on skyrim with Kconfig enabled, SSDT generated as expected. BRANCH=None Change-Id: I712a54e8b3bee8f4ead3b6cf2b495a8dda7962ad Signed-off-by: Prashant Malani <pmalani(a)chromium.org> --- M src/mainboard/google/skyrim/Kconfig M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb 2 files changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/72654/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712a54e8b3bee8f4ead3b6cf2b495a8dda7962ad Gerrit-Change-Number: 72654 Gerrit-PatchSet: 2 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Prashant Malani <pmalani(a)chromium.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel: Use common codeflow for MP init
by Arthur Heymans (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Nico Huber, Sean Rhodes, Tarun Tuli, Subrata Banik, Jonathan Zhang, Johnny Lin, Kapil Porwal, Christian Walter, Lean Sheng Tan, Werner Zeh, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72604 ) Change subject: soc/intel: Use common codeflow for MP init ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/apollolake/cpu.c: https://review.coreboot.org/c/coreboot/+/72604/comment/8a467063_fab87e3d PS2, Line 267: if (CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)) : return; > This seems to be here because APL and GLK use different paths. > `cpu_bus_ops->init` used to bail out here on GLK (because the > common code handled it). But now common code would indirectly > call this function... > > I think we are in trouble here, because of the singleton global > `mp_init_cpus` symbol. (soc/ code seems to be full of such single- > tons... not sure if that's a good path to follow) > > If I understand things correctly, one way out of it would be > to avoid the `.init` for GLK, or have a function there that > calls mp_cpus_bus_init() conditionally. (Or figure out why APL > still doesn't use common code, ofc.) I think APL did not need MP init to happen before calling FSP-S -- To view, visit https://review.coreboot.org/c/coreboot/+/72604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia822468a6f15565b97e57612a294a0b80b45b932 Gerrit-Change-Number: 72604 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:48:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Paul Menzel (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/f20cec3b_a8776526 PS2, Line 9: Intel ArcherCity CRB is a dual socket CRB with Intel : Sapphire Rapids Scalable Processor chipset. The chipset : also includes EmmitsBurg PCH. > Hi Paul, From the coreboot tutorial as below link it requests the commit messsage shall be 80 charac […] You cite an example, which is about the source code files, and not the commit message. (Also that is outdated.) Anyway, cf `util/lint/checkpatch.pl`, and Ic9c686cb1a902259b18377b76b5c999e94660fed. -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:48:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Chou <simonchou(a)supermicro.com.tw> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/3bb56c38_6fc42c4a PS2, Line 7: ArcherCity > Archer City Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:31:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: configs/builder: add default config for Intel Archer City CRB
by Paul Menzel (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Simon Chou, Jonathan Zhang, Johnny Lin, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71969 ) Change subject: configs/builder: add default config for Intel Archer City CRB ...................................................................... Patch Set 7: (1 comment) File configs/builder/config.intel.crb.ac: https://review.coreboot.org/c/coreboot/+/71969/comment/18ef21b0_750d3b23 PS2, Line 14: CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd" : CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd" : CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd" : CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin" : CONFIG_ME_BIN_PATH="site-local/archercity/me.bin" : CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb" > Hi Paul, could you check whether you question got answered? Thank you for the answers. Maybe mention it in the commit message? -- To view, visit https://review.coreboot.org/c/coreboot/+/71969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Gerrit-Change-Number: 71969 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:28:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Simon Chou <simonchou(a)supermicro.com.tw> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71968/comment/24a9b252_a8f5e09a PS2, Line 9: Intel ArcherCity CRB is a dual socket CRB with Intel : Sapphire Rapids Scalable Processor chipset. The chipset : also includes EmmitsBurg PCH. > Please use the full text width of 72 characters. (Please update all commit message accordingly. […] Hi Paul, From the coreboot tutorial as below link it requests the commit messsage shall be 80 characters per line. I have no idea why you are asking for 72 characters. https://doc.coreboot.org/tutorial/part2.html (step 4b) -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:26:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: amdfwtool: Change .rom.efs to .rom and .rom to .rom.body
by Bao Zheng (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72702 ) Change subject: amdfwtool: Change .rom.efs to .rom and .rom to .rom.body ...................................................................... Patch Set 1: (2 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/72702/comment/abcd63cc_511b70a8 PS1, Line 114: Keep the empty line. https://review.coreboot.org/c/coreboot/+/72702/comment/356f0fc9_c74df404 PS1, Line 2697: bytes = write_efs(output, amd_romsig); : if (bytes != sizeof(*amd_romsig)) { : fprintf(stderr, "Error: Writing EFS\n"); : retval = 1; : } check the return value. -- To view, visit https://review.coreboot.org/c/coreboot/+/72702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Gerrit-Change-Number: 72702 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:19:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: [only for test]toolchain: upgrade to gcc-13-20230129
by Elyes Haouas (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/70771 to look at the new patch set (#3). Change subject: [only for test]toolchain: upgrade to gcc-13-20230129 ...................................................................... [only for test]toolchain: upgrade to gcc-13-20230129 Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-11.2.0_gnat.patch R util/crossgcc/patches/gcc-13-20230129_ada-musl_workaround.patch R util/crossgcc/patches/gcc-13-20230129_asan_shadow_offset_callback.patch A util/crossgcc/patches/gcc-13-20230129_gnat.patch R util/crossgcc/patches/gcc-13-20230129_libcpp.patch R util/crossgcc/patches/gcc-13-20230129_libgcc.patch D util/crossgcc/sum/gcc-11.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-13-20230129.tar.xz.cksum 9 files changed, 58 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/70771/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/70771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f2ed4de4811abaa13528906de71eee29a8f2910 Gerrit-Change-Number: 70771 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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