Attention is currently required from: Simon Chou, Johnny Lin, Christian Walter, Arthur Heymans.
Johnny Lin has uploaded a new patch set (#10) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71965 )
Change subject: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
......................................................................
soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
For some Xeon-SP (such as SPR-SP), more buses should be probed.
Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com>
Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
---
M src/soc/intel/xeon_sp/chip_common.c
1 file changed, 57 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/71965/10
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Bora Guvendik has uploaded a new patch set (#4) to the change originally created by Selma Bensaid. ( https://review.coreboot.org/c/coreboot/+/68636 )
Change subject: mb/google/brya,skolas: disable Tccold Handshake
......................................................................
mb/google/brya,skolas: disable Tccold Handshake
The patch disables Tccold Handshake to prevent possible display
flicker issue for skolas board. Please refer Intel doc#723158 for
more information.
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Verify the build for skolas board
Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com>
Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856
---
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/skolas/overridetree.cb
M src/mainboard/google/brya/variants/skolas4es/overridetree.cb
3 files changed, 30 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/68636/4
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Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
......................................................................
soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
This commit provides a dev tree setting for partners to enable/disable
TccoldHandshake for the sighting in doc:723158
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=compile ok and FSP UPD is config properly
Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com>
Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e
---
M src/soc/intel/alderlake/chip.h
M src/soc/intel/alderlake/romstage/fsp_params.c
2 files changed, 29 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/68635/6
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Change subject: commonlib: Add ELOG_ME_PATH_EARLY_SOL_SHOWN eventLog for CSE FW sync
......................................................................
commonlib: Add ELOG_ME_PATH_EARLY_SOL_SHOWN eventLog for CSE FW sync
Add a path entry of ELOG_ME_PATH_EARLY_SOL_SHOWN
to the ELOG_TYPE_MANAGEMENT_ENGINE event in order to support
logging of CSE FW sync early sign of life (SOL) events.
BUG=b:266113626
TEST=verify event shows in eventlog after boot/CSE sync
Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c
Signed-off-by: Tarun Tuli <tarun.tuli(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/elog.h
1 file changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/72670/5
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Hello Subrata Banik, Jérémy Compostella,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#7).
Change subject: soc/intel/alderlake: On CSE FW sync early SOL add entry to eventLog
......................................................................
soc/intel/alderlake: On CSE FW sync early SOL add entry to eventLog
In the case that we perform a CSE sync and early SOL is enabled,
add a corresponding entry to the eventLog of type
ELOG_TYPE_MANAGEMENT_ENGINE and path ELOG_ME_PATH_EARLY_SOL_SHOWN
BUG=b:264648959
TEST=builds and entry is logged as part of CSE FW sync
Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2
Signed-off-by: Tarun Tuli <taruntuli(a)intel.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/alderlake/romstage/ux.c
M src/soc/intel/alderlake/romstage/ux.h
3 files changed, 24 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71295/7
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Hello Subrata Banik, Jérémy Compostella,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/71295
to look at the new patch set (#6).
Change subject: soc/intel/alderlake: On CSE sync early SOL add entry to eventLog
......................................................................
soc/intel/alderlake: On CSE sync early SOL add entry to eventLog
In the case that we perform a CSE sync and early SOL is enabled,
add a corresponding entry to the eventLog of type
ELOG_TYPE_MANAGEMENT_ENGINE and path ELOG_ME_PATH_EARLY_SOL_SHOWN
BUG=b:264648959
TEST=builds
Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2
Signed-off-by: Tarun Tuli <taruntuli(a)intel.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/alderlake/romstage/ux.c
M src/soc/intel/alderlake/romstage/ux.h
3 files changed, 24 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71295/6
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