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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
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Change subject: amdfwtool: Allow the location to be a relative address
......................................................................
amdfwtool: Allow the location to be a relative address
When the BIOS size is more than 32M, the physical address of EFS
header will be complicated, like 0xfe020000 or 0xfc020000. So we make
it simpler to allow to use relative address.
This CL works with https://review.coreboot.org/c/coreboot/+/69852
Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 38 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69856/14
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Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
......................................................................
Patch Set 6: Code-Review+1
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Change subject: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
......................................................................
Patch Set 1: Code-Review-1
(1 comment)
Patchset:
PS1:
Self -1, since this is experimental and not ready for submission.
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Change subject: ec/google/chromeec: Add handles for ori, usb role switch
......................................................................
Patch Set 4:
(1 comment)
File src/ec/google/chromeec/ec_acpi.c:
https://review.coreboot.org/c/coreboot/+/72370/comment/190a1788_46c525b2
PS3, Line 195: .orientation_switch = config->ori_conn[i],
: .usb_role_switch = config->usb_role_conn[i],
> > could you add the skyrim case as the next patch so we have some insight
> into what's coming up? i didn't see anything interesting USB related
> in the existing skyrim device tree.
>
> Sure. I can add a CL to the stack. It's still under development, so we don't want to enable it yet.
Done: https://review.coreboot.org/c/coreboot/+/72654/1
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Change subject: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
......................................................................
mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
Add the platform ACPI devices needed for AP-driven Type-C mux and
retimer programming.
BUG=b:266218046
TEST=Tested on skyrim with Kconfig enabled, SSDT generated as expected.
BRANCH=None
Change-Id: I712a54e8b3bee8f4ead3b6cf2b495a8dda7962ad
---
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
2 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/72654/1
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index d945474..19755cd 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -27,6 +27,7 @@
select DRIVERS_PCIE_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
+ select EC_GOOGLE_CHROMEEC_MUX
select EC_GOOGLE_CHROMEEC_SKUID
select EC_GOOGLE_CHROMEEC_BOARDID
select ELOG
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 04da26c..7f40e32 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -157,6 +157,31 @@
end
end # XHCI1 controller
end # Internal GPP Bridge 0 to Bus A
+
+ device ref lpc_bridge on
+ chip ec/google/chromeec
+ use ecmux0 as retimer_conn[0]
+ use ecmux1 as retimer_conn[1]
+ use ecmux0 as mux_conn[0]
+ use ecmux1 as mux_conn[1]
+ device ref chrome_ec on
+ chip ec/google/chromeec/mux
+ device generic 0 on
+ chip ec/google/chromeec/mux/conn
+ register "mode_switch" = "true"
+ register "retimer_switch" = "true"
+ device generic 0 alias ecmux0 on end
+ end
+ chip ec/google/chromeec/mux/conn
+ register "mode_switch" = "true"
+ register "retimer_switch" = "true"
+ device generic 1 alias ecmux1 on end
+ end
+ end
+ end
+ end
+ end
+ end
end # domain
device ref i2c_0 on
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Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71882/comment/463121a4_cbbfc9b2
PS5, Line 52: # Type-C Port A0
> is A0 the type-C port? Down further A0 refers to the first USB-A port.
This is a typo in the comment here, fixed.
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Hello Sam McNally, build bot (Jenkins), Adam Mills,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
......................................................................
mb/google/dedede/var/dibbi: Update devicetree and GPIO table
Create overridetree and GPIO config based on latest schematic:
1. Update PCIe ports
2. Update USB ports
3. Remove unused I2Cs
4. Remove unused peripherals (SD card, eDP, speakers)
5. Add LAN
6. Thermal policy for updated temp sensors
BUG=b:260934185, b:260934719
BRANCH=dedede
TEST=build
Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe
Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org>
---
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/gpio.c
M src/mainboard/google/dedede/variants/dibbi/overridetree.cb
4 files changed, 310 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/71882/6
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Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71860/comment/2985ab97_069d3d77
PS3, Line 24: CPU_6W_DPTF0
> nit: `THERMAL_SOLUTION_6W` to match config. […]
fixed.
https://review.coreboot.org/c/coreboot/+/71860/comment/a263a93e_212ddc4d
PS3, Line 25: CPU_15W_DPTF1
> nit: `THERMAL_SOLUTION_15W` to match config. […]
fixed.
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Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................
mb/google/nissa/var/craask: Modify DPTF settings
Add ADL-N 15W CPU Power Limit(PL) settings for Craasneto
BUG=b:265101768
TEST=emerge-nissa coreboot
Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/craask/overridetree.cb
1 file changed, 74 insertions(+), 1 deletion(-)
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