February 2023 - coreboot-gerrit

[S] Change in coreboot[master]: crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2
by Elyes Haouas (Code Review) Feb. 1, 2023

Feb. 1, 2023

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71889 ) Change subject: crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2 ...................................................................... crossgcc: Upgrade CMake from version 3.25.0 to 3.25.2 Change-Id: Iaf0988997c6644e0e4f02d60a1d6de0e498e19bc Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71889 Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum A util/crossgcc/sum/cmake-3.25.2.tar.gz.cksum 3 files changed, 15 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 0f5a70a..cfbe0e8 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -42,7 +42,7 @@ IASL_VERSION="R10_20_22" # CLANG version number CLANG_VERSION=15.0.6 -CMAKE_VERSION=3.25.0 +CMAKE_VERSION=3.25.2 NASM_VERSION=2.15.05 # Filename for each package diff --git a/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum b/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum deleted file mode 100644 index bb3d397..0000000 --- a/util/crossgcc/sum/cmake-3.25.0.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c791c64877ee550b78613bf089f2a7a58d3b1b65 tarballs/cmake-3.25.0.tar.gz diff --git a/util/crossgcc/sum/cmake-3.25.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.25.2.tar.gz.cksum new file mode 100644 index 0000000..f4a2e3c --- /dev/null +++ b/util/crossgcc/sum/cmake-3.25.2.tar.gz.cksum @@ -0,0 +1 @@ +2f444bb9951aad09452b692d8b3b9e33309e1641 tarballs/cmake-3.25.2.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/71889 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaf0988997c6644e0e4f02d60a1d6de0e498e19bc Gerrit-Change-Number: 71889 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Log event on CSE sync early Sign of Life
by Tarun Tuli (Code Review) Feb. 1, 2023

Feb. 1, 2023

Tarun Tuli has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/71297 ) Change subject: soc/intel/alderlake: Log event on CSE sync early Sign of Life ...................................................................... Abandoned squashing -- To view, visit https://review.coreboot.org/c/coreboot/+/71297 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63531b3abb5bd01d0304de600e0c01544ad600e0 Gerrit-Change-Number: 71297 Gerrit-PatchSet: 6 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: Documentation/gerrit_guidelines: Fix newlines
by Elyes Haouas (Code Review) Feb. 1, 2023

Feb. 1, 2023

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72625 ) Change subject: Documentation/gerrit_guidelines: Fix newlines ...................................................................... Documentation/gerrit_guidelines: Fix newlines Markdown does not render newlines unless there is an empty line in between the lines of text. Several command examples and a list were missing these empty lines, causing their content to be rendered inline with the preceding text. Fix this by adding triple backticks around code blocks and bullet points to rows of text in a list. Change-Id: I9c1d2b81acdeb378346c68bced0cdbfeeb81bf26 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72625 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/contributing/gerrit_guidelines.md 1 file changed, 51 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Felix Singer: Looks good to me, approved diff --git a/Documentation/contributing/gerrit_guidelines.md b/Documentation/contributing/gerrit_guidelines.md index 74f79c0..e23bff7 100644 --- a/Documentation/contributing/gerrit_guidelines.md +++ b/Documentation/contributing/gerrit_guidelines.md @@ -173,7 +173,10 @@ for no reason if there are failing patches in the train. For running parallel builds, you can specify the number of cores to use by setting the the CPUS environment variable. Example: - make what-jenkins-does CPUS=8 + +```Bash +make what-jenkins-does CPUS=8 +``` * Use a topic when pushing a train of patches. This groups the commits together so people can easily see the connection at the top level of @@ -181,7 +184,10 @@ the patch and clicking on the icon next to the topic line. Topics can also be set when you push the patches into gerrit. For example, to push a set of commits with the i915-kernel-x60 set, use the command: - git push origin HEAD:refs/for/master%topic=i915-kernel-x60 + +```Bash +git push origin HEAD:refs/for/master%topic=i915-kernel-x60 +``` * If one of your patches isn't ready to be merged, make sure it's obvious that you don't feel it's ready for merge yet. The preferred way to show @@ -191,7 +197,10 @@ mark the patch as not ready would be to give it a -1 or -2 review, but isn't as obvious as the commit message. These patches can also be pushed with the wip flag: - git push origin HEAD:refs/for/master%wip + +```Bash +git push origin HEAD:refs/for/master%wip +``` * When pushing patches that are not for submission, these should be marked as such. This can be done in the title ‘[DONOTSUBMIT]’, or can be pushed as @@ -200,10 +209,16 @@ look at. Note that private changes can still be fetched from Gerrit by anybody who knows their commit ID, so don't use this for sensitive changes. To push a private change, use the command: - git push origin HEAD:refs/for/master%private + +```Bash +git push origin HEAD:refs/for/master%private +``` * Multiple push options can be combined: - git push origin HEAD:refs/for/master%private,wip,topic=experiment + +```Bash +git push origin HEAD:refs/for/master%private,wip,topic=experiment +``` * Respond to anyone who has taken the time to review your patches, even if it's just to say that you disagree. While it may seem annoying to address a @@ -277,13 +292,15 @@ the original text this way makes it much easier to tell what changes happened in which repository. This applies to these lines, not the actual commit message itself: - Commit-Id: - Change-Id: - Signed-off-by: - Reviewed-on: - Tested-by: - Reviewed-by: -The script 'util/gitconfig/rebase.sh' can be used to help automate this. + + * Commit-Id: + * Change-Id: + * Signed-off-by: + * Reviewed-on: + * Tested-by: + * Reviewed-by: + +The script `util/gitconfig/rebase.sh` can be used to help automate this. Other tags such as 'Commit-Queue' can simply be removed. * Check if there's documentation that needs to be updated to remain current -- To view, visit https://review.coreboot.org/c/coreboot/+/72625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c1d2b81acdeb378346c68bced0cdbfeeb81bf26 Gerrit-Change-Number: 72625 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: treewide: Remove duplicated include <device/pci.h>
by Elyes Haouas (Code Review) Feb. 1, 2023

Feb. 1, 2023

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72626 ) Change subject: treewide: Remove duplicated include <device/pci.h> ...................................................................... treewide: Remove duplicated include <device/pci.h> <device/pci.h> chain-includes <device/pci_def.h> & <device/pci_type.h>. Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72626 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/arch/x86/smbios.c M src/device/pci_early.c M src/device/pci_ops.c M src/drivers/intel/i210/i210.c M src/drivers/net/r8168.c M src/drivers/siemens/nc_fpga/nc_fpga.c M src/drivers/siemens/nc_fpga/nc_fpga_early.c M src/drivers/uart/oxpcie.c M src/drivers/uart/oxpcie_early.c M src/drivers/usb/pci_ehci.c M src/drivers/wifi/generic/generic.c M src/northbridge/intel/haswell/northbridge.c M src/northbridge/intel/i945/early_init.c M src/northbridge/intel/pineview/gma.c M src/soc/amd/common/block/lpc/lpc.c M src/soc/amd/picasso/sata.c M src/soc/amd/stoneyridge/sata.c M src/soc/cavium/common/ecam.c M src/soc/intel/alderlake/pmutil.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/baytrail/hda.c M src/soc/intel/broadwell/pch/me.c M src/soc/intel/broadwell/pch/pch.c M src/soc/intel/broadwell/pch/pcie.c M src/soc/intel/broadwell/pch/pmutil.c M src/soc/intel/broadwell/pch/power_state.c M src/soc/intel/cannonlake/pmutil.c M src/soc/intel/cannonlake/romstage/fsp_params.c M src/soc/intel/common/block/fast_spi/fast_spi.c M src/soc/intel/common/block/i2c/i2c.c M src/soc/intel/common/block/irq/irq.c M src/soc/intel/common/block/pcie/pcie.c M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/spi/spi.c M src/soc/intel/common/block/uart/uart.c M src/soc/intel/common/block/usb4/usb4.c M src/soc/intel/denverton_ns/soc_util.c M src/soc/intel/elkhartlake/pmutil.c M src/soc/intel/jasperlake/pmutil.c M src/soc/intel/meteorlake/pmutil.c M src/soc/intel/quark/include/soc/pci_devs.h M src/soc/intel/quark/romstage/report_platform.c M src/soc/intel/quark/uart.c M src/soc/intel/skylake/pmutil.c M src/soc/intel/tigerlake/pmutil.c M src/soc/mediatek/common/pcie.c M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/sc7280/pcie.c M src/southbridge/amd/pi/hudson/hudson.c M src/southbridge/amd/pi/hudson/lpc.c M src/southbridge/intel/bd82x6x/lpc.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/bd82x6x/me_common.c M src/southbridge/intel/bd82x6x/me_smm.c M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pci.c M src/southbridge/intel/bd82x6x/pcie.c M src/southbridge/intel/bd82x6x/smbus.c M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/common/smbus_ops.c M src/southbridge/intel/common/watchdog.c M src/southbridge/intel/i82371eb/early_pm.c M src/southbridge/intel/i82371eb/early_smbus.c M src/southbridge/intel/i82801gx/ac97.c M src/southbridge/intel/i82801gx/pci.c M src/southbridge/intel/i82801gx/pcie.c M src/southbridge/intel/i82801gx/smbus.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/i82801ix/pcie.c M src/southbridge/intel/i82801ix/smbus.c M src/southbridge/intel/i82801jx/pcie.c M src/southbridge/intel/i82801jx/smbus.c M src/southbridge/intel/ibexpeak/me.c M src/southbridge/intel/ibexpeak/pch.c M src/southbridge/intel/ibexpeak/smbus.c M src/southbridge/intel/ibexpeak/thermal.c M src/southbridge/intel/lynxpoint/me.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/pmutil.c 81 files changed, 15 insertions(+), 84 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 0b1f8fd..c505bb0 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -16,7 +16,6 @@ #include <cbmem.h> #include <commonlib/helpers.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <device/pci.h> #include <drivers/vpd/vpd.h> #include <stdlib.h> diff --git a/src/device/pci_early.c b/src/device/pci_early.c index 590b170..86278f9 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,9 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> -#include <device/pci_type.h> #include <delay.h> void pci_s_assert_secondary_reset(pci_devfn_t p2p_bridge) diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index a4ef405..31b7345 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -3,9 +3,7 @@ #include <stdint.h> #include <console/console.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> -#include <device/pci_type.h> u8 *const pci_mmconf = (void *)(uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS; diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 018a67d..45219c6 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -6,7 +6,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <string.h> #include <types.h> #include <delay.h> diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 5d19d69..8f070bd 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -16,7 +16,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <delay.h> #include <fmap.h> diff --git a/src/drivers/siemens/nc_fpga/nc_fpga.c b/src/drivers/siemens/nc_fpga/nc_fpga.c index fe6eb15..dd30d51 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga.c @@ -4,7 +4,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <device/mmio.h> #include <hwilib.h> #include <bootstate.h> diff --git a/src/drivers/siemens/nc_fpga/nc_fpga_early.c b/src/drivers/siemens/nc_fpga/nc_fpga_early.c index 8cdc1f9..284ec8a 100644 --- a/src/drivers/siemens/nc_fpga/nc_fpga_early.c +++ b/src/drivers/siemens/nc_fpga/nc_fpga_early.c @@ -2,7 +2,6 @@ #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <types.h> diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index 59e8ff2..ae2a3a6 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> -#include <device/pci_def.h> #include <device/pci.h> #include <console/console.h> #include <console/uart.h> diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index ff7d0cf..2cbc8c7 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -5,7 +5,6 @@ #include <device/pci_ops.h> #include <console/uart.h> #include <device/pci.h> -#include <device/pci_def.h> static unsigned int oxpcie_present; static DEVTREE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; diff --git a/src/drivers/usb/pci_ehci.c b/src/drivers/usb/pci_ehci.c index 8e85426..8b68bc2 100644 --- a/src/drivers/usb/pci_ehci.c +++ b/src/drivers/usb/pci_ehci.c @@ -5,7 +5,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci.h> -#include <device/pci_def.h> #include <string.h> #include "ehci_debug.h" diff --git a/src/drivers/wifi/generic/generic.c b/src/drivers/wifi/generic/generic.c index 2368f51..adcb68d 100644 --- a/src/drivers/wifi/generic/generic.c +++ b/src/drivers/wifi/generic/generic.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <elog.h> #include "chip.h" diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index bcb2a0b..17ffff2 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -7,7 +7,6 @@ #include <cpu/intel/haswell/haswell.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <boot/tables.h> diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d730b2e..d61949f 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -3,7 +3,6 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci.h> #include <option.h> diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index d68c04d..a7ff32f 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -6,7 +6,6 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <drivers/intel/gma/i915_reg.h> diff --git a/src/soc/amd/common/block/lpc/lpc.c b/src/soc/amd/common/block/lpc/lpc.c index 5633d8f..09c35db 100644 --- a/src/soc/amd/common/block/lpc/lpc.c +++ b/src/soc/amd/common/block/lpc/lpc.c @@ -6,7 +6,6 @@ #include <device/pci.h> #include <device/pnp.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <pc80/i8254.h> diff --git a/src/soc/amd/picasso/sata.c b/src/soc/amd/picasso/sata.c index e64635f..fb2f7ac 100644 --- a/src/soc/amd/picasso/sata.c +++ b/src/soc/amd/picasso/sata.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <amdblocks/sata.h> #include <soc/southbridge.h> diff --git a/src/soc/amd/stoneyridge/sata.c b/src/soc/amd/stoneyridge/sata.c index e64635f..fb2f7ac 100644 --- a/src/soc/amd/stoneyridge/sata.c +++ b/src/soc/amd/stoneyridge/sata.c @@ -3,7 +3,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <amdblocks/sata.h> #include <soc/southbridge.h> diff --git a/src/soc/cavium/common/ecam.c b/src/soc/cavium/common/ecam.c index 88368178..1781820 100644 --- a/src/soc/cavium/common/ecam.c +++ b/src/soc/cavium/common/ecam.c @@ -7,7 +7,6 @@ #define __SIMPLE_DEVICE__ #include <device/pci_ops.h> -#include <device/pci_def.h> #include <device/pci.h> #include <soc/addressmap.h> #include <soc/ecam.h> diff --git a/src/soc/intel/alderlake/pmutil.c b/src/soc/intel/alderlake/pmutil.c index 3e9f71f..0c508ff 100644 --- a/src/soc/intel/alderlake/pmutil.c +++ b/src/soc/intel/alderlake/pmutil.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 41f806f..b799d02 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -9,7 +9,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <intelblocks/msr.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/baytrail/hda.c b/src/soc/intel/baytrail/hda.c index 6bebf05..46fbce1 100644 --- a/src/soc/intel/baytrail/hda.c +++ b/src/soc/intel/baytrail/hda.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <reg_script.h> diff --git a/src/soc/intel/broadwell/pch/me.c b/src/soc/intel/broadwell/pch/me.c index 08917fd..6973c72 100644 --- a/src/soc/intel/broadwell/pch/me.c +++ b/src/soc/intel/broadwell/pch/me.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <stdlib.h> #include <string.h> #include <delay.h> diff --git a/src/soc/intel/broadwell/pch/pch.c b/src/soc/intel/broadwell/pch/pch.c index c2ff5b0..98fbc46 100644 --- a/src/soc/intel/broadwell/pch/pch.c +++ b/src/soc/intel/broadwell/pch/pch.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <soc/pch.h> #include <soc/pci_devs.h> #include <soc/rcba.h> diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index 61d6962..ef03eee 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pciexp.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <soc/lpc.h> diff --git a/src/soc/intel/broadwell/pch/pmutil.c b/src/soc/intel/broadwell/pch/pmutil.c index 931dcc9..4ba30b4 100644 --- a/src/soc/intel/broadwell/pch/pmutil.c +++ b/src/soc/intel/broadwell/pch/pmutil.c @@ -11,7 +11,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <console/console.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/broadwell/pch/power_state.c b/src/soc/intel/broadwell/pch/power_state.c index b1ab622..842878b 100644 --- a/src/soc/intel/broadwell/pch/power_state.c +++ b/src/soc/intel/broadwell/pch/power_state.c @@ -6,7 +6,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <string.h> #include <soc/iomap.h> #include <soc/lpc.h> diff --git a/src/soc/intel/cannonlake/pmutil.c b/src/soc/intel/cannonlake/pmutil.c index 512b49b..681068d 100644 --- a/src/soc/intel/cannonlake/pmutil.c +++ b/src/soc/intel/cannonlake/pmutil.c @@ -12,7 +12,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index 842c8fb..737e7c3 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <device/pci_def.h> #include <device/pci.h> #include <cpu/x86/msr.h> #include <console/console.h> diff --git a/src/soc/intel/common/block/fast_spi/fast_spi.c b/src/soc/intel/common/block/fast_spi/fast_spi.c index a2c4991..ed2e8f2 100644 --- a/src/soc/intel/common/block/fast_spi/fast_spi.c +++ b/src/soc/intel/common/block/fast_spi/fast_spi.c @@ -8,7 +8,6 @@ #include <device/mmio.h> #include <assert.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <console/console.h> diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 481ba7b..70c7e18 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -5,7 +5,6 @@ #include <device/device.h> #include <device/i2c_simple.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <drivers/i2c/designware/dw_i2c.h> #include <intelblocks/cfg.h> diff --git a/src/soc/intel/common/block/irq/irq.c b/src/soc/intel/common/block/irq/irq.c index 724061e..4ffe138 100644 --- a/src/soc/intel/common/block/irq/irq.c +++ b/src/soc/intel/common/block/irq/irq.c @@ -3,7 +3,6 @@ #include <assert.h> #include <console/console.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <intelblocks/gpio.h> #include <intelblocks/irq.h> diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index dd0b0ef..c8a958d 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/pciexp.h> diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 12b176c..1f1a85c 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -6,7 +6,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <intelblocks/gpmr.h> #include <intelblocks/pcr.h> #include <intelblocks/pmclib.h> diff --git a/src/soc/intel/common/block/spi/spi.c b/src/soc/intel/common/block/spi/spi.c index f6a211b..93278f1 100644 --- a/src/soc/intel/common/block/spi/spi.c +++ b/src/soc/intel/common/block/spi/spi.c @@ -7,10 +7,8 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <device/pci_type.h> #include <device/spi.h> #include <intelblocks/fast_spi.h> #include <intelblocks/gspi.h> diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 0ca3361..76e4bc9 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -6,7 +6,6 @@ #include <console/uart.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <intelblocks/irq.h> diff --git a/src/soc/intel/common/block/usb4/usb4.c b/src/soc/intel/common/block/usb4/usb4.c index d62496e..a90a35a 100644 --- a/src/soc/intel/common/block/usb4/usb4.c +++ b/src/soc/intel/common/block/usb4/usb4.c @@ -4,7 +4,6 @@ #include <acpi/acpi_device.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <intelblocks/tcss.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/denverton_ns/soc_util.c b/src/soc/intel/denverton_ns/soc_util.c index b4c707d..dbe924b 100644 --- a/src/soc/intel/denverton_ns/soc_util.c +++ b/src/soc/intel/denverton_ns/soc_util.c @@ -4,7 +4,6 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/device.h> #include <string.h> #include <soc/iomap.h> diff --git a/src/soc/intel/elkhartlake/pmutil.c b/src/soc/intel/elkhartlake/pmutil.c index 4203bee..adc3056 100644 --- a/src/soc/intel/elkhartlake/pmutil.c +++ b/src/soc/intel/elkhartlake/pmutil.c @@ -12,7 +12,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/jasperlake/pmutil.c b/src/soc/intel/jasperlake/pmutil.c index 744a2fb..f52cc43 100644 --- a/src/soc/intel/jasperlake/pmutil.c +++ b/src/soc/intel/jasperlake/pmutil.c @@ -12,7 +12,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/meteorlake/pmutil.c b/src/soc/intel/meteorlake/pmutil.c index 9ed87f8..8b377c0 100644 --- a/src/soc/intel/meteorlake/pmutil.c +++ b/src/soc/intel/meteorlake/pmutil.c @@ -12,7 +12,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h index 2c6a532..11594f5 100644 --- a/src/soc/intel/quark/include/soc/pci_devs.h +++ b/src/soc/intel/quark/include/soc/pci_devs.h @@ -4,7 +4,6 @@ #define _QUARK_PCI_DEVS_H_ #include <device/pci.h> -#include <device/pci_def.h> /* DEVICE 0 (Memory Controller Hub) */ #define MC_BDF PCI_DEV(PCI_BUS_NUMBER_QNC, MC_DEV, MC_FUN) diff --git a/src/soc/intel/quark/romstage/report_platform.c b/src/soc/intel/quark/romstage/report_platform.c index 3b4e367..7a49148 100644 --- a/src/soc/intel/quark/romstage/report_platform.c +++ b/src/soc/intel/quark/romstage/report_platform.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <cpu/cpu.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <soc/cpu.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/quark/uart.c b/src/soc/intel/quark/uart.c index c045c34..0047664 100644 --- a/src/soc/intel/quark/uart.c +++ b/src/soc/intel/quark/uart.c @@ -2,7 +2,6 @@ #include <console/uart.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index c31fb06..5152237 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -13,7 +13,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/lpc_lib.h> diff --git a/src/soc/intel/tigerlake/pmutil.c b/src/soc/intel/tigerlake/pmutil.c index 3c870c5..f8a7b19 100644 --- a/src/soc/intel/tigerlake/pmutil.c +++ b/src/soc/intel/tigerlake/pmutil.c @@ -18,7 +18,6 @@ #include <device/mmio.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> diff --git a/src/soc/mediatek/common/pcie.c b/src/soc/mediatek/common/pcie.c index fd93665..8b5b36b 100644 --- a/src/soc/mediatek/common/pcie.c +++ b/src/soc/mediatek/common/pcie.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/resource.h> #include <delay.h> diff --git a/src/soc/qualcomm/common/pcie_common.c b/src/soc/qualcomm/common/pcie_common.c index 940b206..9825508 100644 --- a/src/soc/qualcomm/common/pcie_common.c +++ b/src/soc/qualcomm/common/pcie_common.c @@ -6,7 +6,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <gpio.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sc7280/pcie.c b/src/soc/qualcomm/sc7280/pcie.c index edc73b0..84fa44c 100644 --- a/src/soc/qualcomm/sc7280/pcie.c +++ b/src/soc/qualcomm/sc7280/pcie.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <gpio.h> #include <soc/addressmap.h> #include <soc/clock.h> diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 1e9864a..59e293f 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -7,7 +7,6 @@ #include <acpi/acpi.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <types.h> diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index ccca113..7abb5bf 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -7,7 +7,6 @@ #include <device/pnp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> #include <arch/io.h> diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 7c10c81..0cf7b9c 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -5,7 +5,6 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <device/pci_ops.h> -#include <device/pci_def.h> #include <option.h> #include <pc80/isa-dma.h> #include <pc80/i8259.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 66c7dd2..7394882 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -16,7 +16,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <elog.h> #include <halt.h> #include <option.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 2a6caa6..8702c4d 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -16,7 +16,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <string.h> #include <elog.h> #include <halt.h> diff --git a/src/southbridge/intel/bd82x6x/me_common.c b/src/southbridge/intel/bd82x6x/me_common.c index a48d412..2db3c2d 100644 --- a/src/southbridge/intel/bd82x6x/me_common.c +++ b/src/southbridge/intel/bd82x6x/me_common.c @@ -6,7 +6,6 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <string.h> #include <delay.h> #include <halt.h> diff --git a/src/southbridge/intel/bd82x6x/me_smm.c b/src/southbridge/intel/bd82x6x/me_smm.c index c7a7f45..ea39559 100644 --- a/src/southbridge/intel/bd82x6x/me_smm.c +++ b/src/southbridge/intel/bd82x6x/me_smm.c @@ -2,7 +2,6 @@ #include <console/console.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <stdint.h> diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 16ffaf5..ae8ed9b 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -4,7 +4,6 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <string.h> diff --git a/src/southbridge/intel/bd82x6x/pci.c b/src/southbridge/intel/bd82x6x/pci.c index b82f3da..382506b 100644 --- a/src/southbridge/intel/bd82x6x/pci.c +++ b/src/southbridge/intel/bd82x6x/pci.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index a85b261..6f082e8 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pciexp.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c index 3c19075..0cb6d00 100644 --- a/src/southbridge/intel/bd82x6x/smbus.c +++ b/src/southbridge/intel/bd82x6x/smbus.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index 82b6122..db356b0 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -4,7 +4,6 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include "pciehp.h" diff --git a/src/southbridge/intel/common/smbus_ops.c b/src/southbridge/intel/common/smbus_ops.c index 46fc58a..347de73 100644 --- a/src/southbridge/intel/common/smbus_ops.c +++ b/src/southbridge/intel/common/smbus_ops.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/smbus_host.h> #include <southbridge/intel/common/smbus_ops.h> diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index e22dbfb..1c43a0c 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/tco.h> diff --git a/src/southbridge/intel/i82371eb/early_pm.c b/src/southbridge/intel/i82371eb/early_pm.c index 2a1c6eb..3cf56f2 100644 --- a/src/southbridge/intel/i82371eb/early_pm.c +++ b/src/southbridge/intel/i82371eb/early_pm.c @@ -3,7 +3,6 @@ #include <stdint.h> #include <device/pci_ops.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82371eb/early_smbus.c b/src/southbridge/intel/i82371eb/early_smbus.c index d2ff00a..0e0fd5b 100644 --- a/src/southbridge/intel/i82371eb/early_smbus.c +++ b/src/southbridge/intel/i82371eb/early_smbus.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <device/smbus_host.h> #include "i82371eb.h" diff --git a/src/southbridge/intel/i82801gx/ac97.c b/src/southbridge/intel/i82801gx/ac97.c index bdc8f77..aa73ae2 100644 --- a/src/southbridge/intel/i82801gx/ac97.c +++ b/src/southbridge/intel/i82801gx/ac97.c @@ -4,7 +4,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <arch/io.h> #include <device/pci_ops.h> #include <delay.h> diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index bf123bd..a9e86a0 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -2,7 +2,6 @@ #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "i82801gx.h" diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index b9b8ccd..befbf3b 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "chip.h" diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c index cfacca0..d498037 100644 --- a/src/southbridge/intel/i82801gx/smbus.c +++ b/src/southbridge/intel/i82801gx/smbus.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/smbus_host.h> #include <southbridge/intel/common/smbus_ops.h> diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 811dc50..bfaceea 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -7,7 +7,6 @@ #include "i82801gx.h" #include <device/pci_ehci.h> #include <device/mmio.h> -#include <device/pci_def.h> #include <device/pci_ops.h> static void usb_ehci_init(struct device *dev) diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index a199dd1..a374068 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pciexp.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c index 17f7b6b..1ddfb7f 100644 --- a/src/southbridge/intel/i82801ix/smbus.c +++ b/src/southbridge/intel/i82801ix/smbus.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> diff --git a/src/southbridge/intel/i82801jx/pcie.c b/src/southbridge/intel/i82801jx/pcie.c index 1d02898..3ed9d60 100644 --- a/src/southbridge/intel/i82801jx/pcie.c +++ b/src/southbridge/intel/i82801jx/pcie.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pciexp.h> #include <device/pci_ids.h> diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c index 6c9df2f..8fa1914 100644 --- a/src/southbridge/intel/i82801jx/smbus.c +++ b/src/southbridge/intel/i82801jx/smbus.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index 08f89e3..fbcb01d 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -13,7 +13,6 @@ #include <device/device.h> #include <device/mmio.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <string.h> diff --git a/src/southbridge/intel/ibexpeak/pch.c b/src/southbridge/intel/ibexpeak/pch.c index 958d1db..23768ed 100644 --- a/src/southbridge/intel/ibexpeak/pch.c +++ b/src/southbridge/intel/ibexpeak/pch.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include "pch.h" /* Set bit in function disable register to hide this device */ diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c index de1ad18..3318458 100644 --- a/src/southbridge/intel/ibexpeak/smbus.c +++ b/src/southbridge/intel/ibexpeak/smbus.c @@ -4,7 +4,6 @@ #include <device/path.h> #include <device/smbus.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <device/smbus_host.h> diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 216af67..40df0bd 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -3,7 +3,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pci_ids.h> #include "pch.h" #include <device/mmio.h> diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c index 91eeabd..66d56dc8 100644 --- a/src/southbridge/intel/lynxpoint/me.c +++ b/src/southbridge/intel/lynxpoint/me.c @@ -15,7 +15,6 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/pci_def.h> #include <string.h> #include <delay.h> #include <elog.h> diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index f83f3f6..8b037a9 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -4,7 +4,6 @@ #include <device/pci_ops.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include "iobp.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 2f01560..7d31b3e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -5,7 +5,6 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <device/pciexp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index dd7f199..d67fb6c 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -8,7 +8,6 @@ #include <arch/io.h> #include <device/device.h> #include <device/pci.h> -#include <device/pci_def.h> #include <console/console.h> #include <security/vboot/vbnv.h> #include <security/vboot/vboot_common.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/72626 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4e5999443e81ee1c4b1fd69942050b47f21f42f8 Gerrit-Change-Number: 72626 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jeff Daly <jeffd(a)silicom-usa.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: amdfwtool: Allow the location to be a relative address
by Bao Zheng (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: ritul guru, Zheng Bao, Fred Reitberger. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69856 ) Change subject: amdfwtool: Allow the location to be a relative address ...................................................................... Patch Set 14: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/69856/comment/4c863b77_4ebeca94 PS12, Line 2462: if (efs_location & 0xFF000000) : efs_location = efs_location - rom_base_address; : if (body_location & 0xFF000000) : body_location = body_location - rom_base_address; > My apologies, this ended up breaking 8MB ROM builds. […] Add a special case. -- To view, visit https://review.coreboot.org/c/coreboot/+/69856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Gerrit-Change-Number: 69856 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 02:52:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/qualcomm/sc7280: Memlayout change to support new Crypto sha update
by Yidi Lin (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: Venkat Thogaru, Julius Werner. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72646 ) Change subject: soc/qualcomm/sc7280: Memlayout change to support new Crypto sha update ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72646 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f5c8a79993fc1c529fae5cea4c4182663643ddd Gerrit-Change-Number: 72646 Gerrit-PatchSet: 2 Gerrit-Owner: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sudheer Amrabadi <samrabad(a)codeaurora.org> Gerrit-Attention: Venkat Thogaru <thogaru(a)qualcomm.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Feb 2023 02:46:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
by Sam McNally (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: Liam Flaherty. Sam McNally has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71882 ) Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Gerrit-Change-Number: 71882 Gerrit-PatchSet: 6 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Feb 2023 02:39:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: amdfwtool: Allow the location to be a relative address
by Bao Zheng (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: Bao Zheng, ritul guru, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69856 to look at the new patch set (#14). Change subject: amdfwtool: Allow the location to be a relative address ...................................................................... amdfwtool: Allow the location to be a relative address When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 38 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69856/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/69856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Gerrit-Change-Number: 69856 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
by Adam Mills (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: Sam McNally, Liam Flaherty. Adam Mills has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71882 ) Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71882 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Gerrit-Change-Number: 71882 Gerrit-PatchSet: 6 Gerrit-Owner: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Reviewer: Adam Mills <adamjmills(a)google.com> Gerrit-Reviewer: Sam McNally <sammc(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sam McNally <sammc(a)google.com> Gerrit-Attention: Liam Flaherty <liamflaherty(a)chromium.org> Gerrit-Comment-Date: Wed, 01 Feb 2023 02:15:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
by Prashant Malani (Code Review) Feb. 1, 2023

Feb. 1, 2023

Attention is currently required from: Jason Nien, Martin Roth. Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72654 ) Change subject: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes ...................................................................... Patch Set 1: Code-Review-1 (1 comment) Patchset: PS1: Self -1, since this is experimental and not ready for submission. -- To view, visit https://review.coreboot.org/c/coreboot/+/72654 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I712a54e8b3bee8f4ead3b6cf2b495a8dda7962ad Gerrit-Change-Number: 72654 Gerrit-PatchSet: 1 Gerrit-Owner: Prashant Malani <pmalani(a)chromium.org> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Prashant Malani <pmalani(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 02:00:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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