Prashant Malani has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72654 )
Change subject: mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
......................................................................
mb/google/skyrim/var/winterhold: Add support for AP-driven muxes
Add the platform ACPI devices needed for AP-driven Type-C mux and
retimer programming.
BUG=b:266218046
TEST=Tested on skyrim with Kconfig enabled, SSDT generated as expected.
BRANCH=None
Change-Id: I712a54e8b3bee8f4ead3b6cf2b495a8dda7962ad
---
M src/mainboard/google/skyrim/Kconfig
M src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
2 files changed, 42 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/72654/1
diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig
index d945474..19755cd 100644
--- a/src/mainboard/google/skyrim/Kconfig
+++ b/src/mainboard/google/skyrim/Kconfig
@@ -27,6 +27,7 @@
select DRIVERS_PCIE_GENERIC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_ESPI
+ select EC_GOOGLE_CHROMEEC_MUX
select EC_GOOGLE_CHROMEEC_SKUID
select EC_GOOGLE_CHROMEEC_BOARDID
select ELOG
diff --git a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
index 04da26c..7f40e32 100644
--- a/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
+++ b/src/mainboard/google/skyrim/variants/winterhold/overridetree.cb
@@ -157,6 +157,31 @@
end
end # XHCI1 controller
end # Internal GPP Bridge 0 to Bus A
+
+ device ref lpc_bridge on
+ chip ec/google/chromeec
+ use ecmux0 as retimer_conn[0]
+ use ecmux1 as retimer_conn[1]
+ use ecmux0 as mux_conn[0]
+ use ecmux1 as mux_conn[1]
+ device ref chrome_ec on
+ chip ec/google/chromeec/mux
+ device generic 0 on
+ chip ec/google/chromeec/mux/conn
+ register "mode_switch" = "true"
+ register "retimer_switch" = "true"
+ device generic 0 alias ecmux0 on end
+ end
+ chip ec/google/chromeec/mux/conn
+ register "mode_switch" = "true"
+ register "retimer_switch" = "true"
+ device generic 1 alias ecmux1 on end
+ end
+ end
+ end
+ end
+ end
+ end
end # domain
device ref i2c_0 on
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Liam Flaherty has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71882 )
Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
......................................................................
Patch Set 6:
(1 comment)
File src/mainboard/google/dedede/variants/dibbi/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71882/comment/463121a4_cbbfc9b2
PS5, Line 52: # Type-C Port A0
> is A0 the type-C port? Down further A0 refers to the first USB-A port.
This is a typo in the comment here, fixed.
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Hello Sam McNally, build bot (Jenkins), Adam Mills,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#6).
Change subject: mb/google/dedede/var/dibbi: Update devicetree and GPIO table
......................................................................
mb/google/dedede/var/dibbi: Update devicetree and GPIO table
Create overridetree and GPIO config based on latest schematic:
1. Update PCIe ports
2. Update USB ports
3. Remove unused I2Cs
4. Remove unused peripherals (SD card, eDP, speakers)
5. Add LAN
6. Thermal policy for updated temp sensors
BUG=b:260934185, b:260934719
BRANCH=dedede
TEST=build
Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe
Signed-off-by: Liam Flaherty <liamflaherty(a)chromium.org>
---
M src/mainboard/google/dedede/Kconfig.name
A src/mainboard/google/dedede/variants/dibbi/Makefile.inc
A src/mainboard/google/dedede/variants/dibbi/gpio.c
M src/mainboard/google/dedede/variants/dibbi/overridetree.cb
4 files changed, 310 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/71882/6
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Ren Kuo has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 )
Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................
Patch Set 4: Code-Review+1
(2 comments)
File src/mainboard/google/brya/variants/craask/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/71860/comment/2985ab97_069d3d77
PS3, Line 24: CPU_6W_DPTF0
> nit: `THERMAL_SOLUTION_6W` to match config. […]
fixed.
https://review.coreboot.org/c/coreboot/+/71860/comment/a263a93e_212ddc4d
PS3, Line 25: CPU_15W_DPTF1
> nit: `THERMAL_SOLUTION_15W` to match config. […]
fixed.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa/var/craask: Modify DPTF settings
......................................................................
mb/google/nissa/var/craask: Modify DPTF settings
Add ADL-N 15W CPU Power Limit(PL) settings for Craasneto
BUG=b:265101768
TEST=emerge-nissa coreboot
Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd
Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/craask/overridetree.cb
1 file changed, 74 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/71860/4
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72690 )
Change subject: soc/amd/cezanne/reset: deduplicate code
......................................................................
soc/amd/cezanne/reset: deduplicate code
do_warm_reset does the same as do_cold_reset, since warm resets aren't
supported on this platform. Instead of open coding the same cold reset
functionality again, call do_cold_reset from do_warm_reset. This also
brings do_warm_reset in line with do_board_reset.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: Ie3fe010a2b361ae9a1befeb4f07b12a80d978460
---
M src/soc/amd/cezanne/reset.c
1 file changed, 16 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/72690/1
diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c
index 1360bd5..ac0c981 100644
--- a/src/soc/amd/cezanne/reset.c
+++ b/src/soc/amd/cezanne/reset.c
@@ -18,9 +18,7 @@
void do_warm_reset(void)
{
/* Warm resets are not supported and must be executed as cold */
- pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
- TOGGLE_ALL_PWR_GOOD);
- outb(RST_CPU | SYS_RST, RST_CNT);
+ do_cold_reset();
}
void do_board_reset(void)
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Change subject: soc/amd/mendocino: Force resets to be cold
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/amd/mendocino: Force resets to be cold
......................................................................
Patch Set 3:
(1 comment)
File src/soc/amd/mendocino/fch.c:
https://review.coreboot.org/c/coreboot/+/72486/comment/877ae74a_cd611567
PS3, Line 131: pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
> It sounds like `fch_init_resets()` should be dropped from this CL then, since we aren't doing warm r […]
no, fch_init_resets is essential to make sure that that bit to change the reset behavior is still set in the case when coreboot doesn't do a reset which should be the main case. i'd still set this bit in the do_*_rest functions, so that those also behave correctly before the fch_init_resets call
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Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72649 )
Change subject: include/cpu/amd/mtrr: drop unused TOP_MEM_MASK definitions
......................................................................
include/cpu/amd/mtrr: drop unused TOP_MEM_MASK definitions
Neither TOP_MEM_MASK nor TOP_MEM_MASK_KB is used, so drop the two
definitions.
Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de>
Change-Id: I0b2dfb7be27884dffb948876aabb73f99834c281
---
M src/include/cpu/amd/mtrr.h
1 file changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/72649/1
diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h
index bc3f313..f1b95b6 100644
--- a/src/include/cpu/amd/mtrr.h
+++ b/src/include/cpu/amd/mtrr.h
@@ -37,9 +37,6 @@
#define TOP_MEM2 0xC001001Dul
#endif
-#define TOP_MEM_MASK 0x007fffff
-#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-
#if !defined(__ASSEMBLER__)
#include <cpu/x86/msr.h>
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