coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

1 participants
5082 discussions

[M] Change in coreboot[master]: soc/intel/xeon_sp: move PCH specific code into lbg directory
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, David Hendricks, Christian Walter, Angel Pons, Arthur Heymans, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72396 ) Change subject: soc/intel/xeon_sp: move PCH specific code into lbg directory ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72396 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b357ce877123530dd5c310a730808b6e651712e Gerrit-Change-Number: 72396 Gerrit-PatchSet: 3 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:17:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: configs/builder: add default config for Intel Archer City CRB
by Simon Chou (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Chu. Simon Chou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71969 ) Change subject: configs/builder: add default config for Intel Archer City CRB ...................................................................... Patch Set 7: (1 comment) File configs/builder/config.intel.crb.ac: https://review.coreboot.org/c/coreboot/+/71969/comment/8a40e78b_f9495993 PS2, Line 14: CONFIG_FSP_T_FILE="site-local/archercity/Server_T.fd" : CONFIG_FSP_M_FILE="site-local/archercity/Server_M.fd" : CONFIG_FSP_S_FILE="site-local/archercity/Server_S.fd" : CONFIG_IFD_BIN_PATH="site-local/archercity/descriptor.bin" : CONFIG_ME_BIN_PATH="site-local/archercity/me.bin" : CONFIG_CPU_UCODE_BINARIES="site-local/archercity/mbf806f8.mcb" > Yes OCP Delta Lake also has these and can be built by the builder somehow. […] Hi Paul, could you check whether you question got answered? -- To view, visit https://review.coreboot.org/c/coreboot/+/71969 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I15aefc3edb2d22fc00d854850e948fe2048a992e Gerrit-Change-Number: 71969 Gerrit-PatchSet: 7 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:15:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/amd/phoenix: Allow the amdfw.rom to be split into two parts
by Bao Zheng (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72703 to review the following change. Change subject: soc/amd/phoenix: Allow the amdfw.rom to be split into two parts ...................................................................... soc/amd/phoenix: Allow the amdfw.rom to be split into two parts Split the big PSP FW data into two parts, head and body. The head needs to be located at specific location. The body address is more flexible. So the EC FW can be put to the address like 0x80000. Need 1K extra space for the region header or something. Change-Id: Ia8b318f71632a2c9b97ce67486374dc24d23e63e Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/phoenix/Makefile.inc 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/72703/1 diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 1c24243..d8bce29 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -213,6 +213,8 @@ # If vboot uses 2 RW slots, then 2 copies of PSP binaries are redundant OPT_RECOVERY_AB_SINGLE_COPY=$(if $(CONFIG_VBOOT_SLOTS_RW_AB), --recovery-ab-single-copy) +OPT_AMDFW_BODY_LOCATION=$(if $(CONFIG_AMDFW_BODY_LOCATION), --body-location $(CONFIG_AMDFW_BODY_LOCATION)) + AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_APOB_ADDR) \ $(OPT_PSP_BIOSBIN_FILE) \ @@ -233,7 +235,8 @@ --config $(CONFIG_AMDFW_CONFIG_FILE) \ --soc-name "Phoenix" \ --flashsize $(CONFIG_ROM_SIZE) \ - $(OPT_RECOVERY_AB_SINGLE_COPY) + $(OPT_RECOVERY_AB_SINGLE_COPY) \ + $(OPT_AMDFW_BODY_LOCATION) $(obj)/amdfw.rom: $(call strip_quotes, $(PSP_BIOSBIN_FILE)) \ $(PSP_VERSTAGE_FILE) \ @@ -256,6 +259,17 @@ --location $(shell printf "%#x" $(PHOENIX_FWM_POSITION)) \ --output $@ +ifneq ($(CONFIG_AMDFW_BODY_LOCATION)y,y) +$(obj)/amdfw.rom.body: $(obj)/amdfw.rom + +regions-for-file-apu/amdfwbody=AMDFWBODY + +cbfs-files-y += apu/amdfwbody +apu/amdfwbody-file := $(obj)/amdfw.rom.body +apu/amdfwbody-position := 1024 +apu/amdfwbody-type := raw +endif + $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/72703 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia8b318f71632a2c9b97ce67486374dc24d23e63e Gerrit-Change-Number: 72703 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: amdfwtool: Change .rom.efs to .rom and .rom to .rom.body
by Bao Zheng (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Zheng Bao, Fred Reitberger, Felix Held. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72702 to review the following change. Change subject: amdfwtool: Change .rom.efs to .rom and .rom to .rom.body ...................................................................... amdfwtool: Change .rom.efs to .rom and .rom to .rom.body The non-vboot also need to split amdfw. Keep the default filename which is located at EFS. Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/mendocino/Makefile.inc M util/amdfwtool/amdfwtool.c 2 files changed, 48 insertions(+), 41 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/72702/1 diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 7d7033a..4408b98 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -165,8 +165,8 @@ SIGNED_AMDFW_B_POSITION=$(call int-subtract, \ $(shell awk '$$2 == "FMAP_SECTION_SIGNED_AMDFW_B_START" {print $$3}' $(obj)/fmap_config.h) \ $(shell awk '$$2 == "FMAP_SECTION_FLASH_START" {print $$3}' $(obj)/fmap_config.h)) -SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.signed -SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.signed +SIGNED_AMDFW_A_FILE=$(obj)/amdfw_a.rom.body.signed +SIGNED_AMDFW_B_FILE=$(obj)/amdfw_b.rom.body.signed endif # CONFIG_SEPARATE_SIGNED_PSPFW # Helper function to return a value with given bit set @@ -301,41 +301,41 @@ --anywhere \ --output $@ -$(obj)/amdfw_a.rom.efs: $(obj)/amdfw_a.rom -$(obj)/amdfw_b.rom.efs: $(obj)/amdfw_b.rom +$(obj)/amdfw_a.rom.body: $(obj)/amdfw_a.rom +$(obj)/amdfw_b.rom.body: $(obj)/amdfw_b.rom ifeq ($(CONFIG_VBOOT_SLOTS_RW_A)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a -apu/amdfw_a-file := $(obj)/amdfw_a.rom.efs +apu/amdfw_a-file := $(obj)/amdfw_a.rom apu/amdfw_a-position := $(AMD_FW_AB_POSITION) apu/amdfw_a-type := raw cbfs-files-y += apu/amdfw_a_body -apu/amdfw_a_body-file := $(obj)/amdfw_a.rom +apu/amdfw_a_body-file := $(obj)/amdfw_a.rom.body apu/amdfw_a_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) apu/amdfw_a_body-type := raw endif ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_b -apu/amdfw_b-file := $(obj)/amdfw_b.rom.efs +apu/amdfw_b-file := $(obj)/amdfw_b.rom apu/amdfw_b-position := $(AMD_FW_AB_POSITION) apu/amdfw_b-type := raw cbfs-files-y += apu/amdfw_b_body -apu/amdfw_b_body-file := $(obj)/amdfw_b.rom +apu/amdfw_b_body-file := $(obj)/amdfw_b.rom.body apu/amdfw_b_body-position := $(call int-add, $(AMD_FW_AB_POSITION) $(MENDOCINO_FW_BODY_OFFSET)) apu/amdfw_b_body-type := raw endif ifeq ($(CONFIG_SEPARATE_SIGNED_PSPFW)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) -build_complete:: $(obj)/amdfw_a.rom $(obj)/amdfw_b.rom +build_complete:: $(obj)/amdfw_a.rom.body $(obj)/amdfw_b.rom.body @printf " Adding Signed ROM and HASH\n" - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.signed - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.signed.hash \ + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_A -i 0 -f $(obj)/amdfw_a.rom.body.signed + $(CBFSTOOL) $(obj)/coreboot.rom write -u -r SIGNED_AMDFW_B -i 0 -f $(obj)/amdfw_b.rom.body.signed + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_A -f $(obj)/amdfw_a.rom.body.signed.hash \ -n apu/amdfw_a_hash -t raw - $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.signed.hash \ + $(CBFSTOOL) $(obj)/coreboot.rom add -r FW_MAIN_B -f $(obj)/amdfw_b.rom.body.signed.hash \ -n apu/amdfw_b_hash -t raw endif diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7605f30..562ed22 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -111,7 +111,7 @@ #define HASH_FILE_SUFFIX ".hash" #define EFS_FILE_SUFFIX ".efs" #define TMP_FILE_SUFFIX ".tmp" - +#define BODY_FILE_SUFFIX ".body" /* * Beginning with Family 15h Models 70h-7F, a.k.a Stoney Ridge, the PSP * can support an optional "combo" implementation. If the PSP sees the @@ -2019,48 +2019,48 @@ return 0; } -static ssize_t write_efs(char *output, embedded_firmware *amd_romsig) +static ssize_t write_body(char *output, embedded_firmware *amd_romsig, ssize_t body_size) { - char efs_name[PATH_MAX], efs_tmp_name[PATH_MAX]; + char body_name[PATH_MAX], body_tmp_name[PATH_MAX]; int ret; int fd; ssize_t bytes = -1; /* Create a tmp file and rename it at the end so that make does not get confused if amdfwtool is killed for some unexpected reasons. */ - ret = snprintf(efs_tmp_name, sizeof(efs_tmp_name), "%s%s%s", - output, EFS_FILE_SUFFIX, TMP_FILE_SUFFIX); + ret = snprintf(body_tmp_name, sizeof(body_tmp_name), "%s%s%s", + output, BODY_FILE_SUFFIX, TMP_FILE_SUFFIX); if (ret < 0) { - fprintf(stderr, "Error %s forming EFS tmp file name: %d\n", + fprintf(stderr, "Error %s forming BODY tmp file name: %d\n", strerror(errno), ret); exit(1); - } else if ((unsigned int)ret >= sizeof(efs_tmp_name)) { - fprintf(stderr, "EFS File name %d > %zu\n", ret, sizeof(efs_tmp_name)); + } else if ((unsigned int)ret >= sizeof(body_tmp_name)) { + fprintf(stderr, "BODY File name %d > %zu\n", ret, sizeof(body_tmp_name)); exit(1); } - fd = open(efs_tmp_name, O_RDWR | O_CREAT | O_TRUNC, 0666); + fd = open(body_tmp_name, O_RDWR | O_CREAT | O_TRUNC, 0666); if (fd < 0) { - fprintf(stderr, "Error: Opening %s file: %s\n", efs_tmp_name, strerror(errno)); + fprintf(stderr, "Error: Opening %s file: %s\n", body_tmp_name, strerror(errno)); exit(1); } - bytes = write_from_buf_to_file(fd, amd_romsig, sizeof(*amd_romsig)); - if (bytes != sizeof(*amd_romsig)) { - fprintf(stderr, "Error: Writing to file %s failed\n", efs_tmp_name); + bytes = write_from_buf_to_file(fd, amd_romsig, body_size); + if (bytes != body_size) { + fprintf(stderr, "Error: Writing to file %s failed\n", body_tmp_name); exit(1); } close(fd); /* Rename the tmp file */ - ret = snprintf(efs_name, sizeof(efs_name), "%s%s", output, EFS_FILE_SUFFIX); + ret = snprintf(body_name, sizeof(body_name), "%s%s", output, BODY_FILE_SUFFIX); if (ret < 0) { - fprintf(stderr, "Error %s forming EFS file name: %d\n", strerror(errno), ret); + fprintf(stderr, "Error %s forming BODY file name: %d\n", strerror(errno), ret); exit(1); } - if (rename(efs_tmp_name, efs_name)) { - fprintf(stderr, "Error: renaming file %s to %s\n", efs_tmp_name, efs_name); + if (rename(body_tmp_name, body_name)) { + fprintf(stderr, "Error: renaming file %s to %s\n", body_tmp_name, body_name); exit(1); } @@ -2677,11 +2677,11 @@ targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { - ssize_t bytes; - uint32_t offset = body_location ? body_location : AMD_ROMSIG_OFFSET; + uint32_t offset = efs_location; + uint32_t bytes = efs_location == body_location ? ctx.current - offset : sizeof(*amd_romsig), ret_bytes; - bytes = write(targetfd, BUFF_OFFSET(ctx, offset), ctx.current - offset); - if (bytes != ctx.current - offset) { + ret_bytes = write(targetfd, BUFF_OFFSET(ctx, offset), bytes); + if (bytes != ret_bytes) { fprintf(stderr, "Error: Writing to file %s failed\n", output); retval = 1; } @@ -2692,13 +2692,7 @@ } if (efs_location != body_location) { - ssize_t bytes; - - bytes = write_efs(output, amd_romsig); - if (bytes != sizeof(*amd_romsig)) { - fprintf(stderr, "Error: Writing EFS\n"); - retval = 1; - } + write_body(output, BUFF_OFFSET(ctx, body_location), ctx.current - body_location); } free(rom); -- To view, visit https://review.coreboot.org/c/coreboot/+/72702 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id77b11422d4549cf57a1cd8980c7a9cf3597d1bc Gerrit-Change-Number: 72702 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[S] Change in coreboot[master]: amdfwtool: Remove the limit of spliting EFS and body
by Bao Zheng (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held. Hello Jason Glenesk, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69857 to look at the new patch set (#4). Change subject: amdfwtool: Remove the limit of spliting EFS and body ...................................................................... amdfwtool: Remove the limit of spliting EFS and body Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 10 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/69857/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/69857 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic058cfaeebd1a947227cfa9be2db4eb22702aa28 Gerrit-Change-Number: 69857 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

1 0

[S] Change in coreboot[master]: crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
by Felix Singer (Code Review) 01 Feb '23

01 Feb '23

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71884 ) Change subject: crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7 ...................................................................... crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7 Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71884 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc D util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum D util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum A util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum D util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum A util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum 11 files changed, 19 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Felix Singer: Looks good to me, approved diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index cfbe0e8..0de27ed 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -41,7 +41,7 @@ BINUTILS_VERSION=2.37 IASL_VERSION="R10_20_22" # CLANG version number -CLANG_VERSION=15.0.6 +CLANG_VERSION=15.0.7 CMAKE_VERSION=3.25.2 NASM_VERSION=2.15.05 diff --git a/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum deleted file mode 100644 index 8a98168..0000000 --- a/util/crossgcc/sum/clang-15.0.6.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f8bf6effb93f45fc66cfc4e9e0e160b7845dd9d6 tarballs/clang-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum b/util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum new file mode 100644 index 0000000..b022056 --- /dev/null +++ b/util/crossgcc/sum/clang-15.0.7.src.tar.xz.cksum @@ -0,0 +1 @@ +7b4d1188cce1ce4ea1cf2ea362fba685c4aca34d tarballs/clang-15.0.7.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum deleted file mode 100644 index 60d65a6..0000000 --- a/util/crossgcc/sum/clang-tools-extra-15.0.6.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -bd3df3ff940ea928f74c467691be0e68c5fc014e tarballs/clang-tools-extra-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum new file mode 100644 index 0000000..ac786926 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-15.0.7.src.tar.xz.cksum @@ -0,0 +1 @@ +752fe847136eff2dfbfcc8bbddfaa9319532d104 tarballs/clang-tools-extra-15.0.7.src.tar.xz diff --git a/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum deleted file mode 100644 index 43c36a3..0000000 --- a/util/crossgcc/sum/cmake-15.0.6.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -507185c7c4ce9cd6f4926b05b869fe3e8c945041 tarballs/cmake-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum b/util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum new file mode 100644 index 0000000..0a9cce4 --- /dev/null +++ b/util/crossgcc/sum/cmake-15.0.7.src.tar.xz.cksum @@ -0,0 +1 @@ +8f06060871953422820098346da9a3b63b90120d tarballs/cmake-15.0.7.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum deleted file mode 100644 index 53c1413..0000000 --- a/util/crossgcc/sum/compiler-rt-15.0.6.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ff5f8cdcfc6fbc5c0a68a76da33c88fd3f272951 tarballs/compiler-rt-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum new file mode 100644 index 0000000..9facd1d --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-15.0.7.src.tar.xz.cksum @@ -0,0 +1 @@ +40f2a886636168f6478e20933906bcece2fd6b97 tarballs/compiler-rt-15.0.7.src.tar.xz diff --git a/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum b/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum deleted file mode 100644 index d5cb9a6..0000000 --- a/util/crossgcc/sum/llvm-15.0.6.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -60e9a385dde9a10e6ef7009ce342a119d3432eef tarballs/llvm-15.0.6.src.tar.xz diff --git a/util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum b/util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum new file mode 100644 index 0000000..74eb76c --- /dev/null +++ b/util/crossgcc/sum/llvm-15.0.7.src.tar.xz.cksum @@ -0,0 +1 @@ +497ca3b2010cc0e3e38bc9dc6dda19041dbd7066 tarballs/llvm-15.0.7.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/71884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707 Gerrit-Change-Number: 71884 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7
by Felix Singer (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Martin L Roth, Paul Menzel, Elyes Haouas. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71884 ) Change subject: crossgcc: Upgrade LLVM version 15.0.6 to 15.0.7 ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71884 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3198b065316b98f2d26360c4e65055e7460ea707 Gerrit-Change-Number: 71884 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Wed, 01 Feb 2023 06:06:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: mb/intel/mtlrvp: Modify the print message
by Sridhar Siricilla (Code Review) 01 Feb '23

01 Feb '23

Sridhar Siricilla has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72638 ) Change subject: mb/intel/mtlrvp: Modify the print message ...................................................................... mb/intel/mtlrvp: Modify the print message This patch updates the print message to start with uppercase, 'board' to 'Board'. BUG=b:224325352 BRANCH=None TEST=Able to observe proper print message when invalid board id is configured. Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/intel/mtlrvp/romstage.c 1 file changed, 24 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Sridhar Siricilla: Looks good to me, approved Usha P: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/romstage.c b/src/mainboard/intel/mtlrvp/romstage.c index b5bb777..e2acfd0 100644 --- a/src/mainboard/intel/mtlrvp/romstage.c +++ b/src/mainboard/intel/mtlrvp/romstage.c @@ -12,7 +12,7 @@ uint8_t board_id = get_rvp_board_id(); size_t spd_index; - printk(BIOS_INFO, "board id is 0x%x\n", board_id); + printk(BIOS_INFO, "Board id is 0x%x\n", board_id); spd_index = board_id & SPD_ID_MASK; -- To view, visit https://review.coreboot.org/c/coreboot/+/72638 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Gerrit-Change-Number: 72638 Gerrit-PatchSet: 3 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-MessageType: merged

1 0

[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable CNVi BT Core and Wifi for mtlrvp
by Harsha B R (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jamie Ryu. Hello Jamie Ryu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72695 to review the following change. Change subject: mb/intel/mtlrvp: Enable CNVi BT Core and Wifi for mtlrvp ...................................................................... mb/intel/mtlrvp: Enable CNVi BT Core and Wifi for mtlrvp This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics. 1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to chromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/72695/1 diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8cdbeea..15cdee1 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -36,6 +36,9 @@ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" + # Enable CNVi BT + register "cnvi_bt_core" = "true" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -63,6 +66,15 @@ }" end # PCIE11 SSD Gen4 device ref xhci on end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on end device ref i2c1 on end device ref i2c2 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/72695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Gerrit-Change-Number: 72695 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: vc/amd/pi: Fix "No such file or directory"
by build bot (Jenkins) (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Martin L Roth, Arthur Heymans. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71855 ) Change subject: vc/amd/pi: Fix "No such file or directory" ...................................................................... Patch Set 5: (9 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/2b71cd23_ac4c8e28 PS5, Line 9: Fix: Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/f300ac90_37bd5f0f PS5, Line 10: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/9314c3b0_41db09b1 PS5, Line 11: cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/8ef9eec3_61560166 PS5, Line 12: cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/62017d33_e8aeef88 PS5, Line 13: cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/e7d0de3c_4a87a3a9 PS5, Line 14: cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/bc3c20ab_a9cfb3cb PS5, Line 15: cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/d769a554_2e3aec3a PS5, Line 16: cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169631): https://review.coreboot.org/c/coreboot/+/71855/comment/d5606bf6_54221c30 PS5, Line 17: cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/71855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Gerrit-Change-Number: 71855 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 05:16:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit February 2023