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Change subject: ifdtool: Introduce region_name_fmap
......................................................................
Patch Set 7: Code-Review+2
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Change subject: ifdtool: Drop chipset without IFD
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Patch Set 7: Code-Review+2
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Change subject: util/ifdtool: Add Wellsburg support
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68657/comment/fb15df93_b1a3149c
PS1, Line 9: is IFDv2 compatible
> Is it, though?
Unfortunately there is no Intel doc mention anything about this despite best effort in finding them, feel free to provide if anyone has any. However from the testing it seems yes.
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Change subject: util/ifdtool: Add Wellsburg support
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Patch Set 6: Code-Review+2
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Change subject: soc/intel/xeon_sp/spr: add ACPI code
......................................................................
Patch Set 13:
(1 comment)
File src/soc/intel/xeon_sp/spr/soc_acpi.c:
https://review.coreboot.org/c/coreboot/+/71967/comment/b8022d04_7b70a722
PS13, Line 387: for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) {
This must be CONFIG_MAX_SOCKET to prevent ACPI errors when not all CPUs are plugged on a multi socket system.
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Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/elkhartlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/72404/comment/bcb89aa8_02acf201
PS2, Line 159: if (CONFIG_TTYS0_BASE == 0x3f8)
: m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
: else if (CONFIG_TTYS0_BASE == 0x2f8)
: m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_2F8;
> According to the EHL FSP code, other I/O base addresses than 0x3f8 and 0x2f8 are not supported.
Yes I know, but since the other 2 configs are exposed they should be handled as well. Or only allows EHL to choose from 2 configs instead of 4.
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Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72610 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/prodrive/atlas/data.vbt: Fix VBT lane count
......................................................................
mb/prodrive/atlas/data.vbt: Fix VBT lane count
Currently there is a problem, where two Displayports are not working. To
be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working.
Setting the lane count of the TCP0 and TCP1 to x1 works fine.
Setting the lane count of the TCP0 and TCP1 to x2 does not work.
Setting the lane count of the TCP0 and TCP1 to x4 does not work.
The reason for that is currently unknown.
This change sets the lane count of the TCP0 and TCP1 Port to x1 length
in the VBT binary.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I182b528275152bf5adcb01a56816afd65674aed3
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610
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Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/prodrive/atlas/data.vbt
1 file changed, 25 insertions(+), 0 deletions(-)
Approvals:
build bot (Jenkins): Verified
Lean Sheng Tan: Looks good to me, approved
diff --git a/src/mainboard/prodrive/atlas/data.vbt b/src/mainboard/prodrive/atlas/data.vbt
index 9c4aa8a..da78bfc 100644
--- a/src/mainboard/prodrive/atlas/data.vbt
+++ b/src/mainboard/prodrive/atlas/data.vbt
Binary files differ
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Hello build bot (Jenkins), Zheng Bao,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/69856
to look at the new patch set (#15).
Change subject: amdfwtool: Allow the location to be a relative address
......................................................................
amdfwtool: Allow the location to be a relative address
When the BIOS size is more than 32M, the physical address of EFS
header will be complicated, like 0xfe020000 or 0xfc020000. So we make
it simpler to allow to use relative address.
This CL works with https://review.coreboot.org/c/coreboot/+/69852
Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
1 file changed, 39 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69856/15
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