coreboot-gerrit February 2023

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface
by Harsha B R (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jamie Ryu, Paul Menzel, Sridhar Siricilla, Usha P, Eric Lai. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72706 ) Change subject: mb/intel/mtlrvp: Enable GSPI interface ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/72706/comment/d25a322f_f26b472b PS1, Line 7: for mtlrvp > Redundant as in prefix. Ack https://review.coreboot.org/c/coreboot/+/72706/comment/38188793_e56e39d5 PS1, Line 9: GSPI[1] > Please add a space before the [. Ack https://review.coreboot.org/c/coreboot/+/72706/comment/8a8fc868_ae53efc1 PS1, Line 15: chromeOS > ChromeOS Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/72706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Gerrit-Change-Number: 72706 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 14:51:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable GSPI interface
by Harsha B R (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jamie Ryu, Harsha B R, Sridhar Siricilla, Usha P, Eric Lai. Hello Jamie Ryu, Sridhar Siricilla, Usha P, Eric Lai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72706 to look at the new patch set (#2). Change subject: mb/intel/mtlrvp: Enable GSPI interface ...................................................................... mb/intel/mtlrvp: Enable GSPI interface This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 43 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/72706/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72706 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Gerrit-Change-Number: 72706 Gerrit-PatchSet: 2 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Usha P <usha.p(a)intel.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: mb/prodrive/hermes: Add SATA hotplug EEPROM setting
by Justin van Son (Code Review) 01 Feb '23

01 Feb '23

Justin van Son has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72712 ) Change subject: mb/prodrive/hermes: Add SATA hotplug EEPROM setting ...................................................................... mb/prodrive/hermes: Add SATA hotplug EEPROM setting Add an option to the EEPROM to configure SATA hotplug. Per port configuration is not needed, so add a global option to toggle the hotplug setting on all SATA ports. Change-Id: Ib7dcd12049bdf7c2d200530acd8a6da5df726203 Signed-off-by: Justin van Son <justin.van.son(a)prodrive-technologies.com> --- M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c 2 files changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/72712/1 diff --git a/src/mainboard/prodrive/hermes/eeprom.h b/src/mainboard/prodrive/hermes/eeprom.h index f02206f..82d56d3 100644 --- a/src/mainboard/prodrive/hermes/eeprom.h +++ b/src/mainboard/prodrive/hermes/eeprom.h @@ -60,8 +60,9 @@ uint8_t pink_rear_vref; uint8_t vtx_disabled; uint8_t boot_menu_disabled; + uint8_t sata_hotplug; }; - uint8_t raw_settings[12]; + uint8_t raw_settings[13]; }; }; @@ -70,7 +71,7 @@ PRIMARY_VIDEO_INTEL = 1, }; -_Static_assert(sizeof(struct eeprom_board_settings) == (12 + sizeof(uint32_t)), +_Static_assert(sizeof(struct eeprom_board_settings) == (13 + sizeof(uint32_t)), "struct eeprom_board_settings has invalid size!"); struct __packed eeprom_bmc_settings { diff --git a/src/mainboard/prodrive/hermes/mainboard.c b/src/mainboard/prodrive/hermes/mainboard.c index 0b0eb88..9e2b111 100644 --- a/src/mainboard/prodrive/hermes/mainboard.c +++ b/src/mainboard/prodrive/hermes/mainboard.c @@ -143,6 +143,17 @@ printk(BIOS_ERR, "MB: Failed to update Board Layout\n"); } +static void mainboard_set_sata_hotplug(bool on) +{ + uint8_t sata_hotplug[] = { 1, 1, 0, 0, 1, 1, 1, 1 }; + config_t *config = config_of_soc(); + + if (!on) + memset(sata_hotplug, 0, sizeof(sata_hotplug)); + + memcpy(config->SataPortsHotPlug, sata_hotplug, sizeof(sata_hotplug)); +} + static void mainboard_init(void *chip_info) { const struct eeprom_board_settings *const board_cfg = get_board_settings(); @@ -166,6 +177,11 @@ if (!board_cfg) return; + /* 0: Disable SATA hotplug, 1: Enable SATA hotplug. For all ports.*/ + const bool hotplug = board_cfg->sata_hotplug; + + mainboard_set_sata_hotplug(hotplug); + /* Encoding: 0 -> S0, 1 -> S5 */ const bool on = !board_cfg->power_state_after_g3; -- To view, visit https://review.coreboot.org/c/coreboot/+/72712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7dcd12049bdf7c2d200530acd8a6da5df726203 Gerrit-Change-Number: 72712 Gerrit-PatchSet: 1 Gerrit-Owner: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config
by Yidi Lin (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. Hello Julius Werner, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72711 to look at the new patch set (#2). Change subject: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config ...................................................................... vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementation. This will speed up firmware verification in verstage. [1] https://crrev.com/c/4170144 BUG=b:263514393 TEST='calculating body hash (SHA2)' get 13 msecs improvement on Tentacruel. Before: 509:finished calculating body hash (SHA2) 161,548 (14,490) After: 509:finished calculating body hash (SHA2) 155,101 (1,187) Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/72711/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Gerrit-Change-Number: 72711 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: libpayload: Add VBOOT_SHA_ARMV8_CE config
by Yidi Lin (Code Review) 01 Feb '23

01 Feb '23

Yidi Lin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/72710 ) Change subject: libpayload: Add VBOOT_SHA_ARMV8_CE config ...................................................................... libpayload: Add VBOOT_SHA_ARMV8_CE config Add Kconfig option for VBOOT_SHA_ARMV8_CE, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementation. [1] https://crrev.com/c/4170144 BUG=b:263514393 TEST='vboot kernel verification' gets 111 msecs improvement on Tentacruel. Before: 1100:finished vboot kernel verification 905,150 (123,518) After: 1100:finished vboot kernel verification 787,277 (12,254) Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M payloads/libpayload/vboot/Kconfig M payloads/libpayload/vboot/Makefile.inc 2 files changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/72710/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Gerrit-Change-Number: 72710 Gerrit-PatchSet: 2 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: libpayload: Add VBOOT_SHA_ARMV8_CE config
by build bot (Jenkins) (Code Review) 01 Feb '23

01 Feb '23

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72710 ) Change subject: libpayload: Add VBOOT_SHA_ARMV8_CE config ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169654): https://review.coreboot.org/c/coreboot/+/72710/comment/93684614_37b30291 PS1, Line 14: BUG=b:263514393 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Gerrit-Change-Number: 72710 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 01 Feb 2023 14:00:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config
by build bot (Jenkins) (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72711 ) Change subject: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config ...................................................................... Patch Set 1: (2 comments) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169653): https://review.coreboot.org/c/coreboot/+/72711/comment/7eb1f3d9_c220b7f3 PS1, Line 10: use ARMv8 Crypto Extension for SHA256[1] instead of software 'implementatin' may be misspelled - perhaps 'implementation'? Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169653): https://review.coreboot.org/c/coreboot/+/72711/comment/ac6a1210_bef0e990 PS1, Line 17: BUG=b:263514393 Possible unwrapped commit description (prefer a maximum 72 chars per line) -- To view, visit https://review.coreboot.org/c/coreboot/+/72711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Gerrit-Change-Number: 72711 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 13:59:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config
by Yidi Lin (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Julius Werner, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72711 ) Change subject: vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config ...................................................................... vboot: Add VBOOT_ARMV8_CE_SHA256_ACCELERATION config Add Kconfig option for VBOOT_ARMV8_CE_SHA256_ACCELERATION, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementatin. This will speed up firmware verification in verstage. [1] https://crrev.com/c/4170144 BUG=b:263514393 TEST='calculating body hash (SHA2)' get 13 msecs improvement on Tentacruel. Before: 509:finished calculating body hash (SHA2) 161,548 (14,490) After: 509:finished calculating body hash (SHA2) 155,101 (1,187) Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/security/vboot/Kconfig M src/security/vboot/Makefile.inc 2 files changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/72711/1 diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 9025979..af51083 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -291,6 +291,13 @@ Use sha256msg1, sha256msg2, sha256rnds2 instruction to accelerate SHA hash calculation in vboot. +config VBOOT_ARMV8_CE_SHA256_ACCELERATION + bool "Use ARMv8 Crypto Extension for sha256 hash calculation" + default n + depends on ARCH_ARM64 + help + Use ARMv8 Crypto Extension to accelerate SHA hash calculation in vboot. + config VBOOT_DEFINE_WIDEVINE_COUNTERS bool default n diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc index 8747e02..616e6c8 100644 --- a/src/security/vboot/Makefile.inc +++ b/src/security/vboot/Makefile.inc @@ -30,6 +30,7 @@ EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ X86_SHA_EXT="$(if $(CONFIG_ARCH_$(call toupper,$(1))_X86_32)$(CONFIG_ARCH_$(call toupper,$(1))_X86_64),$\ $(CONFIG_VBOOT_X86_SHA256_ACCELERATION))" \ + SHA_ARMV8_CE="$(if $(CONFIG_ARCH_$(call toupper,$(1))_ARMV8_64),$$(CONFIG_VBOOT_ARMV8_CE_SHA256_ACCELERATION))" \ $(MAKE) -C $(VBOOT_SOURCE) \ BUILD=$$(abspath $$(dir $$(VBOOT_LIB_$(1)))) \ V=$(V) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/72711 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I02671338fd9e0deb5294dbb7c03528061edc18c4 Gerrit-Change-Number: 72711 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: libpayload: Add VBOOT_SHA_ARMV8_CE config
by Yidi Lin (Code Review) 01 Feb '23

01 Feb '23

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72710 ) Change subject: libpayload: Add VBOOT_SHA_ARMV8_CE config ...................................................................... libpayload: Add VBOOT_SHA_ARMV8_CE config Add Kconfig option for VBOOT_SHA_ARMV8_CE, which will use ARMv8 Crypto Extension for SHA256[1] instead of software implementation. [1] https://crrev.com/c/4170144 BUG=b:263514393 TEST='vboot kernel verification' gets 111 msecs improvement on Tentacruel. Before: 1100:finished vboot kernel verification 905,150 (123,518) After: 1100:finished vboot kernel verification 787,277 (12,254) Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M payloads/libpayload/vboot/Kconfig M payloads/libpayload/vboot/Makefile.inc 2 files changed, 32 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/72710/1 diff --git a/payloads/libpayload/vboot/Kconfig b/payloads/libpayload/vboot/Kconfig index e712fbb..3b02155 100644 --- a/payloads/libpayload/vboot/Kconfig +++ b/payloads/libpayload/vboot/Kconfig @@ -24,4 +24,12 @@ This option enables SHA256 implementation using x86 SHA processor extension instructions: sha256msg1, sha256msg2, sha256rnds2. +config VBOOT_SHA_ARMV8_CE + bool "SHA256 implementation using ARMv8 Crypto Extension" + default y if CHROMEOS + default n + depends on ARCH_ARM64 + help + This option enables SHA256 implementation using ARMv8 Crypto Extension. + endif diff --git a/payloads/libpayload/vboot/Makefile.inc b/payloads/libpayload/vboot/Makefile.inc index 3ec3278..38bad4d 100644 --- a/payloads/libpayload/vboot/Makefile.inc +++ b/payloads/libpayload/vboot/Makefile.inc @@ -37,6 +37,7 @@ $(MAKE) -C "$(VBOOT_SOURCE)" \ TPM2_MODE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_TPM2_MODE)) \ X86_SHA_EXT=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_X86_SHA_EXT)) \ + SHA_ARMV8_CE=$(call kconfig-to-binary, $(CONFIG_LP_VBOOT_SHA_ARMV8_CE)) \ UNROLL_LOOPS=1 \ BUILD="$(VBOOT_BUILD_DIR)" \ V=$(V) \ -- To view, visit https://review.coreboot.org/c/coreboot/+/72710 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If92830830a0658dfad2a066e9efa624783865cf2 Gerrit-Change-Number: 72710 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: amdfwtool: Allow the location to be a relative address
by Bao Zheng (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bao Zheng, ritul guru, Zheng Bao. Hello build bot (Jenkins), Zheng Bao, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/69856 to look at the new patch set (#16). Change subject: amdfwtool: Allow the location to be a relative address ...................................................................... amdfwtool: Allow the location to be a relative address When the BIOS size is more than 32M, the physical address of EFS header will be complicated, like 0xfe020000 or 0xfc020000. So we make it simpler to allow to use relative address. This CL works with https://review.coreboot.org/c/coreboot/+/69852 Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 43 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/69856/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/69856 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4308ec9ea05a87329aba0b409508c79ebf42325c Gerrit-Change-Number: 69856 Gerrit-PatchSet: 16 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2023