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Change subject: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
......................................................................
Patch Set 7:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72670/comment/884b9732_4fef1c47
PS6, Line 9: Add a new eventLog type of ELOG_TYPE_FW_EARLY_SOL
: to support logging when we show early signs of life to
: the user.
> Please re-flow for 72 characters per line.
Done
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Hello build bot (Jenkins), Subrata Banik, Nick Vaccaro,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72670
to look at the new patch set (#7).
Change subject: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
......................................................................
commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
Add a new eventLog type of ELOG_TYPE_FW_EARLY_SOL to support logging
when we show early signs of life to the user.
BUG=b:266113626
TEST=event shows in eventlog after CSE sync and/or MRC
Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c
Signed-off-by: Tarun Tuli <tarun.tuli(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/elog.h
1 file changed, 23 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/72670/7
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Shuming Chu (Shuming) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71945 )
Change subject: soc/intel/xeon_sp: add ebg (Emmitsburg PCH) directory
......................................................................
Patch Set 10:
(1 comment)
Patchset:
PS8:
> Tim, could you help to check? Thanks!
Oh, sorry, I miss this, let me check and update to this patch.
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Hello Tarun Tuli, Kapil Porwal,
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#2).
Change subject: soc/intel/meteorlake: Enable V1p05-PHY supply external FET control
......................................................................
soc/intel/meteorlake: Enable V1p05-PHY supply external FET control
This patch enables S0i2.2 by letting 1.5V Phy supply to control the
externa FET.
BUG=b:256805904
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
Change-Id: I8771c11ce3b305343c7e96510e1375538d5e7f04
---
M src/soc/intel/meteorlake/fsp_params.c
1 file changed, 16 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/72709/2
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Change subject: mb/intel/mtlrvp: Add chip configuration for I2C devices
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Patch Set 2: Code-Review+1
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Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/elkhartlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/72404/comment/30a4cdda_6673bf4d
PS2, Line 159: if (CONFIG_TTYS0_BASE == 0x3f8)
: m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8;
: else if (CONFIG_TTYS0_BASE == 0x2f8)
: m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_2F8;
> Yes I know, but since the other 2 configs are exposed they should be handled as well. […]
So how do you suggest to handle them?
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Change subject: ifdtool: Drop chipset without IFD
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Patch Set 7: Code-Review+2
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