coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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5082 discussions

[S] Change in coreboot[master]: util/scripts/testsoc: Only select mainboards
by Martin Roth (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Martin L Roth, Fred Reitberger. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72655 ) Change subject: util/scripts/testsoc: Only select mainboards ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72655 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275 Gerrit-Change-Number: 72655 Gerrit-PatchSet: 1 Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:48:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/tgl: Move ME FSR structures to pertinent header
by Subrata Banik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72416 ) Change subject: soc/intel/tgl: Move ME FSR structures to pertinent header ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Gerrit-Change-Number: 72416 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:42:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/skl: Move ME FSR structures to pertinent header
by Subrata Banik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72415 ) Change subject: soc/intel/skl: Move ME FSR structures to pertinent header ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Gerrit-Change-Number: 72415 Gerrit-PatchSet: 2 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:41:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/jsk: Move ME FSR structures to pertinent header
by Subrata Banik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Dinesh Gehlot, Kapil Porwal. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72414 ) Change subject: soc/intel/jsk: Move ME FSR structures to pertinent header ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Gerrit-Change-Number: 72414 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:41:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Force resets to be cold
by Tim Van Patten (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72486 ) Change subject: soc/amd/mendocino: Force resets to be cold ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/mendocino/fch.c: https://review.coreboot.org/c/coreboot/+/72486/comment/919e6bf2_4ffd90f5 PS3, Line 131: pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); > fch_init_resets() is there so that when Linux does a reset, it's a cold reset. This is identical to the situation on Cezanne. If it's not there, the system will hang on reboot after S0i3. > The warm resets in coreboot haven't been an issue, and we could probably leave that part of this change out, but it definitely doesn't hurt to have it in there as well. Please update the commit message to clarify this. -- To view, visit https://review.coreboot.org/c/coreboot/+/72486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Gerrit-Change-Number: 72486 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:40:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Force resets to be cold
by Martin L Roth (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Tim Van Patten, Fred Reitberger. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72486 ) Change subject: soc/amd/mendocino: Force resets to be cold ...................................................................... Patch Set 3: (1 comment) File src/soc/amd/mendocino/fch.c: https://review.coreboot.org/c/coreboot/+/72486/comment/88e11c9c_ce02f3e6 PS3, Line 131: pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); > no, fch_init_resets is essential to make sure that that bit to change the reset behavior is still se […] fch_init_resets() is there so that when Linux does a reset, it's a cold reset. This is identical to the situation on Cezanne. If it's not there, the system will hang on reboot after S0i3. That's the specific fix that this patch is intended to fix. The warm resets in coreboot haven't been an issue, and we could probably leave that part of this change out, but it definitely doesn't hurt to have it in there as well. This patch is correct to fix the bug it's addressing. -- To view, visit https://review.coreboot.org/c/coreboot/+/72486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Gerrit-Change-Number: 72486 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Van Patten <timvp(a)google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:28:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/prodrive/hermes: Add SATA hotplug EEPROM setting
by Justin van Son (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Christian Walter, Lean Sheng Tan, Angel Pons. Hello Patrick Rudolph, Christian Walter, Lean Sheng Tan, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72712 to look at the new patch set (#2). Change subject: mb/prodrive/hermes: Add SATA hotplug EEPROM setting ...................................................................... mb/prodrive/hermes: Add SATA hotplug EEPROM setting Add an option to the EEPROM to configure SATA hotplug. Per port configuration is not needed, so add a global option to toggle the hotplug setting on all SATA ports. Change-Id: Ib7dcd12049bdf7c2d200530acd8a6da5df726203 Signed-off-by: Justin van Son <justin.van.son(a)prodrive-technologies.com> --- M src/mainboard/prodrive/hermes/eeprom.h M src/mainboard/prodrive/hermes/mainboard.c 2 files changed, 32 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/72712/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72712 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7dcd12049bdf7c2d200530acd8a6da5df726203 Gerrit-Change-Number: 72712 Gerrit-PatchSet: 2 Gerrit-Owner: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: amdfwtool: Add entry RIB whose subprog equals 1
by Felix Held (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bao Zheng, Jason Glenesk, ritul guru, Zheng Bao, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72507 ) Change subject: amdfwtool: Add entry RIB whose subprog equals 1 ...................................................................... Patch Set 2: (1 comment) File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/72507/comment/9c3c0856_0e675dd8 PS2, Line 414: } else if (strcmp(fw_name, "PSP_RIB_FILE") == 0) { for consistency i'd rename this one to PSP_RIB_FILE_SUB0 -- To view, visit https://review.coreboot.org/c/coreboot/+/72507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Gerrit-Change-Number: 72507 Gerrit-PatchSet: 2 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 15:09:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params
by Werner Zeh (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Michał Żygowski, Kacper Stojek, Lean Sheng Tan. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72404 ) Change subject: soc/intel/elkhartlake/romstage/fsp_params.c: separate debug params ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/elkhartlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/72404/comment/ba4b1562_0343cd27 PS2, Line 159: if (CONFIG_TTYS0_BASE == 0x3f8) : m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_3F8; : else if (CONFIG_TTYS0_BASE == 0x2f8) : m_cfg->PcdIsaSerialUartBase = ISA_SERIAL_BASE_ADDR_2F8; > So how do you suggest to handle them? Looks like setting these parameters is added in this commit. Could you please either mention it in the commit message or (preferably) do it in a separate commit? -- To view, visit https://review.coreboot.org/c/coreboot/+/72404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I84f7c19a7c2fd5a4db18f5a37e1c667da017aace Gerrit-Change-Number: 72404 Gerrit-PatchSet: 2 Gerrit-Owner: Kacper Stojek Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kacper Stojek Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 15:02:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/omnigul: Add memory config
by Paul Fagerburg (Code Review) 01 Feb '23

01 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71930 ) Change subject: mb/google/brya/var/omnigul: Add memory config ...................................................................... mb/google/brya/var/omnigul: Add memory config Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang(a)intel.com> --- M src/mainboard/google/brya/variants/omnigul/Makefile.inc A src/mainboard/google/brya/variants/omnigul/memory.c 2 files changed, 137 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Marx Wang: Looks good to me, but someone else must approve Dtrain Hsu: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/omnigul/Makefile.inc b/src/mainboard/google/brya/variants/omnigul/Makefile.inc index d7d2ef7..a9bae70 100644 --- a/src/mainboard/google/brya/variants/omnigul/Makefile.inc +++ b/src/mainboard/google/brya/variants/omnigul/Makefile.inc @@ -4,3 +4,5 @@ ramstage-y += gpio.c romstage-y += gpio.c + +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/omnigul/memory.c b/src/mainboard/google/brya/variants/omnigul/memory.c new file mode 100644 index 0000000..f72b729 --- /dev/null +++ b/src/mainboard/google/brya/variants/omnigul/memory.c @@ -0,0 +1,115 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 3, 2, 1, 6, 4, 5, 7 }, + .dq1 = { 14, 12, 13, 15, 11, 8, 10, 9 }, + }, + .ddr1 = { + .dq0 = { 1, 0, 2, 3, 6, 4, 7, 5 }, + .dq1 = { 15, 13, 12, 14, 8, 11, 10, 9 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 7, 6, 4, 5 }, + .dq1 = { 14, 12, 13, 15, 8, 9, 10, 11 }, + }, + .ddr3 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 13, 15, 12, 14, 8, 11, 10, 9 }, + }, + .ddr4 = { + .dq0 = { 2, 3, 0, 1, 6, 5, 7, 4 }, + .dq1 = { 14, 12, 13, 15, 8, 10, 9, 11 }, + }, + .ddr5 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5 }, + .dq1 = { 15, 13, 12, 14, 11, 9, 10, 8 }, + }, + .ddr6 = { + .dq0 = { 3, 1, 2, 0, 5, 7, 6, 4 }, + .dq1 = { 15, 13, 14, 12, 10, 9, 11, 8 }, + }, + .ddr7 = { + .dq0 = { 2, 3, 1, 0, 5, 4, 7, 6 }, + .dq1 = { 14, 15, 10, 11, 13, 8, 9, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E11 + * GPIO_MEM_CONFIG_1 GPP_E2 + * GPIO_MEM_CONFIG_2 GPP_E1 + * GPIO_MEM_CONFIG_3 GPP_E12 + */ + gpio_t spd_gpios[] = { + GPP_E11, + GPP_E2, + GPP_E1, + GPP_E12, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + /* GPIO_MEM_CH_SEL GPP_E13 */ + return gpio_get(GPP_E13); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/71930 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Gerrit-Change-Number: 71930 Gerrit-PatchSet: 4 Gerrit-Owner: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Marx Wang <marx.wang(a)intel.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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coreboot-gerrit February 2023