coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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5082 discussions

[S] Change in coreboot[master]: soc/intel/apl: Hook up cpu ops in devicetree
by Lean Sheng Tan (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Sean Rhodes, Arthur Heymans. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72705 ) Change subject: soc/intel/apl: Hook up cpu ops in devicetree ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72705 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7fd1db72ca98f0a1b8fd03a979308a7c701a8a54 Gerrit-Change-Number: 72705 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:29:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: Documentation: Add Asus P3B-F
by Keith Hui (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Angel Pons. Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61538 ) Change subject: Documentation: Add Asus P3B-F ...................................................................... Patch Set 3: (3 comments) File Documentation/mainboard/asus/p3b-f.md: https://review.coreboot.org/c/coreboot/+/61538/comment/76f89e2a_94c0ec9c PS2, Line 13: SST 39SF020A (or similar) > It would be good to specify the flash protocol Done https://review.coreboot.org/c/coreboot/+/61538/comment/ed4bfbca_9933e1a3 PS2, Line 23: yse > typo: yes Done https://review.coreboot.org/c/coreboot/+/61538/comment/0666243b_723bf3f2 PS2, Line 83: model_6xx > Would be nice to indicate the actual models and CPU socket (slot 1?) Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0cd6141bb8baa082d5558490533649f907f25dd1 Gerrit-Change-Number: 61538 Gerrit-PatchSet: 3 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:25:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Force resets to be cold
by Felix Held (Code Review) 01 Feb '23

01 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72486 ) Change subject: soc/amd/mendocino: Force resets to be cold ...................................................................... soc/amd/mendocino: Force resets to be cold Like Cezanne, Mendocino does not support warm resets. Change all resets (including resets in the OS) to cold resets (like Cezanne). BUG=b:248221908 TEST=Run suspend_stress_test, then reboot Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72486 Reviewed-by: Jon Murphy <jpmurphy(a)google.com> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> --- M src/soc/amd/mendocino/fch.c M src/soc/amd/mendocino/reset.c 2 files changed, 29 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved Jon Murphy: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index d7c488b..abe2dc1 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -126,6 +126,11 @@ PM_ACPI_TIMER_EN_EN); } +static void fch_init_resets(void) +{ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -197,6 +202,7 @@ void fch_init(void *chip_info) { + fch_init_resets(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/mendocino/reset.c b/src/soc/amd/mendocino/reset.c index 800374c..ac0c981 100644 --- a/src/soc/amd/mendocino/reset.c +++ b/src/soc/amd/mendocino/reset.c @@ -17,8 +17,8 @@ void do_warm_reset(void) { - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); + /* Warm resets are not supported and must be executed as cold */ + do_cold_reset(); } void do_board_reset(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/72486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Gerrit-Change-Number: 72486 Gerrit-PatchSet: 5 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: util/amdfwtool: add comment about reused PSP firmware type 0x5f
by Felix Held (Code Review) 01 Feb '23

01 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72713 ) Change subject: util/amdfwtool: add comment about reused PSP firmware type 0x5f ...................................................................... util/amdfwtool: add comment about reused PSP firmware type 0x5f On family 15h and 16h processors with PSP, the PSP firmware type 0x5f corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to clarify this. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c --- M util/amdfwtool/amdfwtool.h 1 file changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/72713/1 diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d3d6866..f30dce6 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -68,8 +68,8 @@ AMD_FW_MSMU = 0x5a, AMD_FW_SPIROM_CFG = 0x5c, AMD_FW_MPIO = 0x5d, - AMD_FW_TPMLITE = 0x5f, - AMD_FW_PSP_SMUSCS = 0x5f, + AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ + AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_RIB = 0x76, -- To view, visit https://review.coreboot.org/c/coreboot/+/72713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Gerrit-Change-Number: 72713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
by Jonathan Zhang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Simon Chou, Johnny Lin, Christian Walter, Arthur Heymans. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71965 ) Change subject: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks() ...................................................................... Patch Set 10: (1 comment) File src/soc/intel/xeon_sp/chip_common.c: https://review.coreboot.org/c/coreboot/+/71965/comment/432f29a8_9ec574b9 PS2, Line 495: attach_iio_stacks > I submitted patchset 10 for this. BTW the below lint errors need to be fixed in CB:72439. […] This is because [CB:72439] needs to be a dependency for [CB:71965]. You may want to have [CB:71965] on top of [CB:72439] in your branch, then the gerrit build system will build [CB:71965] with [CB:72439] included. In this case the lint error will disappear, and gerrit shows that those two are a patch set. -- To view, visit https://review.coreboot.org/c/coreboot/+/71965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Gerrit-Change-Number: 71965 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:22:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Johnny Lin <Johnny_Lin(a)wiwynn.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code
by Jonathan Zhang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 ) Change subject: soc/intel/xeon_sp/spr: add ACPI code ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/xeon_sp/spr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/71967/comment/c0085c01_bc1e96f6 PS13, Line 387: for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { > This must be CONFIG_MAX_SOCKET to prevent ACPI errors when not all CPUs are plugged on a multi socke […] I do not have such a system. I would guess that when not all CPUs are plugged on a multi socket system, the hob->PlatformData.numofIIO should reflect the actual number of CPUs instead of the number of sockets? Should we confirm this with Intel? IIRC, Johnny has a dual socket ArcherCity CRB with only socket plugged in, and this code works fine for him. -- To view, visit https://review.coreboot.org/c/coreboot/+/71967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Gerrit-Change-Number: 71967 Gerrit-PatchSet: 13 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:13:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
by Tarun Tuli (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Paul Menzel, Julius Werner, Nick Vaccaro, Yu-Ping Wu. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72670 ) Change subject: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type ...................................................................... Patch Set 8: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/elog.h: https://review.coreboot.org/c/coreboot/+/72670/comment/10b2bd27_65af405f PS8, Line 368: #define ELOG_TYPE_FW_EARL > But now 0xb8 is not space out properly :( they are all over the place in this file :D -- To view, visit https://review.coreboot.org/c/coreboot/+/72670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c Gerrit-Change-Number: 72670 Gerrit-PatchSet: 8 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:09:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/tgl: Move ME FSR structures to pertinent header
by Sridhar Siricilla (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot. Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72416 ) Change subject: soc/intel/tgl: Move ME FSR structures to pertinent header ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72416/comment/d8e6f09e_71b0a743 PS3, Line 7: soc/intel/tgl: Move ME FSR structures to pertinent header > Yes, we may need to use SoC specfic Macro's to select the appropriate prints. […] Is it not easier and cleaner defining those structs (txt_support/cpu_debug_disable) and dependent APIs into soc folder itself instead making them common? -- To view, visit https://review.coreboot.org/c/coreboot/+/72416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Gerrit-Change-Number: 72416 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 18:08:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Dinesh Gehlot <digehlot(a)google.com> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/mendocino: Force resets to be cold
by Tim Van Patten (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Felix Held. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72486 ) Change subject: soc/amd/mendocino: Force resets to be cold ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/soc/amd/mendocino/fch.c: https://review.coreboot.org/c/coreboot/+/72486/comment/1e2d2bef_e788f5fb PS3, Line 131: pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); > Done Thanks much. -- To view, visit https://review.coreboot.org/c/coreboot/+/72486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1fbb4cc6eb6e6de9616d00d0191ccf3c0ac55278 Gerrit-Change-Number: 72486 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Amanda Hwang <amanda_hwang(a)compal.corp-partner.google.com> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: EricKY Cheng <ericky_cheng(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 01 Feb 2023 17:58:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Tim Van Patten <timvp(a)google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71295 ) Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL ...................................................................... Patch Set 18: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Gerrit-Change-Number: 71295 Gerrit-PatchSet: 18 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 17:57:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023