coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1
by Anil Kumar K (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Hannah Williams, Cliff Huang, Subrata Banik, Jérémy Compostella. Anil Kumar K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72422 ) Change subject: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72422/comment/e7e48466_cfea433a PS2, Line 8: : Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec nit: Add a full stop after this line -- To view, visit https://review.coreboot.org/c/coreboot/+/72422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Gerrit-Change-Number: 72422 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:08:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1
by Cliff Huang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bora Guvendik, Hannah Williams, Anil Kumar K, Subrata Banik. Hello Bora Guvendik, Hannah Williams, Anil Kumar K, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72422 to look at the new patch set (#2). Change subject: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 ...................................................................... mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 --- M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/72422/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Gerrit-Change-Number: 72422 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks()
by Jonathan Zhang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Simon Chou, Johnny Lin, Christian Walter, Arthur Heymans. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71965 ) Change subject: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks() ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71965/comment/92a16159_48445c9e PS10, Line 7: soc/intel/xeon_sp/chip_common.c: Update attach_iio_stacks() How about "Probe all buses in attach_iio_stacks()"? -- To view, visit https://review.coreboot.org/c/coreboot/+/71965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250 Gerrit-Change-Number: 71965 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 21:49:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code
by Jonathan Zhang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans. Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 ) Change subject: soc/intel/xeon_sp/spr: add ACPI code ...................................................................... Patch Set 13: (2 comments) File src/soc/intel/xeon_sp/spr/acpi/uncore.asl: https://review.coreboot.org/c/coreboot/+/71967/comment/b6444edc_fe63a8e6 PS13, Line 38: #if (CONFIG_MAX_SOCKET > 3) This part of the DSDT code should be generated, using hob->PlatformData.numofIIO. File src/soc/intel/xeon_sp/spr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/71967/comment/f3b8a959_5d348b60 PS13, Line 387: for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { > The issue is that SSDT needs to be in sync with DSDT (src/soc/intel/xeon_sp/spr/acpi/uncore. […] Got you. I think we should use hob->PlatformData.numofIIO for DSDT as well; in other words, we should generate that part of the DSDT code. Do you agree? -- To view, visit https://review.coreboot.org/c/coreboot/+/71967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Gerrit-Change-Number: 71967 Gerrit-PatchSet: 13 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 21:46:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/amd/pi: Fix "No such file or directory"
by Elyes Haouas (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Martin L Roth, Arthur Heymans, Eric Lai. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71855 ) Change subject: vc/amd/pi: Fix "No such file or directory" ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: needed for https://review.coreboot.org/c/coreboot/+/70251 -- To view, visit https://review.coreboot.org/c/coreboot/+/71855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Gerrit-Change-Number: 71855 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 21:39:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PCO, CZN, MDN, PHX & Glinda
by Martin L Roth (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Hello Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72659 to look at the new patch set (#2). Change subject: soc/amd: Use common reset code for PCO, CZN, MDN, PHX & Glinda ...................................................................... soc/amd: Use common reset code for PCO, CZN, MDN, PHX & Glinda This switches the Ryzen SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Picasso does support warm reset, so set the SOC_SUPPORTS_WARM_RESET flag in Kconfig. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fch.c D src/soc/amd/cezanne/reset.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/glinda/fch.c D src/soc/amd/glinda/reset.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/fch.c D src/soc/amd/mendocino/reset.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/phoenix/fch.c D src/soc/amd/phoenix/reset.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/reset.c 19 files changed, 32 insertions(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/72659/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PCO, CZN, MDN, PHZ & Glinda
by Martin L Roth (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Fred Reitberger, Felix Held. Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72659 ) Change subject: soc/amd: Use common reset code for PCO, CZN, MDN, PHZ & Glinda ...................................................................... soc/amd: Use common reset code for PCO, CZN, MDN, PHZ & Glinda This switches the Ryzen SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Picasso does support warm reset, so set the SOC_SUPPORTS_WARM_RESET flag in Kconfig. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fch.c D src/soc/amd/cezanne/reset.c M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/glinda/fch.c D src/soc/amd/glinda/reset.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/fch.c D src/soc/amd/mendocino/reset.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/phoenix/fch.c D src/soc/amd/phoenix/reset.c M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/reset.c 19 files changed, 32 insertions(+), 174 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/72659/1 diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 35c2927..e1ab7b8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -55,6 +55,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5313e0d..a8474e2 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -12,18 +12,15 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -37,7 +34,6 @@ ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 0936c5e..985587c 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> @@ -130,11 +131,6 @@ PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -204,7 +200,7 @@ void fch_init(void *chip_info) { - fch_init_resets(); + set_cf9_reset_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c deleted file mode 100644 index 1360bd5..0000000 --- a/src/soc/amd/cezanne/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 7b0b736..214fc81 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 891a68d..ef0d27d 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index af5f0ec..77c0050 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -196,6 +197,7 @@ void fch_init(void *chip_info) { + set_cf9_reset_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/glinda/reset.c b/src/soc/amd/glinda/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/glinda/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 7faa479..5b274f9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 7d7033a..1dc0773 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -14,19 +14,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -39,7 +36,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index abe2dc1..0d55b48 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -126,11 +127,6 @@ PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -202,7 +198,7 @@ void fch_init(void *chip_info) { - fch_init_resets(); + set_cf9_reset_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/mendocino/reset.c b/src/soc/amd/mendocino/reset.c deleted file mode 100644 index ac0c981..0000000 --- a/src/soc/amd/mendocino/reset.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - do_cold_reset(); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 883359c..37a2fc9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 1c24243..84825d0 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index 91df79e..73340e7 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -192,6 +193,7 @@ void fch_init(void *chip_info) { + set_cf9_reset_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/phoenix/reset.c b/src/soc/amd/phoenix/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/phoenix/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a0254e9..bc8077b 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI @@ -61,6 +62,7 @@ select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES + select SOC_SUPPORTS_WARM_RESET select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 50fc62c..e7ed68e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -12,19 +12,16 @@ bootblock-y += early_fch.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -38,7 +35,6 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += pcie_gpp.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += sata.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c deleted file mode 100644 index 8181d90..0000000 --- a/src/soc/amd/picasso/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - /* TODO: Would a warm_reset() suffice? */ - do_cold_reset(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Martin L Roth (Code Review) 01 Feb '23

01 Feb '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... soc/amd: Create AMD common reset code This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 --- M src/soc/amd/common/block/include/amdblocks/reset.h A src/soc/amd/common/block/reset/Kconfig A src/soc/amd/common/block/reset/Makefile.inc A src/soc/amd/common/block/reset/reset.c 4 files changed, 73 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/72658/1 diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 353720c..cf002ad 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -3,9 +3,12 @@ #ifndef AMD_BLOCK_RESET_H #define AMD_BLOCK_RESET_H -#include <console/console.h> +#include <amdblocks/acpimmio.h> #include <arch/cache.h> +#include <console/console.h> #include <halt.h> +#include <soc/southbridge.h> + void do_warm_reset(void); void do_cold_reset(void); @@ -28,4 +31,10 @@ halt(); } +static inline void set_cf9_reset_to_cold(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + #endif /* AMD_BLOCK_RESET_H */ diff --git a/src/soc/amd/common/block/reset/Kconfig b/src/soc/amd/common/block/reset/Kconfig new file mode 100644 index 0000000..ffb7ee7 --- /dev/null +++ b/src/soc/amd/common/block/reset/Kconfig @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: GPL-2.0-only + +config SOC_AMD_COMMON_BLOCK_RESET + bool + help + Select this option to use AMD common reset driver support. + +config SOC_SUPPORTS_WARM_RESET + bool + help + Select this option if the chip supports warm reset. diff --git a/src/soc/amd/common/block/reset/Makefile.inc b/src/soc/amd/common/block/reset/Makefile.inc new file mode 100644 index 0000000..c53d58b --- /dev/null +++ b/src/soc/amd/common/block/reset/Makefile.inc @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_RESET),y) + +bootblock-y += reset.c +verstage_x86-y += reset.c +romstage-y += reset.c +ramstage-y += reset.c + +endif diff --git a/src/soc/amd/common/block/reset/reset.c b/src/soc/amd/common/block/reset/reset.c new file mode 100644 index 0000000..b926553 --- /dev/null +++ b/src/soc/amd/common/block/reset/reset.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <cf9_reset.h> +#include <reset.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> + +void do_cold_reset(void) +{ + set_cf9_reset_to_cold(); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + /* If warm resets are not supported, executed a cold reset */ + if (!CONFIG(SOC_SUPPORTS_WARM_RESET)) + do_cold_reset(); + + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + do_cold_reset(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in libgfxinit[master]: [EXPERIMENTAL] Begin Meteor Lake integration
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/libgfxinit/+/72714 ) Change subject: [EXPERIMENTAL] Begin Meteor Lake integration ...................................................................... [EXPERIMENTAL] Begin Meteor Lake integration MeteoLake is gen 14 which is another generation (compared to Tigerlake 12) but according to the GOP team, changes are minimal. Therefore, this patch does NOT create a new Gen_Meteorlake. On the first run the board got stuck on common/tigerlake/hw-gfx-gma-power_and_clocks.adb::Get_RawClk() It turns that it hangs on Registers.SFUSE_STRAP. According to the https://patchwork.freedesktop.org/patch/499261/ i915 driver change: MTL has a fixed rawclk of 38400Khz. Register does not need to be reprogrammed. So I made Get_RawClk() return 38_400_000 on MTL. The commit message also states that it does not need to be reprogrammed and that's something I have not looked in and that may be something worth looking at. Nevertheless, with this change the board gets further and at least isn't stuck. Change-Id: I890b32497af8edc82dd533e5c556e30ec50d0d04 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M common/hw-gfx-gma-config.ads.template M common/hw-gfx-gma.ads M common/tigerlake/hw-gfx-gma-power_and_clocks.adb 3 files changed, 55 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/libgfxinit refs/changes/14/72714/1 diff --git a/common/hw-gfx-gma-config.ads.template b/common/hw-gfx-gma-config.ads.template index 8a39618..7ab5071 100644 --- a/common/hw-gfx-gma-config.ads.template +++ b/common/hw-gfx-gma-config.ads.template @@ -31,7 +31,7 @@ when Haswell => Broadwell, when Broxton => Broxton, when Skylake => Kabylake, - when Tigerlake => Alderlake); + when Tigerlake => Meteorlake); CPU_Var_Last : constant CPU_Variant := (case Gen is when Haswell | Skylake | Tigerlake => ULX, @@ -161,6 +161,7 @@ CPU_Kabylake : <sklbool> := Gen_Skylake and then CPU = Kabylake; CPU_Tigerlake : <tglbool> := Gen_Tigerlake and then CPU = Tigerlake; CPU_Alderlake : <tglbool> := Gen_Tigerlake and then CPU = Alderlake; + CPU_Meteorlake : <tglbool> := Gen_Tigerlake and then CPU = Meteorlake; Sandybridge_On : <ilkbool> := ((Gen_Ironlake and then CPU >= Sandybridge) or Haswell_On); @@ -566,6 +567,9 @@ Is_Alder_Lake_N (Device_Id) or Is_Raptor_Lake_P (Device_Id)); + function Is_Meteor_Lake (Device_ID : Word16) return Boolean is + (Device_Id = 16#7d45#); + function Is_GPU (Device_Id : Word16; CPU : CPU_Type; CPU_Var : CPU_Variant) return Boolean is (case CPU is @@ -609,7 +613,12 @@ when Normal => False, when ULT | ULX => - Is_Alder_Lake (Device_ID))); + Is_Alder_Lake (Device_ID)), + when Meteorlake => (case CPU_Var is + when Normal => + False, + when ULT | ULX => + Is_Meteor_Lake (Device_ID))); function Compatible_GPU (Device_Id : Word16) return Boolean is (Is_GPU (Device_Id, CPU, CPU_Var)); diff --git a/common/hw-gfx-gma.ads b/common/hw-gfx-gma.ads index 1c589d0..54e24be 100644 --- a/common/hw-gfx-gma.ads +++ b/common/hw-gfx-gma.ads @@ -49,7 +49,8 @@ Skylake, Kabylake, Tigerlake, - Alderlake); + Alderlake, + Meteorlake); type CPU_Variant is (Normal, ULT, ULX); @@ -61,7 +62,8 @@ Sunrise_Point, -- Union Point compatible Cannon_Point, Tiger_Point, - Alder_Point); + Alder_Point, + Meteor_Point); type Port_Type is (Disabled, diff --git a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb index a01a89d..570eb1a 100644 --- a/common/tigerlake/hw-gfx-gma-power_and_clocks.adb +++ b/common/tigerlake/hw-gfx-gma-power_and_clocks.adb @@ -133,14 +133,18 @@ Raw_Frequency_24_MHz : Boolean; SFUSE_STRAP_RAW_FREQUENCY : constant := 1 * 2 ** 8; begin - Rawclk := Config.Default_RawClk_Freq; - Registers.Is_Set_Mask - (Register => Registers.SFUSE_STRAP, - Mask => SFUSE_STRAP_RAW_FREQUENCY, - Result => Raw_Frequency_24_MHz); + if Config.CPU_Meteorlake then + Rawclk := 38_400_000; + else + Rawclk := Config.Default_RawClk_Freq; + Registers.Is_Set_Mask + (Register => Registers.SFUSE_STRAP, + Mask => SFUSE_STRAP_RAW_FREQUENCY, + Result => Raw_Frequency_24_MHz); - if not Raw_Frequency_24_MHz then - Rawclk := 19_200_000; + if not Raw_Frequency_24_MHz then + Rawclk := 38_400_000; + end if; end if; end Get_RawClk; -- To view, visit https://review.coreboot.org/c/libgfxinit/+/72714 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: I890b32497af8edc82dd533e5c556e30ec50d0d04 Gerrit-Change-Number: 72714 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[master]: soc/intel/xeon_sp/spr: add ACPI code
by Patrick Rudolph (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jonathan Zhang, Simon Chou, Johnny Lin, Christian Walter, Shuming Chu (Shuming), Arthur Heymans. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71967 ) Change subject: soc/intel/xeon_sp/spr: add ACPI code ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/xeon_sp/spr/soc_acpi.c: https://review.coreboot.org/c/coreboot/+/71967/comment/f7449a13_99c00f93 PS13, Line 387: for (uint8_t socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { > I do not have such a system. […] The issue is that SSDT needs to be in sync with DSDT (src/soc/intel/xeon_sp/spr/acpi/uncore.asl) and DSDT only uses CONFIG_MAX_SOCKET, but not hob->PlatformData.numofIIO. -- To view, visit https://review.coreboot.org/c/coreboot/+/71967 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6 Gerrit-Change-Number: 71967 Gerrit-PatchSet: 13 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-CC: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuming Chu (Shuming) <s1218944(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 01 Feb 2023 20:47:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023