coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: mb/google/nissa/var/craask: Modify DPTF settings
by Reka Norman (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: David Wu, Tarun Tuli, Kangheui Won, Ren Kuo, Peter Ou. Reka Norman has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71860 ) Change subject: mb/google/nissa/var/craask: Modify DPTF settings ...................................................................... Patch Set 5: Code-Review-1 (1 comment) File src/mainboard/google/brya/variants/craask/overridetree.cb: https://review.coreboot.org/c/coreboot/+/71860/comment/fa46e863_23299638 PS5, Line 230: ## Fan Performance Control (Percent, Speed, Noise, Power) Please see the previous discussion in https://chrome-internal-review.googlesource.com/c/chromeos/project/nissa/cr… The proposal from the quanta thermal team was: - Fan controlled by EC only, based on `FAN` fw_config. No fan table in coreboot. - Other DPTF settings in coreboot selected by `THERMAL_SOLUTION` fw_config. So I don't expect to see a fan table in coreboot. Since there are 6W+fan SKUs, we can't select the fan table based on `THERMAL_SOLUTION` only. If we do need a fan table in coreboot, we'll have to change the fw_config setup. -- To view, visit https://review.coreboot.org/c/coreboot/+/71860 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Gerrit-Change-Number: 71860 Gerrit-PatchSet: 5 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kangheui Won <khwon(a)chromium.org> Gerrit-Attention: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Attention: Peter Ou <peter.ou(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:57:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1
by Cliff Huang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Anil Kumar K, Hannah Williams, Subrata Banik, Jérémy Compostella. Cliff Huang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72422 ) Change subject: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72422/comment/133e4730_cb1d4054 PS2, Line 8: : Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec > nit: Add a full stop after this line Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Gerrit-Change-Number: 72422 Gerrit-PatchSet: 2 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:50:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1
by Cliff Huang (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Anil Kumar K, Hannah Williams, Subrata Banik, Jérémy Compostella. Hello Bora Guvendik, Hannah Williams, Anil Kumar K, Subrata Banik, Jérémy Compostella, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72422 to look at the new patch set (#3). Change subject: mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 ...................................................................... mb/intel/adlrvp: Fix RTD3 timing for PCIe slot1 Fix RTD3 timing for adlrvp_p_ext_ec and adlrvp_rpl_ext_ec. BUG=none BRANCH=firmware-brya-14505.B TEST=Insert a SD card or NIC AIC on PCIe slot1 and run 'suspend_stress_test -c 1'. The RP8 should not cause suspend issue. Signed-off-by: Cliff Huang <cliff.huang(a)intel.com> Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 --- M src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb M src/mainboard/intel/adlrvp/variants/adlrvp_rpl_ext_ec/overridetree.cb 2 files changed, 22 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/72422/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72422 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I792c55a6361d1eae55cc6f668a03dc2503120fe1 Gerrit-Change-Number: 72422 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72715 ) Change subject: [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life ...................................................................... [EXPERIMENTAL] soc/intel/meteorlake: Test early sign-of-life It unlocks memory in romstage but I have not verified if it is necessary on MTL. I verified in the rex0 VBT that the Power Sequence parameters are still the (T3 2000 T7 10 T9 2000 T10 500 T12 5000). Therefore, src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb should be correct. Change-Id: Ic4c37077b3b3032c861f96231435fcebc7ef36ff Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/gma/Kconfig M src/mainboard/google/rex/Kconfig.name M src/mainboard/google/rex/Makefile.inc A src/mainboard/google/rex/gma-mainboard.ads M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb M src/soc/intel/meteorlake/Kconfig M src/soc/intel/meteorlake/chip.h M src/soc/intel/meteorlake/romstage/Makefile.inc M src/soc/intel/meteorlake/romstage/fsp_params.c A src/soc/intel/meteorlake/romstage/graphics.c M src/soc/intel/meteorlake/romstage/romstage.c 11 files changed, 146 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/72715/1 diff --git a/src/drivers/intel/gma/Kconfig b/src/drivers/intel/gma/Kconfig index ea892d1..6de18d1 100644 --- a/src/drivers/intel/gma/Kconfig +++ b/src/drivers/intel/gma/Kconfig @@ -92,7 +92,7 @@ config EARLY_GFX_GMA def_bool y - depends on SOC_INTEL_ALDERLAKE + depends on SOC_INTEL_ALDERLAKE || SOC_INTEL_METEORLAKE depends on MAINBOARD_USE_EARLY_LIBGFXINIT select ROMSTAGE_LIBHWBASE @@ -142,6 +142,7 @@ default "Ironlake" if NORTHBRIDGE_INTEL_IRONLAKE || NORTHBRIDGE_INTEL_SANDYBRIDGE default "G45" if NORTHBRIDGE_INTEL_GM45 || NORTHBRIDGE_INTEL_X4X default "Tigerlake" if SOC_INTEL_ALDERLAKE + default "Tigerlake" if SOC_INTEL_METEORLAKE config GFX_GMA_PCH string @@ -151,6 +152,7 @@ default "Sunrise_Point" if SOC_INTEL_COMMON_SKYLAKE_BASE default "Cannon_Point" if SOC_INTEL_CANNONLAKE_BASE default "Alder_Point" if SOC_INTEL_ALDERLAKE + default "Meteor_Point" if SOC_INTEL_METEORLAKE default "No_PCH" config GFX_GMA_PANEL_1_PORT diff --git a/src/mainboard/google/rex/Kconfig.name b/src/mainboard/google/rex/Kconfig.name index d74c499..7cd88aa 100644 --- a/src/mainboard/google/rex/Kconfig.name +++ b/src/mainboard/google/rex/Kconfig.name @@ -2,3 +2,5 @@ config BOARD_GOOGLE_REX0 bool "-> Rex 0" + select MAINBOARD_HAS_EARLY_LIBGFXINIT + select DEBUG_ADA_CODE diff --git a/src/mainboard/google/rex/Makefile.inc b/src/mainboard/google/rex/Makefile.inc index 3fb7729..37cdc96 100644 --- a/src/mainboard/google/rex/Makefile.inc +++ b/src/mainboard/google/rex/Makefile.inc @@ -4,6 +4,7 @@ romstage-y += romstage.c romstage-$(CONFIG_CHROMEOS) += chromeos.c +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += mainboard.c ramstage-$(CONFIG_CHROMEOS) += chromeos.c diff --git a/src/mainboard/google/rex/gma-mainboard.ads b/src/mainboard/google/rex/gma-mainboard.ads new file mode 100644 index 0000000..3b02f14 --- /dev/null +++ b/src/mainboard/google/rex/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; diff --git a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb index f14699f..f4e6f93 100644 --- a/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb +++ b/src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb @@ -34,7 +34,37 @@ register "pch_hda_idisp_codec_enable" = "1" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref xhci on end device ref shared_sram on end diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index c00be8f..764ec25 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -37,6 +37,7 @@ select INTEL_GMA_ACPI select INTEL_GMA_ADD_VBT if RUN_FSP_GOP select INTEL_GMA_OPREGION_2_1 + select INTEL_TXT_LIB select IOAPIC select MICROCODE_BLOB_UNDISCLOSED select MRC_SETTINGS_PROTECT @@ -163,6 +164,9 @@ hex default 0x10000 +config GFX_GMA_DEFAULT_MMIO + default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT + # Intel recommends reserving the PCIe TBT root port resources as below: # - 42 buses # - 194 MiB Non-prefetchable memory diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h index 4e95321..853bd42 100644 --- a/src/soc/intel/meteorlake/chip.h +++ b/src/soc/intel/meteorlake/chip.h @@ -4,6 +4,7 @@ #define _SOC_CHIP_H_ #include <drivers/i2c/designware/dw_i2c.h> +#include <drivers/intel/gma/gma.h> #include <gpio.h> #include <intelblocks/cfg.h> #include <intelblocks/gspi.h> @@ -348,6 +349,11 @@ * Set this to 1 in order to disable Package C-state demotion. */ bool disable_package_c_state_demotion; + + /* + * IGD panel configuration + */ + struct i915_gpu_panel_config panel_cfg; }; typedef struct soc_intel_meteorlake_config config_t; diff --git a/src/soc/intel/meteorlake/romstage/Makefile.inc b/src/soc/intel/meteorlake/romstage/Makefile.inc index 99c1d2c..7f1a94b 100644 --- a/src/soc/intel/meteorlake/romstage/Makefile.inc +++ b/src/soc/intel/meteorlake/romstage/Makefile.inc @@ -4,3 +4,4 @@ romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += romstage.c romstage-y += systemagent.c +romstage-$(CONFIG_EARLY_GFX_GMA) += graphics.c diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index c01896f..13d4aec 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -336,6 +336,9 @@ soc_memory_init_params(m_cfg, config); mainboard_memory_init_params(mupd); + + if (CONFIG(HWBASE_STATIC_MMIO)) + m_cfg->GttMmAdr = CONFIG_GFX_GMA_DEFAULT_MMIO; } __weak void mainboard_memory_init_params(FSPM_UPD *memupd) diff --git a/src/soc/intel/meteorlake/romstage/graphics.c b/src/soc/intel/meteorlake/romstage/graphics.c new file mode 100644 index 0000000..3c8c174 --- /dev/null +++ b/src/soc/intel/meteorlake/romstage/graphics.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <drivers/intel/gma/i915_reg.h> +#include <intelblocks/early_graphics.h> +#include <soc/soc_chip.h> + +void early_graphics_soc_panel_init(void) +{ + const struct soc_intel_meteorlake_config *soc_conf; + const struct i915_gpu_panel_config *panel_cfg; + void *mmio = (void *)CONFIG_GFX_GMA_DEFAULT_MMIO; + uint32_t reg32; + unsigned int pwm_period, pwm_polarity, pwm_duty; + + soc_conf = config_of_soc(); + panel_cfg = &soc_conf->panel_cfg; + + reg32 = ((DIV_ROUND_UP(panel_cfg->cycle_delay_ms, 100) + 1) & 0x1f) << 4; + reg32 |= PANEL_POWER_RESET; + write32(mmio + PCH_PP_CONTROL, reg32); + + reg32 = ((panel_cfg->up_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_on_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_ON_DELAYS, reg32); + + reg32 = ((panel_cfg->down_delay_ms * 10) & 0x1fff) << 16; + reg32 |= (panel_cfg->backlight_off_delay_ms * 10) & 0x1fff; + write32(mmio + PCH_PP_OFF_DELAYS, reg32); + + if (!panel_cfg->backlight_pwm_hz) + return; + + /* Configure backlight */ + pwm_polarity = panel_cfg->backlight_polarity ? BXT_BLC_PWM_POLARITY : 0; + pwm_period = DIV_ROUND_CLOSEST(CONFIG_CPU_XTAL_HZ, + panel_cfg->backlight_pwm_hz); + pwm_duty = DIV_ROUND_CLOSEST(pwm_period, 2); /* Start with 50 % */ + write32(mmio + BXT_BLC_PWM_FREQ(0), pwm_period); + write32(mmio + BXT_BLC_PWM_CTL(0), pwm_polarity); + write32(mmio + BXT_BLC_PWM_DUTY(0), pwm_duty); +} diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 340716f..b5b8550 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -17,6 +17,12 @@ #include <soc/soc_chip.h> #include <timestamp.h> #include <string.h> +#include <security/intel/txt/txt.h> + +#include <console/console.h> +#include <intelblocks/early_graphics.h> +#include <pc80/vga.h> + #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -148,4 +154,20 @@ pmc_set_disb(); if (!s3wake) save_dimm_info(); + + /* + * Disable Intel TXT if `CPU is unsupported` or `SoC haven't selected the config`. + * + * It would help to access VGA framebuffer prior calling into FSP-M. + */ + if (!CONFIG(INTEL_TXT)) { + disable_intel_txt(); + if (CONFIG(MAINBOARD_HAS_EARLY_LIBGFXINIT) && + early_graphics_init()) { + printk(BIOS_INFO, "J2M: Testing early sign-of-life.\n"); + vga_write_text(VGA_TEXT_CENTER, VGA_TEXT_HORIZONTAL_MIDDLE, + "J2M: Your device is finishing an update. This may take 1-2 minutes.\nPlease do not turn off your device."); + } + } + } -- To view, visit https://review.coreboot.org/c/coreboot/+/72715 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic4c37077b3b3032c861f96231435fcebc7ef36ff Gerrit-Change-Number: 72715 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Kane Chen. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68636 ) Change subject: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Gerrit-Change-Number: 68636 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:19:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Tarun Tuli, Subrata Banik, Selma Bensaid, Kane Chen, Tim Wawrzynczak, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 7 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:18:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake
by Bora Guvendik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Subrata Banik, Jérémy Compostella, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Kane Chen. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68636 ) Change subject: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake ...................................................................... Patch Set 5: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/68636/comment/1fc4dd24_ea5f937d PS4, Line 7: brya > s/brya/brya0/ […] Done https://review.coreboot.org/c/coreboot/+/68636/comment/a55e6d82_92b1eff7 PS4, Line 10: refer > s/refer/refer to/ Done https://review.coreboot.org/c/coreboot/+/68636/comment/122d1332_0240e7b9 PS4, Line 15: Verify the build for skolas board > what about "Boot successfully on skolas" ? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Gerrit-Change-Number: 68636 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:16:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Bora Guvendik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Zhixing Ma, Anil Kumar K, Tarun Tuli, Subrata Banik, Jérémy Compostella, Selma Bensaid, Kane Chen, Tim Wawrzynczak, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/68635/comment/467522b2_cd885174 PS6, Line 15: Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> > Sign-off is out of place. And usually @intel.com are preferable. Author is kane.chen(a)intel.corp-partner.google.com, so he signed with his partner email, I don't think we should change it. Fixed placement. -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 7 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 22:15:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake
by Bora Guvendik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bora Guvendik, Tarun Tuli, Subrata Banik, Selma Bensaid, Tim Wawrzynczak, Angel Pons, Kane Chen. Bora Guvendik has uploaded a new patch set (#5) to the change originally created by Selma Bensaid. ( https://review.coreboot.org/c/coreboot/+/68636 ) Change subject: mb/google/brya0,skolas4es,skolas: disable Tccold Handshake ...................................................................... mb/google/brya0,skolas4es,skolas: disable Tccold Handshake The patch disables Tccold Handshake to prevent possible display flicker issue for skolas board. Please refer to Intel doc#723158 for more information. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS on Skolas, verify upd setting. Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Signed-off-by: Selma Bensaid <selma.bensaid(a)intel.com> Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- M src/mainboard/google/brya/variants/brya0/overridetree.cb M src/mainboard/google/brya/variants/skolas/overridetree.cb M src/mainboard/google/brya/variants/skolas4es/overridetree.cb 3 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/68636/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/68636 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Gerrit-Change-Number: 68636 Gerrit-PatchSet: 5 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree
by Bora Guvendik (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Bora Guvendik, Zhixing Ma, Anil Kumar K, Tarun Tuli, Subrata Banik, Selma Bensaid, Kane Chen, Tim Wawrzynczak, Nick Vaccaro. Bora Guvendik has uploaded a new patch set (#7) to the change originally created by Selma Bensaid. ( https://review.coreboot.org/c/coreboot/+/68635 ) Change subject: soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree ...................................................................... soc/intel/alderlake: Hook up DisableDynamicTccoldHandshake to dev tree This commit provides a dev tree setting for partners to enable/disable TccoldHandshake for the sighting in doc:723158 BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=compile ok and FSP UPD is config properly Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Signed-off-by: Kane Chen <kane.chen(a)intel.corp-partner.google.com> --- M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/romstage/fsp_params.c 2 files changed, 29 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/68635/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/68635 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica13b98204acebef7f0b9a4411b4ac19f53cad6e Gerrit-Change-Number: 68635 Gerrit-PatchSet: 7 Gerrit-Owner: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Selma Bensaid <selma.bensaid(a)intel.com> Gerrit-Attention: Kane Chen <kane.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit February 2023