coreboot-gerrit February 2023

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[S] Change in coreboot[master]: util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOL
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Julius Werner, Nick Vaccaro, Yu-Ping Wu. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71296 ) Change subject: util/cbfstool: Add eventLog support for ELOG_TYPE_FW_EARLY_SOL ...................................................................... Patch Set 13: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/71296 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3913cb8501de9a2605266cf9988a7195576cb91d Gerrit-Change-Number: 71296 Gerrit-PatchSet: 13 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 17:04:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Paul Menzel, Julius Werner, Nick Vaccaro, Yu-Ping Wu. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72670 ) Change subject: commonlib: Add ELOG_TYPE_FW_EARLY_SOL eventLog type ...................................................................... Patch Set 7: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/elog.h: https://review.coreboot.org/c/coreboot/+/72670/comment/26fc7f59_1538a5b5 PS7, Line 368: Why do you have two spaces here ? My understanding of this convention is that the "header" (line 368) here should only have one space and the following two spaces. -- To view, visit https://review.coreboot.org/c/coreboot/+/72670 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bd5a250c0be824dbbad0236cee7d61a1ffdbc6c Gerrit-Change-Number: 72670 Gerrit-PatchSet: 7 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 17:03:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/apl: Move cpu cluster to chipset.cb
by Lean Sheng Tan (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Felix Singer, Sean Rhodes, Nico Huber, Maxim Polyakov, Arthur Heymans, Werner Zeh. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72704 ) Change subject: soc/intel/apl: Move cpu cluster to chipset.cb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Gerrit-Change-Number: 72704 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <felixsinger(a)posteo.net> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 17:01:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/jsk: Move ME FSR structures to pertinent header
by Lean Sheng Tan (Code Review) 01 Feb '23

01 Feb '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72414 ) Change subject: soc/intel/jsk: Move ME FSR structures to pertinent header ...................................................................... soc/intel/jsk: Move ME FSR structures to pertinent header This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/72414 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/jasperlake/include/soc/me.h 1 file changed, 52 insertions(+), 71 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/jasperlake/include/soc/me.h b/src/soc/intel/jasperlake/include/soc/me.h index 7319690..951f652 100644 --- a/src/soc/intel/jasperlake/include/soc/me.h +++ b/src/soc/intel/jasperlake/include/soc/me.h @@ -7,23 +7,19 @@ union me_hfsts1 { uint32_t data; struct { - uint32_t working_state: 4; - uint32_t mfg_mode: 1; - uint32_t fpt_bad: 1; - uint32_t operation_state: 3; - uint32_t fw_init_complete: 1; - uint32_t ft_bup_ld_flr: 1; - uint32_t update_in_progress: 1; - uint32_t error_code: 4; - uint32_t operation_mode: 4; - uint32_t reset_count: 4; - uint32_t boot_options_present: 1; - uint32_t reserved1: 1; - uint32_t bist_test_state: 1; - uint32_t bist_reset_request: 1; - uint32_t current_power_source: 2; - uint32_t reserved: 1; - uint32_t d0i3_support_valid: 1; + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t update_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reserved_0 : 4; + uint32_t boot_options_present : 1; + uint32_t reserved_1 : 6; + uint32_t d0i3_support_valid : 1; } __packed fields; }; @@ -31,23 +27,12 @@ union me_hfsts2 { uint32_t data; struct { - uint32_t nftp_load_failure : 1; - uint32_t icc_prog_status : 2; - uint32_t invoke_mebx : 1; + uint32_t reserved_0 : 4; uint32_t cpu_replaced : 1; - uint32_t rsvd0 : 1; - uint32_t mfs_failure : 1; - uint32_t warm_reset_rqst : 1; + uint32_t reserved_1 : 3; uint32_t cpu_replaced_valid : 1; uint32_t low_power_state : 1; - uint32_t me_power_gate : 1; - uint32_t ipu_needed : 1; - uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; - uint32_t listener_change : 1; - uint32_t status_data : 8; - uint32_t current_pmevent : 4; - uint32_t phase : 4; + uint32_t reserved_2 : 22; } __packed fields; }; @@ -55,9 +40,9 @@ union me_hfsts3 { uint32_t data; struct { - uint32_t reserved_0: 4; - uint32_t fw_sku: 3; - uint32_t reserved: 25; + uint32_t reserved_0 : 4; + uint32_t fw_sku : 3; + uint32_t reserved_1 : 25; } __packed fields; }; @@ -65,15 +50,7 @@ union me_hfsts4 { uint32_t data; struct { - uint32_t rsvd0 : 9; - uint32_t enforcement_flow : 1; - uint32_t sx_resume_type : 1; - uint32_t rsvd1 : 1; - uint32_t tpms_disconnected : 1; - uint32_t rvsd2 : 1; - uint32_t fwsts_valid : 1; - uint32_t boot_guard_self_test : 1; - uint32_t rsvd3 : 16; + uint32_t reserved_0; } __packed fields; }; @@ -81,18 +58,7 @@ union me_hfsts5 { uint32_t data; struct { - uint32_t acm_active : 1; - uint32_t valid : 1; - uint32_t result_code_source : 1; - uint32_t error_status_code : 5; - uint32_t acm_done_sts : 1; - uint32_t timeout_count : 7; - uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; - uint32_t start_enforcement : 1; + uint32_t reserved_0; } __packed fields; }; @@ -100,23 +66,9 @@ union me_hfsts6 { uint32_t data; struct { - uint32_t force_boot_guard_acm : 1; + uint32_t reserved_0 : 1; uint32_t cpu_debug_disable : 1; - uint32_t bsp_init_disable : 1; - uint32_t protect_bios_env : 1; - uint32_t rsvd0 : 2; - uint32_t error_enforce_policy : 2; - uint32_t measured_boot : 1; - uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; - uint32_t key_manifest_id : 4; - uint32_t boot_policy_status : 1; - uint32_t error : 1; - uint32_t boot_guard_disable : 1; - uint32_t fpf_disable : 1; - uint32_t fpf_soc_lock : 1; + uint32_t reserved_1 : 29; uint32_t txt_support : 1; } __packed fields; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/72414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58faed286718f5eab714cd39001177e50feb4f8b Gerrit-Change-Number: 72414 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/skl: Move ME FSR structures to pertinent header
by Lean Sheng Tan (Code Review) 01 Feb '23

01 Feb '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72415 ) Change subject: soc/intel/skl: Move ME FSR structures to pertinent header ...................................................................... soc/intel/skl: Move ME FSR structures to pertinent header This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72415 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/skylake/include/soc/me.h 1 file changed, 89 insertions(+), 49 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/soc/intel/skylake/include/soc/me.h b/src/soc/intel/skylake/include/soc/me.h index 5dbcefe..ffeb2f0 100644 --- a/src/soc/intel/skylake/include/soc/me.h +++ b/src/soc/intel/skylake/include/soc/me.h @@ -108,72 +108,83 @@ #define ME_HFS2_PMEVENT_CM3_CM3PG 0xe #define ME_HFS2_PMEVENT_CM0PG_CM0 0xf +/* FPF State */ +#define ME_HFS6_FPF_NOT_COMMITTED 0x0 +#define ME_HFS6_FPF_ERROR 0x2 + /* ME Host Firmware Status register 1 */ union me_hfsts1 { - u32 data; + uint32_t data; struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 reserved1: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 d3_support_valid: 1; - u32 d0i3_support_valid: 1; + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t update_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reserved_0 : 4; + uint32_t boot_options_present : 1; + uint32_t reserved_1 : 5; + uint32_t d3_support_valid : 1; + uint32_t d0i3_support_valid : 1; } __packed fields; }; +/* ME Host Firmware Status register 2 */ union me_hfsts2 { - u32 data; + uint32_t data; struct { - u32 reserved1: 3; - u32 invoke_mebx: 1; - u32 cpu_replaced_sts: 1; - u32 reserved2: 1; - u32 mfs_failure: 1; - u32 warm_reset_request: 1; - u32 cpu_replaced_valid: 1; - u32 low_power_state: 1; - u32 power_gating_ind: 1; - u32 reserved3: 1; - u32 fw_upd_forced_sb: 1; - u32 reserved4: 3; - u32 current_state: 8; - u32 current_pmevent: 4; - u32 progress_code: 4; + uint32_t reserved_0 : 4; + uint32_t cpu_replaced_sts : 1; + uint32_t reserved_1 : 3; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t reserved_2 : 6; + uint32_t current_state : 8; + uint32_t current_pmevent : 4; + uint32_t progress_code : 4; } __packed fields; }; +/* ME Host Firmware Status register 3 */ union me_hfsts3 { - u32 data; + uint32_t data; struct { - u32 reserved1: 4; - u32 fw_sku: 3; - u32 encrypt_key_check: 1; - u32 pch_config_change: 1; - u32 reserved2: 21; - u32 encrypt_key_override: 1; - u32 power_down_mitigation: 1; + uint32_t reserved_0 : 4; + uint32_t fw_sku : 3; + uint32_t encrypt_key_check : 1; + uint32_t pch_config_change : 1; + uint32_t reserved_1 : 21; + uint32_t encrypt_key_override : 1; + uint32_t power_down_mitigation : 1; } __packed fields; }; -#define ME_HFS6_FPF_NOT_COMMITTED 0x0 -#define ME_HFS6_FPF_ERROR 0x2 - -union me_hfsts6 { - u32 data; +/* ME Host Firmware Status register 4 */ +union me_hfsts4 { + uint32_t data; struct { - u32 reserved1: 30; - u32 fpf_nvars: 2; + uint32_t reserved_0; + } __packed fields; +}; + +/* ME Host Firmware Status register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* ME Host Firmware Status register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t reserved1 : 30; + uint32_t fpf_nvars : 2; } __packed fields; }; -- To view, visit https://review.coreboot.org/c/coreboot/+/72415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic42c67163fe42392952499293e91e35537cb9147 Gerrit-Change-Number: 72415 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/cnl: Move ME FSR structures to pertinent header
by Lean Sheng Tan (Code Review) 01 Feb '23

01 Feb '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72412 ) Change subject: soc/intel/cnl: Move ME FSR structures to pertinent header ...................................................................... soc/intel/cnl: Move ME FSR structures to pertinent header This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72412 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/cannonlake/include/soc/me.h M src/soc/intel/cannonlake/me.c 2 files changed, 86 insertions(+), 114 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/cannonlake/include/soc/me.h b/src/soc/intel/cannonlake/include/soc/me.h index 705bb9f..36b062e 100644 --- a/src/soc/intel/cannonlake/include/soc/me.h +++ b/src/soc/intel/cannonlake/include/soc/me.h @@ -5,43 +5,71 @@ /* ME Host Firmware Status register 1 */ union me_hfsts1 { - u32 data; + uint32_t data; struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; -#if CONFIG(SOC_INTEL_COMETLAKE) - u32 invoke_enhance_dbg_mode:1; -#else - u32 reserved0: 1; -#endif - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 reserved1: 1; - u32 d0i3_support_valid: 1; + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t update_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reserved_0 : 4; + uint32_t boot_options_present : 1; + uint32_t reserved_1 : 6; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t reserved_0 : 4; + uint32_t cpu_replaced : 1; + uint32_t reserved_1 : 3; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t reserved_2 : 22; } __packed fields; }; /* ME Host Firmware Status Register 3 */ union me_hfsts3 { - u32 data; + uint32_t data; struct { - u32 reserved_0: 4; - u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; + uint32_t reserved_0 : 4; + uint32_t fw_sku : 3; + uint32_t reserved_1 : 25; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t reserved_0 : 1; + uint32_t cpu_debug_disable : 1; + uint32_t reserved_1 : 29; + uint32_t txt_support : 1; } __packed fields; }; diff --git a/src/soc/intel/cannonlake/me.c b/src/soc/intel/cannonlake/me.c index 7bbe1ae..e5025e8 100644 --- a/src/soc/intel/cannonlake/me.c +++ b/src/soc/intel/cannonlake/me.c @@ -10,90 +10,6 @@ #include <soc/pci_devs.h> #include <stdint.h> -/* Host Firmware Status Register 2 */ -union me_hfsts2 { - uint32_t data; - struct { - uint32_t nftp_load_failure : 1; - uint32_t icc_prog_status : 2; - uint32_t invoke_mebx : 1; - uint32_t cpu_replaced : 1; - uint32_t rsvd0 : 1; - uint32_t mfs_failure : 1; - uint32_t warm_reset_rqst : 1; - uint32_t cpu_replaced_valid : 1; - uint32_t low_power_state : 1; - uint32_t me_power_gate : 1; - uint32_t ipu_needed : 1; - uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; - uint32_t listener_change : 1; - uint32_t status_data : 8; - uint32_t current_pmevent : 4; - uint32_t phase : 4; - } __packed fields; -}; - -/* Host Firmware Status Register 4 */ -union me_hfsts4 { - uint32_t data; - struct { - uint32_t rsvd0 : 9; - uint32_t enforcement_flow : 1; - uint32_t sx_resume_type : 1; - uint32_t rsvd1 : 1; - uint32_t tpms_disconnected : 1; - uint32_t rvsd2 : 1; - uint32_t fwsts_valid : 1; - uint32_t boot_guard_self_test : 1; - uint32_t rsvd3 : 16; - } __packed fields; -}; - -/* Host Firmware Status Register 5 */ -union me_hfsts5 { - uint32_t data; - struct { - uint32_t acm_active : 1; - uint32_t valid : 1; - uint32_t result_code_source : 1; - uint32_t error_status_code : 5; - uint32_t acm_done_sts : 1; - uint32_t timeout_count : 7; - uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; - uint32_t start_enforcement : 1; - } __packed fields; -}; - -/* Host Firmware Status Register 6 */ -union me_hfsts6 { - uint32_t data; - struct { - uint32_t force_boot_guard_acm : 1; - uint32_t cpu_debug_disable : 1; - uint32_t bsp_init_disable : 1; - uint32_t protect_bios_env : 1; - uint32_t rsvd0 : 2; - uint32_t error_enforce_policy : 2; - uint32_t measured_boot : 1; - uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; - uint32_t key_manifest_id : 4; - uint32_t boot_policy_status : 1; - uint32_t error : 1; - uint32_t boot_guard_disable : 1; - uint32_t fpf_disable : 1; - uint32_t fpf_soc_lock : 1; - uint32_t txt_support : 1; - } __packed fields; -}; - void dump_me_status(void *unused) { union me_hfsts1 hfsts1; -- To view, visit https://review.coreboot.org/c/coreboot/+/72412 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34d3c4a60653fe0c1766cd50c96b8d3fe63637d1 Gerrit-Change-Number: 72412 Gerrit-PatchSet: 5 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
by Tarun Tuli (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Nick Vaccaro. Hello build bot (Jenkins), Subrata Banik, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71295 to look at the new patch set (#18). Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL ...................................................................... soc/intel/alderlake: Add entries to eventLog on invocation of early SOL If we show the user early signs of life during CSE FW sync or MRC (re)training, log these to the eventLog (ELOG_TYPE_FW_EARLY_SOL) BUG=b:264648959 TEST=event shows in eventlog after CSE sync and/or MRC Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Signed-off-by: Tarun Tuli <taruntuli(a)intel.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/alderlake/romstage/ux.c M src/soc/intel/alderlake/romstage/ux.h 4 files changed, 28 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/71295/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/71295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Gerrit-Change-Number: 71295 Gerrit-PatchSet: 18 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
by Tarun Tuli (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71295 ) Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL ...................................................................... Patch Set 17: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/71295/comment/6618f6b8_9a3762a3 PS15, Line 10: retraining > training (it could technically be the first one). Done File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/71295/comment/c63deb7d_ac2ea170 PS15, Line 23: nclude <elog.h> > Usually, includes should follow the alphabetical order. Done File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/71295/comment/b27e6aa5_0c87c0d0 PS15, Line 27: include <elog.h> > Same here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/71295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Gerrit-Change-Number: 71295 Gerrit-PatchSet: 17 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:56:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71295 ) Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL ...................................................................... Patch Set 15: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/71295/comment/0b2f2682_a639715d PS15, Line 10: retraining training (it could technically be the first one). -- To view, visit https://review.coreboot.org/c/coreboot/+/71295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Gerrit-Change-Number: 71295 Gerrit-PatchSet: 15 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:54:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[master]: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL
by Jérémy Compostella (Code Review) 01 Feb '23

01 Feb '23

Attention is currently required from: Tarun Tuli, Kapil Porwal, Nick Vaccaro. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71295 ) Change subject: soc/intel/alderlake: Add entries to eventLog on invocation of early SOL ...................................................................... Patch Set 15: (2 comments) File src/soc/intel/alderlake/romstage/fsp_params.c: https://review.coreboot.org/c/coreboot/+/71295/comment/4442d22c_24ee4a3d PS15, Line 23: nclude <elog.h> Usually, includes should follow the alphabetical order. File src/soc/intel/alderlake/romstage/romstage.c: https://review.coreboot.org/c/coreboot/+/71295/comment/3d5feddc_ed3cbe94 PS15, Line 27: include <elog.h> Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/71295 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8181370633a1ecff77b051d3110f593c3eb484a2 Gerrit-Change-Number: 71295 Gerrit-PatchSet: 15 Gerrit-Owner: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Wed, 01 Feb 2023 16:53:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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