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Change subject: bsd/cb_err: Add error code for UEFI variable store
......................................................................
bsd/cb_err: Add error code for UEFI variable store
Add a new set of errors that will be used by the introduced EFI
non-volatile variable store in flash.
Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90
Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com>
---
M src/commonlib/bsd/include/commonlib/bsd/cb_err.h
1 file changed, 23 insertions(+), 0 deletions(-)
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Change subject: mb/google/brya/var/skolas: add dptf settings
......................................................................
mb/google/brya/var/skolas: add dptf settings
Add RPL 28W dptf settings for Skolas
BUG=b:235311241
BRANCH=firmware-brya-14505.B
TEST=Built and tested on skolas
Change-Id: I4364ca6a50906c2a6dd0e754238264c680e7ebd0
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---
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Change subject: mb/google/brya/var/skolas: update PL1 minimum value
......................................................................
mb/google/brya/var/skolas: update PL1 minimum value
Update Power Limit1 (PL1) minimum value to 15W based on the skolas
design.
BRANCH=firmware-brya-14505.B
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Change subject: mb/google/brya/var/skolas: update dptf thermal settings
......................................................................
mb/google/brya/var/skolas: update dptf thermal settings
Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast. This change is based on the discussion on
bug:235311241 comment#7.
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Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
---
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Change subject: mb/google/brya/var/skolas: update dptf thermal settings
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/71692/comment/9bb13450_c9f7701f
PS4, Line 14: BRANCH=None
> Yes. I'll update BRANCH info with "firmware-brya-14505.B".
Done
Patchset:
PS1:
> We are waiting for comment from Compal on this patch as per the discussion on bug:235311241.
I'll submit next version.
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Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/fast_spi.h:
https://review.coreboot.org/c/coreboot/+/71953/comment/bd92793a_3c563b9e
PS6, Line 107: * Set FAST_SPIBAR BIOS Decode Lock bit.
> Please remove the dot/period at the end.
Done
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Change subject: soc/intel/common/block/fast_spi: Add SPI BIOS decode lock
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/common/block/fast_spi/fast_spi.c:
https://review.coreboot.org/c/coreboot/+/71953/comment/28efe9c7_7550591f
PS6, Line 467: pci_write_config32(dev, SPI_BIOS_DECODE_EN, bde);
> Can you use `pci_or_config32()`?
I checked the implementation of pci_or_config32(), both pci_read_config32() and pci_write_config32() will also be involked via pci_update_config32(). I see there is no difference to me.
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Change subject: soc/intel/tgl: Move ME FSR structures to pertinent header
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/72416/comment/7949d990_55bb34f3
PS3, Line 7: soc/intel/tgl: Move ME FSR structures to pertinent header
> Is it not easier and cleaner defining those structs (txt_support/cpu_debug_disable) and dependent AP […]
Currently multiple me.h headers are scattered in different board variants. Keeping version control ME HFSR headers (18.x_ME.h, 16.x_ME.h etc) in common will increase readability.
Apart from this keeping ME source in common will help to reduce multiple set of almost similar source code into single, hence easier to maintain.
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Change subject: soc/intel/alderlake: Add missing DSDT device
......................................................................
Patch Set 1: Code-Review+2
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