coreboot-gerrit February 2023

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Bill XIE has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/72764 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... Abandoned It seems that duplicated change ID is expected. Sorry for the disturbance. -- To view, visit https://review.coreboot.org/c/coreboot/+/72764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: Iaf03ce01a2160108c412caf1ea6335fa59382bfa Gerrit-Change-Number: 72764 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Bill XIE has restored this change. ( https://review.coreboot.org/c/coreboot/+/72763 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... Restored -- To view, visit https://review.coreboot.org/c/coreboot/+/72763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Gerrit-Change-Number: 72763 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: restore

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Bill XIE has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/72763 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... Abandoned It has duplicated change ID. We might review CB:72764 instead. -- To view, visit https://review.coreboot.org/c/coreboot/+/72763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Gerrit-Change-Number: 72763 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by build bot (Jenkins) (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Angel Pons. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72764 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... Patch Set 1: (1 comment) Commit Message: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169816): https://review.coreboot.org/c/coreboot/+/72764/comment/4190f7b2_6ca9a612 PS1, Line 15: Cherry-picked from commit b184e6e0a1cc ("nb/intel/{sandybridge, Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit b184e6e0a1cc ("nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw")' -- To view, visit https://review.coreboot.org/c/coreboot/+/72764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: Iaf03ce01a2160108c412caf1ea6335fa59382bfa Gerrit-Change-Number: 72764 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 13:08:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Bill XIE has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72764 ) Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Cherry-picked from commit b184e6e0a1cc ("nb/intel/{sandybridge, haswell}: Generate IOAPIC DMAR entries from hw"). Change-Id: Iaf03ce01a2160108c412caf1ea6335fa59382bfa Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c 2 files changed, 27 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/72764/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 290dc1e..8d179aa 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" @@ -38,8 +39,9 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c2f6eae..8be161e 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "sandybridge.h" @@ -42,8 +43,9 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) -- To view, visit https://review.coreboot.org/c/coreboot/+/72764 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: Iaf03ce01a2160108c412caf1ea6335fa59382bfa Gerrit-Change-Number: 72764 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Nico Huber, Angel Pons, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Angel Pons, Arthur Heymans, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72763 to look at the new patch set (#2). Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Cherry-picked from commit b184e6e0a1cc ("nb/intel/{sandybridge, haswell}: Generate IOAPIC DMAR entries from hw"). Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c 2 files changed, 31 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/72763/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Gerrit-Change-Number: 72763 Gerrit-PatchSet: 2 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[4.19_branch]: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
by Bill XIE (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Nico Huber, Arthur Heymans. Hello build bot (Jenkins), Nico Huber, Arthur Heymans, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/72763 to review the following change. Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw ...................................................................... nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries. This can restore s3 resume capability for Sandy Bridge platforms lost after commit d165357ec37c ("sb,soc/intel: Use register_new_ioapic_gsi0()"). Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org> Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72513 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/haswell/acpi.c M src/northbridge/intel/sandybridge/acpi.c 2 files changed, 28 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/72763/1 diff --git a/src/northbridge/intel/haswell/acpi.c b/src/northbridge/intel/haswell/acpi.c index 290dc1e..8d179aa 100644 --- a/src/northbridge/intel/haswell/acpi.c +++ b/src/northbridge/intel/haswell/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "haswell.h" @@ -38,8 +39,9 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, vtvc0bar); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c index c2f6eae..8be161e 100644 --- a/src/northbridge/intel/sandybridge/acpi.c +++ b/src/northbridge/intel/sandybridge/acpi.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <commonlib/helpers.h> #include <acpi/acpi.h> +#include <arch/ioapic.h> #include <device/device.h> #include <device/pci_ops.h> #include "sandybridge.h" @@ -42,8 +43,9 @@ const unsigned long tmp = current; current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, 0, VTVC0_BASE); - current += acpi_create_dmar_ds_ioapic(current, 2, PCH_IOAPIC_PCI_BUS, - PCH_IOAPIC_PCI_SLOT, 0); + current += acpi_create_dmar_ds_ioapic_from_hw(current, IO_APIC_ADDR, + PCH_IOAPIC_PCI_BUS, + PCH_IOAPIC_PCI_SLOT, 0); size_t i; for (i = 0; i < 8; ++i) -- To view, visit https://review.coreboot.org/c/coreboot/+/72763 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: 4.19_branch Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656 Gerrit-Change-Number: 72763 Gerrit-PatchSet: 1 Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a missing RPL-P power limits configuration
by Tarun Tuli (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Bora Guvendik, Zhixing Ma, Hannah Williams, Cliff Huang, Subrata Banik, Jérémy Compostella, Nick Vaccaro. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72734 ) Change subject: soc/intel/alderlake: Add a missing RPL-P power limits configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Gerrit-Change-Number: 72734 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 12:27:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/rex: Use OV13B10 sensor for Proto 1 SKUs
by Tarun Tuli (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Subrata Banik, Ivy Jian, Eric Lai. Tarun Tuli has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/70226 ) Change subject: mb/google/rex: Use OV13B10 sensor for Proto 1 SKUs ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/70226 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Gerrit-Change-Number: 70226 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Ivy Jian <ivy.jian(a)quanta.corp-partner.google.com> Gerrit-Attention: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 12:18:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: bsd/cb_err: Add error code for UEFI variable store
by David Milosevic (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Maximilian Brune, Angel Pons, Julius Werner. David Milosevic has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61960 ) Change subject: bsd/cb_err: Add error code for UEFI variable store ...................................................................... Patch Set 13: (1 comment) File src/commonlib/bsd/include/commonlib/bsd/cb_err.h: https://review.coreboot.org/c/coreboot/+/61960/comment/39dba791_23f69f69 PS11, Line 46: CB_EFI_FVH_INVALID = -500, /**< UEFI FVH is corrupted */ > Not to be padentic, but for the comment, could you write out the FVH abbreviation. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/61960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Gerrit-Change-Number: 61960 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph Gerrit-Comment-Date: Fri, 03 Feb 2023 12:03:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023