coreboot-gerrit February 2023

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a missing RPL-P power limits configuration
by Nick Vaccaro (Code Review) 03 Feb '23

03 Feb '23

Nick Vaccaro has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72734 ) Change subject: soc/intel/alderlake: Add a missing RPL-P power limits configuration ...................................................................... soc/intel/alderlake: Add a missing RPL-P power limits configuration This patch adds the {MCH:a706, TDP:28W} missing 28W configuration. BUG=b:267666609 BRANCH=firmware-brya-14505.B TEST=Power Limit are properly set on skolas 28W Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72734 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Tarun Tuli <taruntuli(a)google.com> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/alderlake/chip.h 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Nick Vaccaro: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve Tarun Tuli: Looks good to me, approved diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 5173b1c..8e76e55 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -133,6 +133,7 @@ { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, -- To view, visit https://review.coreboot.org/c/coreboot/+/72734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Gerrit-Change-Number: 72734 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/alderlake: Add a missing RPL-P power limits configuration
by Nick Vaccaro (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Bora Guvendik, Zhixing Ma, Hannah Williams, Cliff Huang, Subrata Banik, Jérémy Compostella. Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72734 ) Change subject: soc/intel/alderlake: Add a missing RPL-P power limits configuration ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72734 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice35d622eeec5799c53de086430d00dc8789097e Gerrit-Change-Number: 72734 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Zhixing Ma <zhixing.ma(a)intel.com> Gerrit-Attention: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 18:23:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/amdfwtool: add comment about reused PSP firmware type 0x5f
by Fred Reitberger (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Arthur Heymans, Felix Held. Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72713 ) Change subject: util/amdfwtool: add comment about reused PSP firmware type 0x5f ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Gerrit-Change-Number: 72713 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 18:17:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Martin Roth, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72737 to look at the new patch set (#4). Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 28 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/72737/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: update USB ports
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72773 to look at the new patch set (#2). Change subject: soc/amd/phoenix/chipset.cb: update USB ports ...................................................................... soc/amd/phoenix/chipset.cb: update USB ports Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 77 insertions(+), 51 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/72773/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Gerrit-Change-Number: 72773 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72771 to look at the new patch set (#3). Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... soc/amd/phoenix/chipset.cb: add remaining PCI devices The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Also the USB port configuration still needs to be updated. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72771/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/var/skolas: update dptf thermal settings
by Bora Guvendik (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Subrata Banik, Jérémy Compostella, Sumeet R Pawnikar, Nick Vaccaro. Bora Guvendik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71692 ) Change subject: mb/google/brya/var/skolas: update dptf thermal settings ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: Don't we need the same changes for Brya0? -- To view, visit https://review.coreboot.org/c/coreboot/+/71692 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c Gerrit-Change-Number: 71692 Gerrit-PatchSet: 5 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: AlanKY Lee <alanky_lee(a)compal.corp-partner.google.com> Gerrit-CC: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-CC: Vidya Gopalakrishnan <vidya.gopalakrishnan(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 17:15:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: update USB ports
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72773 ) Change subject: soc/amd/phoenix/chipset.cb: update USB ports ...................................................................... soc/amd/phoenix/chipset.cb: update USB ports Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 53 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/72773/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index c6fb321..bd06a54 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -44,11 +44,23 @@ device usb 3.0 alias usb3_port0 off end end chip drivers/usb/acpi + device usb 3.1 alias usb3_port1 off end + end + chip drivers/usb/acpi device usb 2.0 alias usb2_port0 off end end chip drivers/usb/acpi device usb 2.1 alias usb2_port1 off end end + chip drivers/usb/acpi + device usb 2.2 alias usb2_port2 off end + end + chip drivers/usb/acpi + device usb 2.3 alias usb2_port3 off end + end + chip drivers/usb/acpi + device usb 2.4 alias usb2_port4 off end + end end end end @@ -57,19 +69,10 @@ register "type" = "UPC_TYPE_HUB" device usb 0.0 alias xhci_1_root_hub off chip drivers/usb/acpi - device usb 3.0 alias usb3_port2 off end + device usb 3.0 alias usb3_port5 off end end chip drivers/usb/acpi - device usb 3.1 alias usb3_port3 off end - end - chip drivers/usb/acpi - device usb 2.0 alias usb2_port2 off end - end - chip drivers/usb/acpi - device usb 2.1 alias usb2_port3 off end - end - chip drivers/usb/acpi - device usb 2.2 alias usb2_port4 off end + device usb 2.0 alias usb2_port5 off end end end end @@ -88,8 +91,32 @@ ops amd_internal_pcie_gpp_ops device pci 0.0 on end # dummy, do not disable device pci 0.2 alias i2s_ac97 off end - device pci 0.3 alias usb4_xhci_0 off end - device pci 0.4 alias usb4_xhci_1 off end + device pci 0.3 alias usb4_xhci_0 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port6 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port6 off end + end + end + end + end + device pci 0.4 alias usb4_xhci_1 off + chip drivers/usb/acpi + register "type" = "UPC_TYPE_HUB" + device usb 0.0 alias xhci_1_root_hub off + chip drivers/usb/acpi + device usb 3.0 alias usb3_port7 off end + end + chip drivers/usb/acpi + device usb 2.0 alias usb2_port7 off end + end + end + end + end device pci 0.5 alias usb4_router_0 off end device pci 0.6 alias usb4_router_1 off end end -- To view, visit https://review.coreboot.org/c/coreboot/+/72773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Gerrit-Change-Number: 72773 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72771 to look at the new patch set (#2). Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... soc/amd/phoenix/chipset.cb: add remaining PCI devices The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Also the USB port configuration still needs to be updated. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72771/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/intel/rtd3: Fix S3 on TGL and ADL
by Sean Rhodes (Code Review) 03 Feb '23

03 Feb '23

Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72765 ) Change subject: soc/intel/rtd3: Fix S3 on TGL and ADL ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/72765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Gerrit-Change-Number: 72765 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Comment-Date: Fri, 03 Feb 2023 16:39:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit February 2023