coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[master]: treewide: Remove unuseful "_HID: Hardware ID" comment
by Tim Crawford (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Sean Rhodes, Jeremy Soller, Nick Vaccaro, Elyes Haouas, Felix Held. Tim Crawford has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72661 ) Change subject: treewide: Remove unuseful "_HID: Hardware ID" comment ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > I'm not sure to understand. […] If we're going to delete all the comments just because ACPI defines them (I assume *all* the ACPI-defined names are getting their comment deleted?), then I would like to at least see the ACPI "documentation" at https://doc.coreboot.org/acpi/index.html updated to link to *actual* ACPI documentation. -- To view, visit https://review.coreboot.org/c/coreboot/+/72661 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5eb1424e9e6c1fbf20cd0bf68fbb52e1ec97f905 Gerrit-Change-Number: 72661 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 16:22:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Crawford <tcrawford(a)system76.com> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72771 ) Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... soc/amd/phoenix/chipset.cb: add remaining PCI devices The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Also the USB port configuration still needs to be updated. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 33 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72771/1 diff --git a/src/soc/amd/phoenix/chipset.cb b/src/soc/amd/phoenix/chipset.cb index e9fd2f2..df62590 100644 --- a/src/soc/amd/phoenix/chipset.cb +++ b/src/soc/amd/phoenix/chipset.cb @@ -24,6 +24,12 @@ device pci 02.5 alias gpp_bridge_2_5 off ops amd_external_pcie_gpp_ops end device pci 02.6 alias gpp_bridge_2_6 off ops amd_external_pcie_gpp_ops end + device pci 03.0 on end # Dummy Host Bridge, do not disable + device pci 03.1 off alias usb4_pcie_bridge_0 end + + device pci 04.0 on end # Dummy Host Bridge, do not disable + device pci 04.1 off alias usb4_pcie_bridge_1 end + device pci 08.0 on end # Dummy Host Bridge, do not disable device pci 08.1 alias gpp_bridge_a off # Internal GPP Bridge 0 to Bus A ops amd_internal_pcie_gpp_ops @@ -72,10 +78,20 @@ device pci 0.6 alias hda off end # Audio Processor HD Audio Controller (main AZ) device pci 0.7 alias mp2 off end # Sensor Fusion Hub (MP2) end - device pci 08.2 alias gpp_bridge_b off ops amd_internal_pcie_gpp_ops end # Internal GPP Bridge 1 to Bus B + device pci 08.2 alias gpp_bridge_b off # Internal GPP Bridge 1 to Bus B + ops amd_internal_pcie_gpp_ops + device pci 0.0 on end # dummy, do not disable + device pci 0.1 alias ipu off end + end + device pci 08.3 alias gpp_bridge_c off # Internal GPP Bridge 2 to Bus C ops amd_internal_pcie_gpp_ops - device pci 0.0 alias xhci_2 off end # Might also be a dummy device with different PCI DID + device pci 0.0 on end # dummy, do not disable + device pci 0.2 alias i2s_ac97 off + device pci 0.3 alias usb4_xhci_0 off + device pci 0.4 alias usb4_xhci_1 off + device pci 0.5 alias usb4_router_0 off + device pci 0.6 alias usb4_router_1 off end device pci 14.0 alias smbus on ops amd_smbus_ops end # primary FCH function -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: acpi/acpigen.h: Fix ACPI OP codes
by Elyes Haouas (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Elyes Haouas. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72757 to look at the new patch set (#4). Change subject: acpi/acpigen.h: Fix ACPI OP codes ...................................................................... acpi/acpigen.h: Fix ACPI OP codes Fix the values according to ACPI specs: https://uefi.org/specs/ACPI/6.5/20_AML_Specification.html?highlight=aml%20b… Change-Id: I51e7f8dc6c0bfef0816ab4da6d96cb0fac873ee8 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/include/acpi/acpigen.h 1 file changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/72757/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72757 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51e7f8dc6c0bfef0816ab4da6d96cb0fac873ee8 Gerrit-Change-Number: 72757 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[master]: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
by Johnny Lin (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Simon Chou, TimLiu-SMCI, Christian Walter, Angel Pons, Arthur Heymans, Jian-Ming Wang, Tim Chu, Shelly Chang. Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71958 ) Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > The diff between the original nb_acpi.c and the new uncore_acpi.c is not shown. […] nb_acpi.c is removed and unified in the newly added uncore_acpi.c, gerrit is not easy to review the differences, but if I cherry-pick it and use 'git show, it can show the differences made to nb_acpi.c and uncore_acpi.c directly for easier review: git log --stat src/soc/intel/xeon_sp/{nb_acpi.c => uncore_acpi.c} git show diff --git a/src/soc/intel/xeon_sp/nb_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c similarity index 58% rename from src/soc/intel/xeon_sp/nb_acpi.c rename to src/soc/intel/xeon_sp/uncore_acpi.c .... -- To view, visit https://review.coreboot.org/c/coreboot/+/71958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Gerrit-Change-Number: 71958 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 15:54:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Martin Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72736 ) Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/phoenix/chipset.cb: https://review.coreboot.org/c/coreboot/+/72736/comment/e4beb13e_efc05452 PS1, Line 12: Dummy Host Bridge > Add comment about disabling to match the others? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 15:42:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72736 to look at the new patch set (#3). Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 35 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/72736/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Martin Roth, Fred Reitberger. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72737 ) Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... Patch Set 2: (1 comment) File src/mainboard/amd/mayan/devicetree_phoenix.cb: https://review.coreboot.org/c/coreboot/+/72737/comment/d4b5a20e_c338873e PS1, Line 163: gpp_bridge_2_2 > I think that should be fixed in a separate commit. This one's just about renaming the devices. this commit is just about renaming the bridges and not to update the bridges in the mainboards. before updating the bridges in the mainboards, the dxio descriptors need to be updated first -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 15:40:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Comment-In-Reply-To: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72737 to look at the new patch set (#2). Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 27 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/72737/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72736 to look at the new patch set (#2). Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 ...................................................................... soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1 Only the PCIe ports on the functions of device 2 were present in the devicetree and had the amd_external_pcie_gpp_ops ops assigned. Add the missing PCIe ports on the functions of device 1 and assign the amd_external_pcie_gpp_ops ops to them. This SoC uses a slightly different naming scheme for its PCIe GPP ports. Previously the PCIe GPP bridge number from the PCI Device ID Assignments table from the PPR was used. Those bridge numbers are one less than the function numbers of the device. This is to function 0 being a dummy bridge to avoid having to shuffle around the function numbers when the first bridge is unused, since the PCIe specification mandates the function 0 to be implemented if any other function on the same device is implemented. In order for the device aliases to be consistent with the PCIe device and function numbers which is way more commonly used and also what lspci shows and what goes into the DXIO descriptors, change the naming scheme of the aliases. This was checked with PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 --- M src/soc/amd/phoenix/chipset.cb 1 file changed, 34 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/72736/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72736 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7 Gerrit-Change-Number: 72736 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Martin Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Fred Reitberger, Felix Held. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72737 ) Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... Patch Set 1: (1 comment) File src/mainboard/amd/mayan/devicetree_phoenix.cb: https://review.coreboot.org/c/coreboot/+/72737/comment/60ece2c4_b8392380 PS1, Line 163: gpp_bridge_2_2 > gpp_bridge_2_3 is NVMe SSD in mayan I think that should be fixed in a separate commit. This one's just about renaming the devices. -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 14:51:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023