Attention is currently required from: Bao Zheng, Paul Menzel, Zheng Bao, Felix Held.
Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72724 )
Change subject: amdfwtool: Remove useless printing out
......................................................................
Patch Set 3: Code-Review+2
--
To view, visit https://review.coreboot.org/c/coreboot/+/72724
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I819633d8d6d1886b48d53e73923add444ca032e4
Gerrit-Change-Number: 72724
Gerrit-PatchSet: 3
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Zheng Bao
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Fri, 03 Feb 2023 14:50:56 +0000
Gerrit-HasComments: No
Gerrit-Has-Labels: Yes
Gerrit-MessageType: comment
Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held.
Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72736 )
Change subject: soc/amd/phoenix/chipset.cb: add missing GPP bridges on device 1
......................................................................
Patch Set 1:
(1 comment)
File src/soc/amd/phoenix/chipset.cb:
https://review.coreboot.org/c/coreboot/+/72736/comment/795d4191_541e2f0f
PS1, Line 12: Dummy Host Bridge
Add comment about disabling to match the others?
--
To view, visit https://review.coreboot.org/c/coreboot/+/72736
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib5c62c1df585877d9b6986a462a3636d4f2eb4c7
Gerrit-Change-Number: 72736
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Fri, 03 Feb 2023 14:49:39 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held.
ritul guru has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72737 )
Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/amd/mayan/devicetree_phoenix.cb:
https://review.coreboot.org/c/coreboot/+/72737/comment/98eeb2c6_afb5f0b4
PS1, Line 163: gpp_bridge_2_2
gpp_bridge_2_3 is NVMe SSD in mayan
--
To view, visit https://review.coreboot.org/c/coreboot/+/72737
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Gerrit-Change-Number: 72737
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: ritul guru <ritul.bits(a)gmail.com>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Fri, 03 Feb 2023 14:43:51 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment
Attention is currently required from: Jason Nien, Matt DeVillier.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Marshall Dawson, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/58552
to look at the new patch set (#36).
Change subject: amdfwtool: Put soc name setting to fw.cfg from command line
......................................................................
amdfwtool: Put soc name setting to fw.cfg from command line
The fw.cfg should combine the SOC name.
This is for future combo feature. Each entry in combo has its own
fw.cfg.
The soc_id in struct cb_config can only be available after the fw.cfg
is processed.
Some functions which take soc_id as a parameter can be simplified.
3/5 (and the key one with same change ID)
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/amdfwtool.c
M util/amdfwtool/data_parse.c
2 files changed, 90 insertions(+), 75 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/58552/36
--
To view, visit https://review.coreboot.org/c/coreboot/+/58552
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib0eead1f2156542ea03d58145f5ad67683bf9b52
Gerrit-Change-Number: 58552
Gerrit-PatchSet: 36
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>
Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-MessageType: newpatchset
Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Zheng Bao, Martin Roth, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Raul Rangel, Jason Nien, Matt DeVillier, Zheng Bao, Martin Roth, Fred Reitberger, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72457
to look at the new patch set (#4).
Change subject: soc/amd/*: Add SOC_NAME in fw.cfg(s)
......................................................................
soc/amd/*: Add SOC_NAME in fw.cfg(s)
2/5
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: I18f73462a3995038fe93750320dfc053fec969ba
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M src/mainboard/google/guybrush/variants/baseboard/amdfw.cfg
M src/mainboard/google/skyrim/amdfw.cfg
M src/soc/amd/cezanne/fw.cfg
M src/soc/amd/common/Makefile.inc
M src/soc/amd/glinda/fw.cfg
M src/soc/amd/mendocino/fw.cfg
M src/soc/amd/phoenix/fw.cfg
M src/soc/amd/picasso/fw.cfg
M src/soc/amd/stoneyridge/fw_cz.cfg
M src/soc/amd/stoneyridge/fw_st.cfg
10 files changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/72457/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/72457
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I18f73462a3995038fe93750320dfc053fec969ba
Gerrit-Change-Number: 72457
Gerrit-PatchSet: 4
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Zheng Bao
Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newpatchset
Attention is currently required from: Jason Glenesk, Martin L Roth, Marshall Dawson, Zheng Bao, Felix Held.
Hello build bot (Jenkins), Jason Glenesk, Martin L Roth, Marshall Dawson, Zheng Bao, Felix Held,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/51881
to look at the new patch set (#6).
Change subject: amdfwtool: Add a function to make the calling stack less deep
......................................................................
amdfwtool: Add a function to make the calling stack less deep
And make less levels of indentations in the code.
Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com>
---
M util/amdfwtool/data_parse.c
1 file changed, 49 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/51881/6
--
To view, visit https://review.coreboot.org/c/coreboot/+/51881
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ib8cae386eace4f423bde9c252992625e1ff3c690
Gerrit-Change-Number: 51881
Gerrit-PatchSet: 6
Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Zheng Bao
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Attention: Zheng Bao
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: newpatchset
Fred Reitberger has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72655 )
Change subject: util/scripts/testsoc: Only select mainboards
......................................................................
util/scripts/testsoc: Only select mainboards
The testsoc script was pulling in odd results when the -K option matched
options in sources, Makefiles, and device trees. Adding another grep to
limit the list to just Kconfig matches ensures that only actual
mainboards are built.
TEST="./util/testsoc -K PICASSO" no longer tries to build mainboard "0"
Signed-off-by: Fred Reitberger <reitbergerfred(a)gmail.com>
Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72655
Reviewed-by: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M util/scripts/testsoc
1 file changed, 21 insertions(+), 1 deletion(-)
Approvals:
build bot (Jenkins): Verified
Martin Roth: Looks good to me, approved
diff --git a/util/scripts/testsoc b/util/scripts/testsoc
index bf23e66..81ce2f0 100755
--- a/util/scripts/testsoc
+++ b/util/scripts/testsoc
@@ -81,7 +81,7 @@
;;
-K | --kconfig)
shift
- mblist=$(grep -r "$1" src/mainboard | sed 's|src/mainboard/||;s|/Kconfig.*||')
+ mblist=$(grep -r "$1" src/mainboard | grep Kconfig | sed 's|src/mainboard/||;s|/Kconfig.*||')
printf "Adding mainboard for %s\n%s\n" "$1" "${mblist}"
echo
mapfile -t mainboards <<<"$mblist"
--
To view, visit https://review.coreboot.org/c/coreboot/+/72655
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I3860df4520a5594fb9c1a06e75487520b7d5d275
Gerrit-Change-Number: 72655
Gerrit-PatchSet: 2
Gerrit-Owner: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: merged
Attention is currently required from: Jason Glenesk, Raul Rangel, Matt DeVillier, Arthur Heymans, Felix Held.
Fred Reitberger has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72739 )
Change subject: soc/amd/common/data_fabric_helper: normalize addresses in debug print
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
> the ffff in the case of the limit being 0 still looks a bit odd to me, but i'd say that that's the c […]
Potentially could use the df_mmio_ctrl union to read control, then something like:
`limit += (control.re | control.we) ? BIT(D18F0_MMIO_SHIFT) - 1 : 0;`
But that's a bit on the complex side.
--
To view, visit https://review.coreboot.org/c/coreboot/+/72739
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I62eeb88ddac6a7a421fccc8e433523459117976a
Gerrit-Change-Number: 72739
Gerrit-PatchSet: 1
Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com>
Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com>
Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org>
Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>
Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Comment-Date: Fri, 03 Feb 2023 13:52:07 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-MessageType: comment
Hello build bot (Jenkins), Nico Huber, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72763
to look at the new patch set (#4).
Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
......................................................................
nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Cherry-picked from
commit b184e6e0a1cc ("nb/intel/{sandybridge,haswell}: Generate IOAPIC
DMAR entries from hw").
Original-signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Original-reviewed-by: Nico Huber <nico.h(a)gmx.de>
Original-reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
---
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/sandybridge/acpi.c
2 files changed, 32 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/72763/4
--
To view, visit https://review.coreboot.org/c/coreboot/+/72763
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: 4.19_branch
Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Gerrit-Change-Number: 72763
Gerrit-PatchSet: 4
Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset
Hello build bot (Jenkins), Nico Huber, Angel Pons, Arthur Heymans,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/72763
to look at the new patch set (#3).
Change subject: nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
......................................................................
nb/intel/{sandybridge,haswell}: Generate IOAPIC DMAR entries from hw
Use acpi_create_dmar_ds_ioapic_from_hw() to generate DMAR entries.
This can restore s3 resume capability for Sandy Bridge platforms lost
after commit d165357ec37c ("sb,soc/intel: Use
register_new_ioapic_gsi0()").
Cherry-picked from commit b184e6e0a1cc ("nb/intel/{sandybridge,
haswell}: Generate IOAPIC DMAR entries from hw").
Original-signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Original-reviewed-on: https://review.coreboot.org/c/coreboot/+/72513
Original-reviewed-by: Nico Huber <nico.h(a)gmx.de>
Original-reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Signed-off-by: Bill XIE <persmule(a)hardenedlinux.org>
---
M src/northbridge/intel/haswell/acpi.c
M src/northbridge/intel/sandybridge/acpi.c
2 files changed, 31 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/72763/3
--
To view, visit https://review.coreboot.org/c/coreboot/+/72763
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: 4.19_branch
Gerrit-Change-Id: I83e735707cd9ff30aa339443593239cd7e3e4656
Gerrit-Change-Number: 72763
Gerrit-PatchSet: 3
Gerrit-Owner: Bill XIE <persmule(a)hardenedlinux.org>
Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com>
Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-MessageType: newpatchset