coreboot-gerrit February 2023

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[S] Change in coreboot[master]: util/scripts/testsoc: Pass arguments to abuild
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72766 ) Change subject: util/scripts/testsoc: Pass arguments to abuild ...................................................................... util/scripts/testsoc: Pass arguments to abuild This allows the user to pass one or more arguments through the testsoc script to abuild. Example: testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN" Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84 --- M util/scripts/testsoc 1 file changed, 27 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/72766/1 diff --git a/util/scripts/testsoc b/util/scripts/testsoc index 81ce2f0..c093042 100755 --- a/util/scripts/testsoc +++ b/util/scripts/testsoc @@ -11,6 +11,9 @@ CPUS=$(nproc || echo "4") NO_CROS=0 +# Extra arguments to pass to abuild +ABUILD_ARGS="" + # Text STYLE variables BOLD="\033[1m" RED='\033[38;5;9m' @@ -26,6 +29,7 @@ Usage: ${PROGNAME} [options] Options: + -a | --abuild "<text>" Specify options to pass to abuild -C | --cpus <num> Specify number of CPUs to use (currently ${CPUS}) -K | --kconfig <CONFIG> Search for Kconfig option -n | --no_cros Don't run chromeos builds @@ -66,7 +70,7 @@ local mblist local mainboards=() - if ! args="$(getopt -l version,help,debug,nocolor,kconfig:,cpus:,no_cros -o C:K:nDhV -- "$@")"; then + if ! args="$(getopt -l version,help,debug,nocolor,kconfig:,cpus:,no_cros,abuild: -o a:C:K:nDhV -- "$@")"; then usage exit 1 fi @@ -75,6 +79,10 @@ while true; do case "$1" in + -a | --abuild) + shift + ABUILD_ARGS=$1 + ;; -C | --cpus) shift CPUS=$1 @@ -155,7 +163,7 @@ rm -rf "./${OUTPUT}" # Non-CrOS build - if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}"; then + if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" ${ABUILD_ARGS}; then _echo_error "Error: Non-cros build of ${board} failed." exit 1 fi @@ -163,7 +171,7 @@ # CrOS build if [[ ${NO_CROS} -eq 0 ]]; then rm -rf "./${OUTPUT}" - if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" --chromeos; then + if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" --chromeos ${ABUILD_ARGS}; then _echo_error "Error: CrOS build of ${board} failed." exit 1 fi -- To view, visit https://review.coreboot.org/c/coreboot/+/72766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84 Gerrit-Change-Number: 72766 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: util/abuild: Add flags to allow abuild to skip boards
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Martin L Roth. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/71730 to look at the new patch set (#3). Change subject: util/abuild: Add flags to allow abuild to skip boards ...................................................................... util/abuild: Add flags to allow abuild to skip boards This change adds 2 command line parameters, --skip_set and --skip_unset that allows abuild to skip boards with particular Kconfig values either set or not set. Note that it only works on BOOL type variables. This can be set on the abuild command line, or the JENKINS_ABUILD_OPT= variable on the make command line. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I43336484cf25f83065ec7facf45c123d831024b5 --- M util/abuild/abuild 1 file changed, 61 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/71730/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/71730 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I43336484cf25f83065ec7facf45c123d831024b5 Gerrit-Change-Number: 71730 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/intel/apl: Move cpu cluster to chipset.cb
by Lean Sheng Tan (Code Review) 03 Feb '23

03 Feb '23

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72704 ) Change subject: soc/intel/apl: Move cpu cluster to chipset.cb ...................................................................... soc/intel/apl: Move cpu cluster to chipset.cb Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/google/octopus/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/baseboard/devicetree.cb M src/mainboard/google/reef/variants/coral/devicetree.cb M src/mainboard/google/reef/variants/pyro/devicetree.cb M src/mainboard/google/reef/variants/sand/devicetree.cb M src/mainboard/google/reef/variants/snappy/devicetree.cb M src/mainboard/intel/apollolake_rvp/devicetree.cb M src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb M src/mainboard/intel/leafhill/devicetree.cb M src/mainboard/intel/minnow3/devicetree.cb M src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb M src/mainboard/kontron/mal10/variants/mal10/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb M src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb M src/mainboard/starlabs/lite/variants/glk/devicetree.cb M src/mainboard/starlabs/lite/variants/glkr/devicetree.cb M src/mainboard/up/squared/devicetree.cb M src/soc/intel/apollolake/chipset_apl.cb M src/soc/intel/apollolake/chipset_glk.cb 24 files changed, 16 insertions(+), 39 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Sean Rhodes: Looks good to me, approved diff --git a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb index eec90bc..7801b0d 100644 --- a/src/mainboard/google/octopus/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/octopus/variants/baseboard/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end register "pcie_rp_clkreq_pin[2]" = "3" # wifi/bt # Disable unused clkreq of PCIe root ports diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 2199ac0..d24e67b 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb index 7052497..f162519 100644 --- a/src/mainboard/google/reef/variants/coral/devicetree.cb +++ b/src/mainboard/google/reef/variants/coral/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index bf40464..79da9fd 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb index 1ee9c38..45007f0 100644 --- a/src/mainboard/google/reef/variants/sand/devicetree.cb +++ b/src/mainboard/google/reef/variants/sand/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb index 7c775ef..ec9ea9c1 100644 --- a/src/mainboard/google/reef/variants/snappy/devicetree.cb +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "0" # wifi/bt # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index ef361b0..a983807 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb index 45fb736..551fc60 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" # Disable unused clkreq of PCIe root ports register "pcie_rp_clkreq_pin[1]" = "3" # wifi/bt diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb index add83fe..0a152b6 100644 --- a/src/mainboard/intel/leafhill/devicetree.cb +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb index add83fe..0a152b6 100644 --- a/src/mainboard/intel/minnow3/devicetree.cb +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -7,8 +7,6 @@ register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" - device cpu_cluster 0 on end - device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb index e77a172..b3f9a6e 100644 --- a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -2,8 +2,6 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - # Override USB port configuration register "usb_config_override" = "1" # USB 2.0 diff --git a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb index 7ce2480..a2a9df4 100644 --- a/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb +++ b/src/mainboard/kontron/mal10/variants/mal10/devicetree.cb @@ -5,7 +5,6 @@ register "enable_vtd" = "1" register "dptf_enable" = "1" - device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 00.1 on end # DPTF diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb index dad319e..a08f053 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb index b728438..b515170 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb index 4fae59e..56d93aa 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb index 586d65e..1c5f797 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb index 40739df..92bba65 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb index c48eb5a..8223f68 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # 0:HS400(Default), 1:HS200, 2:DDR50 diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb index ce716a0..0a080c3 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl7/devicetree.cb @@ -1,7 +1,5 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end - register "sci_irq" = "SCIS_IRQ10" # EMMC TX DATA Delay 1 diff --git a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb index 709d8e1..f1ace5a 100644 --- a/src/mainboard/starlabs/lite/variants/glk/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glk/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb index 96011ea..71932a6 100644 --- a/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb +++ b/src/mainboard/starlabs/lite/variants/glkr/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/apollolake - device cpu_cluster 0 on end # Graphics # TODO: diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb index 867f3a5..4b0d5f7 100644 --- a/src/mainboard/up/squared/devicetree.cb +++ b/src/mainboard/up/squared/devicetree.cb @@ -20,7 +20,6 @@ # 0:HS400 (Default) 1:HS200 2:DDR50 register "emmc_host_max_speed" = "1" - device cpu_cluster 0 on end device domain 0 on subsystemid 0x8086 0x7270 inherit device pci 00.0 on end # - Host Bridge diff --git a/src/soc/intel/apollolake/chipset_apl.cb b/src/soc/intel/apollolake/chipset_apl.cb index 8a1b501..b4f1659 100644 --- a/src/soc/intel/apollolake/chipset_apl.cb +++ b/src/soc/intel/apollolake/chipset_apl.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF diff --git a/src/soc/intel/apollolake/chipset_glk.cb b/src/soc/intel/apollolake/chipset_glk.cb index 0043630..07eecf5 100644 --- a/src/soc/intel/apollolake/chipset_glk.cb +++ b/src/soc/intel/apollolake/chipset_glk.cb @@ -1,4 +1,5 @@ chip soc/intel/apollolake + device cpu_cluster 0 on end device domain 0 on device pci 00.0 alias system_agent on end # Host Bridge device pci 00.1 alias dptf on end # DPTF -- To view, visit https://review.coreboot.org/c/coreboot/+/72704 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Gerrit-Change-Number: 72704 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: bsd/cb_err: Add error code for UEFI variable store
by Lean Sheng Tan (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Maximilian Brune, Angel Pons, Julius Werner, David Milosevic. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/61960 ) Change subject: bsd/cb_err: Add error code for UEFI variable store ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/61960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6baea9fb138d1a2755d22a3d587105793adb9c90 Gerrit-Change-Number: 61960 Gerrit-PatchSet: 13 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Joey Madafferi <joeymadafferi(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph Gerrit-Attention: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 19:53:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: update USB ports
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72773 to look at the new patch set (#3). Change subject: soc/amd/phoenix/chipset.cb: update USB ports ...................................................................... soc/amd/phoenix/chipset.cb: update USB ports Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 83 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/72773/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Gerrit-Change-Number: 72773 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Matt DeVillier, Fred Reitberger. Hello Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72771 to look at the new patch set (#4). Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... soc/amd/phoenix/chipset.cb: add remaining PCI devices The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 34 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/72771/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2
by Felix Held (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, ritul guru, Martin Roth, Felix Held. Hello build bot (Jenkins), Jason Glenesk, Matt DeVillier, Fred Reitberger, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72737 to look at the new patch set (#5). Change subject: soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 ...................................................................... soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2 Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d --- M src/mainboard/amd/birman/devicetree_phoenix.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/soc/amd/phoenix/chipset.cb 3 files changed, 28 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/72737/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/72737 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Gerrit-Change-Number: 72737 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by build bot (Jenkins) (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 10: (25 comments) File src/mainboard/intel/archercity_crb/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/d9f3b8f5_53f23a77 PS10, Line 15: #define PCR_DMI_LPCIOD 0x2770 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/bdd1d9c0_2319b8b6 PS10, Line 16: #define PCR_DMI_LPCIOE 0x2774 please, no space before tabs File src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/410208e8_62546a62 PS10, Line 9: #define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/9b369916_403f3a7d PS10, Line 11: .SLOTEIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/9645c65d_25543dea PS10, Line 12: .SLOTHPCAP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/9feed2ee_c754bd8a PS10, Line 13: .SLOTHPSUP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/a5874378_134a9c9f PS10, Line 14: .SLOTPIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/e59501f7_666ee511 PS10, Line 15: .SLOTAIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/08a18dfe_c86b0ec7 PS10, Line 16: .SLOTMRLSP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/15dfdc26_60a251d8 PS10, Line 17: .SLOTPCP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/c65e099c_f5576534 PS10, Line 18: .SLOTABP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/4308cafd_5c3236cc PS10, Line 19: .SLOTIMP = slotimp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/4c77c3b3_53ae0ba7 PS10, Line 20: .SLOTSPLS = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/a31d636a_b8f18a66 PS10, Line 21: .SLOTSPLV = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/38254129_3efc5dfd PS10, Line 22: .SLOTPSP = slotpsp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/50b39419_4e9865e1 PS10, Line 23: .VppEnabled = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/35d56727_75f4b562 PS10, Line 24: .VppPort = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/70d9db53_6c554677 PS10, Line 25: .VppAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/d785caba_638b7963 PS10, Line 26: .MuxAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/83e3b435_a5fffc3e PS10, Line 27: .ChannelID = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/aa245211_11ae739c PS10, Line 28: .PciePortEnable = 1, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/a2ca1cfc_53e028af PS10, Line 29: .PEXPHIDE = pexphide, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/b27abc99_e31c5462 PS10, Line 30: .HidePEXPMenu = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/edb6867a_58c4fda5 PS10, Line 31: .PciePortOwnership = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169840): https://review.coreboot.org/c/coreboot/+/71968/comment/fa175152_cc96ad3f PS10, Line 32: .RetimerConnectCount = 0, \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 19:43:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Jonathan Zhang (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. Jonathan Zhang has uploaded a new patch set (#10) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... mb/intel: add ArcherCity CRB support Intel ArcherCity CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes EmmitsBurg PCH. Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 898 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 10 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by build bot (Jenkins) (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Johnny Lin, Paul Menzel, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 9: (25 comments) File src/mainboard/intel/archercity_crb/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/ac0eef5c_71b1684d PS9, Line 15: #define PCR_DMI_LPCIOD 0x2770 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/e079b7c4_7dc9d382 PS9, Line 16: #define PCR_DMI_LPCIOE 0x2774 please, no space before tabs File src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/29284efe_d6d5168b PS9, Line 9: #define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/412ed611_d6017538 PS9, Line 11: .SLOTEIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/a40218b1_0dde649d PS9, Line 12: .SLOTHPCAP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/a589b150_ad878bdb PS9, Line 13: .SLOTHPSUP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/0e8d4591_9b6ff066 PS9, Line 14: .SLOTPIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/87abb4ab_c6a8e9cf PS9, Line 15: .SLOTAIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/6386f8a4_a95aabb4 PS9, Line 16: .SLOTMRLSP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/8a211fc5_a654693d PS9, Line 17: .SLOTPCP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/869573ea_26d93f9a PS9, Line 18: .SLOTABP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/a1800883_f3447739 PS9, Line 19: .SLOTIMP = slotimp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/86552e31_8e740d35 PS9, Line 20: .SLOTSPLS = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/95369ff7_8ce92247 PS9, Line 21: .SLOTSPLV = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/145e02aa_b38e1392 PS9, Line 22: .SLOTPSP = slotpsp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/153c04de_5ad77929 PS9, Line 23: .VppEnabled = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/74d33a36_addd7df5 PS9, Line 24: .VppPort = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/2454d325_5acd75d7 PS9, Line 25: .VppAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/f9a3eff9_f54e6fd8 PS9, Line 26: .MuxAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/93695fef_a357b1cb PS9, Line 27: .ChannelID = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/2e7c97ec_46208168 PS9, Line 28: .PciePortEnable = 1, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/418a6f66_30605ae3 PS9, Line 29: .PEXPHIDE = pexphide, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/1e291c7d_6fb8917f PS9, Line 30: .HidePEXPMenu = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/90d54bd8_227d83a1 PS9, Line 31: .PciePortOwnership = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169839): https://review.coreboot.org/c/coreboot/+/71968/comment/4aa454c0_785d59df PS9, Line 32: .RetimerConnectCount = 0, \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 9 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 19:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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