coreboot-gerrit February 2023

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[S] Change in coreboot[master]: mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI mask
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72455 ) Change subject: mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI mask ...................................................................... mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI mask Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Tim Van Patten <timvp(a)google.com> --- M src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h 1 file changed, 25 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Raul Rangel: Looks good to me, approved Tim Van Patten: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h index 0be43a4..973e613 100644 --- a/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/google/skyrim/variants/baseboard/include/baseboard/ec.h @@ -22,7 +22,8 @@ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) \ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) \ | EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) \ - | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX) \ + | EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) #define MAINBOARD_EC_SMI_EVENTS (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) -- To view, visit https://review.coreboot.org/c/coreboot/+/72455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Gerrit-Change-Number: 72455 Gerrit-PatchSet: 2 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: amdfwtool: Add entry RIB whose subprog equals 1
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72507 ) Change subject: amdfwtool: Add entry RIB whose subprog equals 1 ...................................................................... amdfwtool: Add entry RIB whose subprog equals 1 For the PHX, it uses subprog 0. For the PHX2, it uses subprog 1. Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72507 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/data_parse.c 2 files changed, 22 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 2937264..f4fd6ee 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -329,7 +329,8 @@ { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_RIB, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_RIB, .subprog = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index 8a336d9..8c22dc5 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -411,9 +411,12 @@ } else if (strcmp(fw_name, "PSP_MPIOFW_FILE") == 0) { fw_type = AMD_FW_MPIO; subprog = 0; - } else if (strcmp(fw_name, "PSP_RIB_FILE") == 0) { + } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB0") == 0) { fw_type = AMD_RIB; subprog = 0; + } else if (strcmp(fw_name, "PSP_RIB_FILE_SUB1") == 0) { + fw_type = AMD_RIB; + subprog = 1; } else if (strcmp(fw_name, "FEATURE_TABLE_FILE") == 0) { fw_type = AMD_FW_FCFG_TABLE; subprog = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/72507 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib013f264fc9940ad95e559fe19bba72c06a19625 Gerrit-Change-Number: 72507 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Enable CNVi BT Core and Wifi
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72695 ) Change subject: mb/intel/mtlrvp: Enable CNVi BT Core and Wifi ...................................................................... mb/intel/mtlrvp: Enable CNVi BT Core and Wifi This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics. 1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1 Signed-off-by: Harsha B R <harsha.b.r(a)intel.com> Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb 1 file changed, 42 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8cdbeea..15cdee1 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -36,6 +36,9 @@ register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" + # Enable CNVi BT + register "cnvi_bt_core" = "true" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -63,6 +66,15 @@ }" end # PCIE11 SSD Gen4 device ref xhci on end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on end device ref i2c1 on end device ref i2c2 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/72695 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Gerrit-Change-Number: 72695 Gerrit-PatchSet: 4 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Harsha B R, Ravishankar Sarawadi, Sridhar Siricilla. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72742 ) Change subject: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: Interesting, since no one use it why it prevent the G3? Or real HW is connected to WLAN? -- To view, visit https://review.coreboot.org/c/coreboot/+/72742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 Gerrit-Change-Number: 72742 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:52:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/intel/tgl: Move ME FSR structures to pertinent header
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Eric Lai has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72416 ) Change subject: soc/intel/tgl: Move ME FSR structures to pertinent header ...................................................................... soc/intel/tgl: Move ME FSR structures to pertinent header This patch moves ME host firmware status register structures to ME header file. It also marks unused structure fields to reserved. The idea here is to decouple ME specification defined structures from the source file `.c` and keep those into header files so that in future those spec defined header can move into common code. The current and future SoC platform will be able to select the correct ME spec header based on the applicable config. It might be also beneficial if two different SoC platforms would like to use the same ME specification and not necessarily share the same SoC directory. BUG=b:260309647 Test=Able to build and boot. Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72416 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/soc/intel/tigerlake/include/soc/me.h M src/soc/intel/tigerlake/me.c 2 files changed, 91 insertions(+), 110 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/tigerlake/include/soc/me.h b/src/soc/intel/tigerlake/include/soc/me.h index ed25444..fd54de0 100644 --- a/src/soc/intel/tigerlake/include/soc/me.h +++ b/src/soc/intel/tigerlake/include/soc/me.h @@ -5,39 +5,73 @@ /* ME Host Firmware Status register 1 */ union me_hfsts1 { - u32 data; + uint32_t data; struct { - u32 working_state: 4; - u32 mfg_mode: 1; - u32 fpt_bad: 1; - u32 operation_state: 3; - u32 fw_init_complete: 1; - u32 ft_bup_ld_flr: 1; - u32 update_in_progress: 1; - u32 error_code: 4; - u32 operation_mode: 4; - u32 reset_count: 4; - u32 boot_options_present: 1; - u32 invoke_enhance_dbg_mode: 1; - u32 bist_test_state: 1; - u32 bist_reset_request: 1; - u32 current_power_source: 2; - u32 reserved: 1; - u32 d0i3_support_valid: 1; + uint32_t working_state : 4; + uint32_t mfg_mode : 1; + uint32_t fpt_bad : 1; + uint32_t operation_state : 3; + uint32_t fw_init_complete : 1; + uint32_t ft_bup_ld_flr : 1; + uint32_t update_in_progress : 1; + uint32_t error_code : 4; + uint32_t operation_mode : 4; + uint32_t reserved_0 : 4; + uint32_t boot_options_present : 1; + uint32_t invoke_enhance_dbg_mode: 1; + uint32_t reserved_1 : 5; + uint32_t d0i3_support_valid : 1; + } __packed fields; +}; + +/* Host Firmware Status Register 2 */ +union me_hfsts2 { + uint32_t data; + struct { + uint32_t reserved_0 : 4; + uint32_t cpu_replaced : 1; + uint32_t reserved_1 : 3; + uint32_t cpu_replaced_valid : 1; + uint32_t low_power_state : 1; + uint32_t reserved_2 : 22; } __packed fields; }; /* ME Host Firmware Status Register 3 */ union me_hfsts3 { - u32 data; + uint32_t data; struct { - u32 reserved_0: 4; - u32 fw_sku: 3; - u32 reserved_7: 2; - u32 reserved_9: 2; - u32 resered_11: 3; - u32 resered_14: 16; - u32 reserved_30: 2; + uint32_t reserved_0 : 4; + uint32_t fw_sku : 3; + uint32_t reserved_1 : 25; + } __packed fields; +}; + +/* Host Firmware Status Register 4 */ +union me_hfsts4 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* Host Firmware Status Register 5 */ +union me_hfsts5 { + uint32_t data; + struct { + uint32_t reserved_0; + } __packed fields; +}; + +/* Host Firmware Status Register 6 */ +union me_hfsts6 { + uint32_t data; + struct { + uint32_t reserved_0 : 1; + uint32_t cpu_debug_disable : 1; + uint32_t reserved_1 : 28; + uint32_t fpf_soc_lock : 1; + uint32_t txt_support : 1; } __packed fields; }; #endif /* _TIGERLAKE_ME_H_ */ diff --git a/src/soc/intel/tigerlake/me.c b/src/soc/intel/tigerlake/me.c index 560464f..e953844 100644 --- a/src/soc/intel/tigerlake/me.c +++ b/src/soc/intel/tigerlake/me.c @@ -6,90 +6,6 @@ #include <soc/me.h> #include <types.h> -/* Host Firmware Status Register 2 */ -union me_hfsts2 { - uint32_t data; - struct { - uint32_t nftp_load_failure : 1; - uint32_t icc_prog_status : 2; - uint32_t invoke_mebx : 1; - uint32_t cpu_replaced : 1; - uint32_t rsvd0 : 1; - uint32_t mfs_failure : 1; - uint32_t warm_reset_rqst : 1; - uint32_t cpu_replaced_valid : 1; - uint32_t low_power_state : 1; - uint32_t me_power_gate : 1; - uint32_t ipu_needed : 1; - uint32_t forced_safe_boot : 1; - uint32_t rsvd1 : 2; - uint32_t listener_change : 1; - uint32_t status_data : 8; - uint32_t current_pmevent : 4; - uint32_t phase : 4; - } __packed fields; -}; - -/* Host Firmware Status Register 4 */ -union me_hfsts4 { - uint32_t data; - struct { - uint32_t rsvd0 : 9; - uint32_t enforcement_flow : 1; - uint32_t sx_resume_type : 1; - uint32_t rsvd1 : 1; - uint32_t tpms_disconnected : 1; - uint32_t rvsd2 : 1; - uint32_t fwsts_valid : 1; - uint32_t boot_guard_self_test : 1; - uint32_t rsvd3 : 16; - } __packed fields; -}; - -/* Host Firmware Status Register 5 */ -union me_hfsts5 { - uint32_t data; - struct { - uint32_t acm_active : 1; - uint32_t valid : 1; - uint32_t result_code_source : 1; - uint32_t error_status_code : 5; - uint32_t acm_done_sts : 1; - uint32_t timeout_count : 7; - uint32_t scrtm_indicator : 1; - uint32_t inc_boot_guard_acm : 4; - uint32_t inc_key_manifest : 4; - uint32_t inc_boot_policy : 4; - uint32_t rsvd0 : 2; - uint32_t start_enforcement : 1; - } __packed fields; -}; - -/* Host Firmware Status Register 6 */ -union me_hfsts6 { - uint32_t data; - struct { - uint32_t force_boot_guard_acm : 1; - uint32_t cpu_debug_disable : 1; - uint32_t bsp_init_disable : 1; - uint32_t protect_bios_env : 1; - uint32_t rsvd0 : 2; - uint32_t error_enforce_policy : 2; - uint32_t measured_boot : 1; - uint32_t verified_boot : 1; - uint32_t boot_guard_acmsvn : 4; - uint32_t kmsvn : 4; - uint32_t bpmsvn : 4; - uint32_t key_manifest_id : 4; - uint32_t boot_policy_status : 1; - uint32_t error : 1; - uint32_t boot_guard_disable : 1; - uint32_t fpf_disable : 1; - uint32_t fpf_soc_lock : 1; - uint32_t txt_support : 1; - } __packed fields; -}; - static void dump_me_status(void *unused) { union me_hfsts1 hfsts1; -- To view, visit https://review.coreboot.org/c/coreboot/+/72416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Gerrit-Change-Number: 72416 Gerrit-PatchSet: 4 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/intel/tgl: Move ME FSR structures to pertinent header
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Tarun Tuli, Dinesh Gehlot, Rizwan Qureshi, Sridhar Siricilla. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72416 ) Change subject: soc/intel/tgl: Move ME FSR structures to pertinent header ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib96fcb86fd2c3fe16f23c8f038f4930a832a5b01 Gerrit-Change-Number: 72416 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:49:19 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/rtd3: Fix S3 on TGL and ADL
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Sean Rhodes, Matt DeVillier, Angel Pons. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72765 ) Change subject: soc/intel/rtd3: Fix S3 on TGL and ADL ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72765/comment/94704251_e0f2cca5 PS1, Line 9: S3 does not support D3Cold, > where's this documented? I'm not seeing anything in Linux/Windows power state docs to indicate D3col […] IMHO the power rail of S3 on their board can't support it. D3cold more like the HW support. -- To view, visit https://review.coreboot.org/c/coreboot/+/72765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Gerrit-Change-Number: 72765 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:34:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/rtd3: Fix S3 on TGL and ADL
by Matt DeVillier (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Sean Rhodes, Angel Pons. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72765 ) Change subject: soc/intel/rtd3: Fix S3 on TGL and ADL ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/72765/comment/1a4fae19_68d6cbcd PS1, Line 9: S3 does not support D3Cold, where's this documented? I'm not seeing anything in Linux/Windows power state docs to indicate D3cold requires S0ix -- To view, visit https://review.coreboot.org/c/coreboot/+/72765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Gerrit-Change-Number: 72765 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:17:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/rtd3: Fix S3 on TGL and ADL
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Sean Rhodes, Matt DeVillier, Angel Pons. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72765 ) Change subject: soc/intel/rtd3: Fix S3 on TGL and ADL ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72765 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a4b89132b594ad568a5851137575f921f8e2a2e Gerrit-Change-Number: 72765 Gerrit-PatchSet: 1 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:15:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Update ASPM settings for the NVMe device
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Martin L Roth, Jason Nien, Jason Glenesk, Martin Roth, Fred Reitberger, Felix Held. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72391 ) Change subject: mb/google/skyrim: Update ASPM settings for the NVMe device ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Gerrit-Change-Number: 72391 Gerrit-PatchSet: 6 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:10:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit February 2023