coreboot-gerrit February 2023

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[S] Change in coreboot[master]: Revert "UPSTREAM: mb/google/rex: Enable SaGv"
by Eric Lai (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Vikrant Jadeja, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar. Eric Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72774 ) Change subject: Revert "UPSTREAM: mb/google/rex: Enable SaGv" ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Gerrit-Change-Number: 72774 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 00:04:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by build bot (Jenkins) (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Chu. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... Patch Set 11: (25 comments) File src/mainboard/intel/archercity_crb/bootblock.c: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/9a130d40_cdb3ed28 PS11, Line 15: #define PCR_DMI_LPCIOD 0x2770 please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/e0e01c1d_53603fd6 PS11, Line 16: #define PCR_DMI_LPCIOE 0x2774 please, no space before tabs File src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/d300671b_399b3195 PS11, Line 9: #define CFG_UPD_PCIE_PORT(pexphide, slotimp, slotpsp) \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/4bb4e680_67e8e2d7 PS11, Line 11: .SLOTEIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/c7f993f2_8a77b036 PS11, Line 12: .SLOTHPCAP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/22a8b88b_a92f536a PS11, Line 13: .SLOTHPSUP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/3da2a9e6_6e11fab5 PS11, Line 14: .SLOTPIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/5719ed87_143f4595 PS11, Line 15: .SLOTAIP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/6c784a0b_75801995 PS11, Line 16: .SLOTMRLSP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/c51df5c4_173682a6 PS11, Line 17: .SLOTPCP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/47b068ed_b3588c08 PS11, Line 18: .SLOTABP = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/ef1539c6_0b125de8 PS11, Line 19: .SLOTIMP = slotimp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/8201c813_cc3ce28c PS11, Line 20: .SLOTSPLS = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/88d2355c_09541494 PS11, Line 21: .SLOTSPLV = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/e1f1b786_6f62c581 PS11, Line 22: .SLOTPSP = slotpsp, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/93e8d139_4aeceaf0 PS11, Line 23: .VppEnabled = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/5144084c_02009c16 PS11, Line 24: .VppPort = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/90496de9_1568b335 PS11, Line 25: .VppAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/fe263195_6a982f35 PS11, Line 26: .MuxAddress = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/6836bf9e_2b2d04a8 PS11, Line 27: .ChannelID = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/f70756d3_5fceed9f PS11, Line 28: .PciePortEnable = 1, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/8ea0580d_f2dc4609 PS11, Line 29: .PEXPHIDE = pexphide, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/c19e243d_cd338005 PS11, Line 30: .HidePEXPMenu = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/67ad096b_a7e722df PS11, Line 31: .PciePortOwnership = 0, \ please, no space before tabs Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169854): https://review.coreboot.org/c/coreboot/+/71968/comment/65c227ec_c4fd0a42 PS11, Line 32: .RetimerConnectCount = 0, \ please, no space before tabs -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 23:11:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[master]: mb/intel: add ArcherCity CRB support
by Jonathan Zhang (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Patrick Rudolph, Simon Chou, Jonathan Zhang, Johnny Lin, Paul Menzel, Tim Chu. Jonathan Zhang has uploaded a new patch set (#11) to the change originally created by Simon Chou. ( https://review.coreboot.org/c/coreboot/+/71968 ) Change subject: mb/intel: add ArcherCity CRB support ...................................................................... mb/intel: add ArcherCity CRB support Intel ArcherCity CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes EmmitsBurg PCH. Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang(a)meta.com> Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- A src/mainboard/intel/archercity_crb/Kconfig A src/mainboard/intel/archercity_crb/Kconfig.name A src/mainboard/intel/archercity_crb/Makefile.inc A src/mainboard/intel/archercity_crb/acpi/platform.asl A src/mainboard/intel/archercity_crb/board.fmd A src/mainboard/intel/archercity_crb/board_info.txt A src/mainboard/intel/archercity_crb/bootblock.c A src/mainboard/intel/archercity_crb/devicetree.cb A src/mainboard/intel/archercity_crb/dsdt.asl A src/mainboard/intel/archercity_crb/include/mainboard_ras.h A src/mainboard/intel/archercity_crb/include/sprsp_ac_iio.h A src/mainboard/intel/archercity_crb/ramstage.c A src/mainboard/intel/archercity_crb/romstage.c 13 files changed, 902 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/71968/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/71968 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Gerrit-Change-Number: 71968 Gerrit-PatchSet: 11 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: Revert "UPSTREAM: mb/google/rex: Enable SaGv"
by Jamie Ryu (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Vikrant Jadeja, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar. Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72774 ) Change subject: Revert "UPSTREAM: mb/google/rex: Enable SaGv" ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/72774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Gerrit-Change-Number: 72774 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Fri, 03 Feb 2023 23:02:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: update USB ports
by Matt DeVillier (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72773 ) Change subject: soc/amd/phoenix/chipset.cb: update USB ports ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72773 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Gerrit-Change-Number: 72773 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 22:40:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: soc/amd/phoenix/chipset.cb: add remaining PCI devices
by Matt DeVillier (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Jason Glenesk, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72771 ) Change subject: soc/amd/phoenix/chipset.cb: add remaining PCI devices ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Gerrit-Change-Number: 72771 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 22:39:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Update ASPM settings for the NVMe device
by Matt DeVillier (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Martin L Roth, Jason Nien, Jason Glenesk, Martin Roth, Fred Reitberger, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72391 ) Change subject: mb/google/skyrim: Update ASPM settings for the NVMe device ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72391 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Gerrit-Change-Number: 72391 Gerrit-PatchSet: 6 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 03 Feb 2023 22:38:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/google/skyrim: Disable unused SPI ROM types
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72769 ) Change subject: mb/google/skyrim: Disable unused SPI ROM types ...................................................................... mb/google/skyrim: Disable unused SPI ROM types By default, coreboot includes support for all the different types of SPI ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k. BUG=b:267735039 TEST=Build & Boot ROM Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/72769/1 diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index d945474..aee408e 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -173,4 +173,14 @@ just the small SRAM buffer to a much larger area reserved in main memory. +# Exclude support for SPI ROM types that won't be used on Skyrim platforms +config SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS + default y + +config SPI_FLASH_GIGADEVICE + default y + +config SPI_FLASH_WINBOND + default y + endif # BOARD_GOOGLE_BASEBOARD_SKYRIM -- To view, visit https://review.coreboot.org/c/coreboot/+/72769 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf Gerrit-Change-Number: 72769 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[master]: Revert "UPSTREAM: mb/google/rex: Enable SaGv"
by Subrata Banik (Code Review) 03 Feb '23

03 Feb '23

Attention is currently required from: Vikrant Jadeja, Subrata Banik, Kapil Porwal, Balaji Manigandan, Ronak Kanabar. Hello Vikrant Jadeja, Tarun Tuli, Kapil Porwal, Balaji Manigandan, Ronak Kanabar, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72774 to look at the new patch set (#2). Change subject: Revert "UPSTREAM: mb/google/rex: Enable SaGv" ...................................................................... Revert "UPSTREAM: mb/google/rex: Enable SaGv" Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a --- M src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb 1 file changed, 18 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/72774/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72774 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Gerrit-Change-Number: 72774 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Vikrant Jadeja Gerrit-Attention: Vikrant Jadeja Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[master]: drivers/spi: Remove SPI_FRAM_RAMTRON from makefile
by Martin L Roth (Code Review) 03 Feb '23

03 Feb '23

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72767 ) Change subject: drivers/spi: Remove SPI_FRAM_RAMTRON from makefile ...................................................................... drivers/spi: Remove SPI_FRAM_RAMTRON from makefile This is unused - other references were removed long ago. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ia7a65f54c736db20a5440795fdfaa8be31ef971f --- M src/drivers/spi/Makefile.inc 1 file changed, 12 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/72767/1 diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 56ee44b..e166984 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -28,7 +28,6 @@ $(1)-$(CONFIG_SPI_FLASH_SST) += sst.c $(1)-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c $(1)-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c -$(1)-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c endef $(eval $(call add_spi_stage,bootblock,_EARLY)) -- To view, visit https://review.coreboot.org/c/coreboot/+/72767 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7a65f54c736db20a5440795fdfaa8be31ef971f Gerrit-Change-Number: 72767 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit February 2023