coreboot-gerrit February 2023

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[S] Change in coreboot[master]: util/amdfwtool: add comment about reused PSP firmware type 0x5f
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72713 ) Change subject: util/amdfwtool: add comment about reused PSP firmware type 0x5f ...................................................................... util/amdfwtool: add comment about reused PSP firmware type 0x5f On family 15h and 16h processors with PSP, the PSP firmware type 0x5f corresponds to AMD_FW_PSP_SMUSCS, while on family 17h and 19h this corresponds to AMD_FW_TPMLITE. Add comments to those two enum values to clarify this. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72713 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Bao Zheng <fishbaozi(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M util/amdfwtool/amdfwtool.h 1 file changed, 21 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Bao Zheng: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, approved diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index d3d6866..f30dce6 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -68,8 +68,8 @@ AMD_FW_MSMU = 0x5a, AMD_FW_SPIROM_CFG = 0x5c, AMD_FW_MPIO = 0x5d, - AMD_FW_TPMLITE = 0x5f, - AMD_FW_PSP_SMUSCS = 0x5f, + AMD_FW_TPMLITE = 0x5f, /* family 17h & 19h */ + AMD_FW_PSP_SMUSCS = 0x5f, /* family 15h & 16h */ AMD_FW_DMCUB = 0x71, AMD_FW_PSP_BOOTLOADER_AB = 0x73, AMD_RIB = 0x76, -- To view, visit https://review.coreboot.org/c/coreboot/+/72713 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia5c125ec6a0eb548f58a457f9040278391d2101c Gerrit-Change-Number: 72713 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: test
by Morris Hsu (Code Review) 04 Feb '23

04 Feb '23

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72776 ) Change subject: test ...................................................................... test Change-Id: If5abbe07d3a231b88c48049c553dfab5e2b8e77e --- M 3rdparty/amd_blobs M 3rdparty/blobs M 3rdparty/intel-microcode M 3rdparty/libgfxinit M 3rdparty/libhwbase 5 files changed, 14 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/72776/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index acf7395..5cc1532 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit acf7395452de0c17743068e0bb27d9f53eff9aa0 +Subproject commit 5cc15323c0a35e35df2bdddfe2699d5940ff7dde diff --git a/3rdparty/blobs b/3rdparty/blobs index 01ba156..e82e4b6 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 01ba15667f34793580f5edd0de1e26b7a542cac6 +Subproject commit e82e4b618beaae56f56da9311a8e4f61b6a046f8 diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 262f0c9..ee319ae 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 262f0c97f2fbc3839a59523cc6c6bcf500e2850b +Subproject commit ee319ae7bc59e88b60142f40a9ec1b46656de4db diff --git a/3rdparty/libgfxinit b/3rdparty/libgfxinit index 066e52e..31042e8 160000 --- a/3rdparty/libgfxinit +++ b/3rdparty/libgfxinit @@ -1 +1 @@ -Subproject commit 066e52eeaa329d782ccee96265a6a351fc395bf1 +Subproject commit 31042e8cb3dd2e1fbc56cd1e07b41c00c37e33c6 diff --git a/3rdparty/libhwbase b/3rdparty/libhwbase index 8be5a82..5ec3927 160000 --- a/3rdparty/libhwbase +++ b/3rdparty/libhwbase @@ -1 +1 @@ -Subproject commit 8be5a82b85ceb3ee8a1c4fbf36c75a4bfbda8900 +Subproject commit 5ec392755dad0644817a72d1d9a379171012b89d -- To view, visit https://review.coreboot.org/c/coreboot/+/72776 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If5abbe07d3a231b88c48049c553dfab5e2b8e77e Gerrit-Change-Number: 72776 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[master]: mb/google/brya/var/constitution: Add SOLDERDOWN support
by Morris Hsu (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Tarun Tuli, Morris Hsu. Hello build bot (Jenkins), Tarun Tuli, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/72775 to look at the new patch set (#2). Change subject: mb/google/brya/var/constitution: Add SOLDERDOWN support ...................................................................... mb/google/brya/var/constitution: Add SOLDERDOWN support Constitution will use SOLDERDOWN. Add memory.c to override baseboard. BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/constitution/Makefile.inc A src/mainboard/google/brya/variants/constitution/memory.c 4 files changed, 126 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/72775/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Gerrit-Change-Number: 72775 Gerrit-PatchSet: 2 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Attention: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: mb/google/brya/var/constitution: Add SOLDERDOWN support
by Morris Hsu (Code Review) 04 Feb '23

04 Feb '23

Morris Hsu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/72775 ) Change subject: mb/google/brya/var/constitution: Add SOLDERDOWN support ...................................................................... mb/google/brya/var/constitution: Add SOLDERDOWN support Constitution will use SOLDERDOWN. Add memory.c to override baseboard. BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/constitution/Makefile.inc A src/mainboard/google/brya/variants/constitution/memory.c 4 files changed, 122 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/72775/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index c947ce8..1e63406 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -53,7 +53,7 @@ select BOARD_ROMSIZE_KB_32768 select ENABLE_TCSS_DISPLAY_DETECTION if RUN_FSP_GOP select HAVE_SLP_S0_GATE - select MEMORY_SODIMM + select MEMORY_SODIMM if !BOARD_GOOGLE_CONSTITUTION select RT8168_GEN_ACPI_POWER_RESOURCE select RT8168_GET_MAC_FROM_VPD select RT8168_SET_LED_MODE diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name index 5c393b7..452f57b 100644 --- a/src/mainboard/google/brya/Kconfig.name +++ b/src/mainboard/google/brya/Kconfig.name @@ -335,3 +335,4 @@ config BOARD_GOOGLE_CONSTITUTION bool "-> Constitution" select BOARD_GOOGLE_BASEBOARD_BRASK + select MEMORY_SOLDERDOWN diff --git a/src/mainboard/google/brya/variants/constitution/Makefile.inc b/src/mainboard/google/brya/variants/constitution/Makefile.inc new file mode 100644 index 0000000..c44e4f0 --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/Makefile.inc @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +romstage-y += memory.c diff --git a/src/mainboard/google/brya/variants/constitution/memory.c b/src/mainboard/google/brya/variants/constitution/memory.c new file mode 100644 index 0000000..436353c --- /dev/null +++ b/src/mainboard/google/brya/variants/constitution/memory.c @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP4X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + + /* Baseboard Rcomp target values */ + .targets = {40, 30, 30, 30, 30}, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 0, 2, 1, 4, 6, 5, 7, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, },//check DDR_A_DQ0,DDR_A_DQ1 + }, + .ddr1 = { + .dq0 = { 13, 14, 11, 12, 10, 8, 15, 9, }, + .dq1 = { 5, 2, 4, 3, 1, 6, 0, 7, },//check DDR_A_DQ2,DDR_A_DQ3 + }, + .ddr2 = { + .dq0 = { 2, 3, 1, 0, 7, 6, 5, 4, }, + .dq1 = { 12, 13, 14, 15, 8, 9, 10, 11, },//check DDR_A_DQ4,DDR_A_DQ5 + }, + .ddr3 = { + .dq0 = { 13, 14, 12, 15, 11, 9, 8, 10, }, + .dq1 = { 5, 2, 1, 4, 7, 0, 3, 6, },//check DDR_A_DQ6,DDR_A_DQ7 + }, + .ddr4 = { + .dq0 = { 11, 10, 8, 9, 14, 15, 13, 12, }, + .dq1 = { 3, 0, 2, 1, 5, 4, 6, 7, },//check DDR_B_DQ0,DDR_B_DQ1 + }, + .ddr5 = { + .dq0 = { 11, 15, 13, 12, 10, 9, 14, 8, }, + .dq1 = { 3, 0, 2, 1, 6, 7, 5, 4, },//check DDR_B_DQ2,DDR_B_DQ3 + }, + .ddr6 = { + .dq0 = { 11, 13, 10, 12, 15, 9, 14, 8, }, + .dq1 = { 4, 3, 5, 2, 7, 0, 1, 6, },//check DDR_B_DQ4,DDR_B_DQ5 + }, + .ddr7 = { + .dq0 = { 12, 13, 15, 14, 11, 9, 10, 8, }, + .dq1 = { 4, 5, 1, 2, 6, 3, 0, 7, },//check DDR_B_DQ6,DDR_B_DQ7 + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 },//check + .ddr1 = { .dqs0 = 1, .dqs1 = 0 },//check + .ddr2 = { .dqs0 = 0, .dqs1 = 1 },//check + .ddr3 = { .dqs0 = 1, .dqs1 = 0 },//check + .ddr4 = { .dqs0 = 1, .dqs1 = 0 },//check + .ddr5 = { .dqs0 = 1, .dqs1 = 0 },//check + .ddr6 = { .dqs0 = 1, .dqs1 = 0 },//check + .ddr7 = { .dqs0 = 1, .dqs1 = 0 },//check + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int __weak variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_F16 + * GPIO_MEM_CONFIG_1 GPP_F12 + * GPIO_MEM_CONFIG_2 GPP_F13 + * GPIO_MEM_CONFIG_3 GPP_F15 + */ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F12, + GPP_F13, + GPP_F15, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* GPIO_MEM_CH_SEL GPP_F11 */ + return gpio_get(GPP_F11); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Gerrit-Change-Number: 72775 Gerrit-PatchSet: 1 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[XL] Change in coreboot[master]: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support
by Jian-Ming Wang (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Patrick Rudolph, Jonathan Zhang, Simon Chou, TimLiu-SMCI, Johnny Lin, Christian Walter, Angel Pons, Arthur Heymans, Tim Chu, Shelly Chang. Jian-Ming Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71958 ) Change subject: soc/intel/xeon_sp: Rename nb_acpi.c and add SPR-SP support ...................................................................... Patch Set 8: (1 comment) File src/soc/intel/xeon_sp/uncore_acpi.c: https://review.coreboot.org/c/coreboot/+/71958/comment/e5aac4d3_ed78fe6e PS2, Line 147: pds. > pds is short for Proximity Domains. […] The pds is a global variable defined in numa.h which is not included in this patch. Details could be find from the header. I can't find specific rule for global variable from coding convention of coreboot. Possible we could use g_pds, G_pds, or even g_proximity_domains as improvement for readability. Since the improvement can impact multiple files across different changes and many code reviews are on going, suggest to do the improvement in near future. -- To view, visit https://review.coreboot.org/c/coreboot/+/71958 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf Gerrit-Change-Number: 71958 Gerrit-PatchSet: 8 Gerrit-Owner: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jian-Ming Wang <jianmingW(a)supermicro.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Simon Chou <simonchou(a)supermicro.com.tw> Gerrit-Attention: TimLiu-SMCI <timliu(a)supermicro.com.tw> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 02:32:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jonathan Zhang <jonzhang(a)fb.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[master]: mb/*: Replace SNB PCI devices with references from chipset.cb
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/69502 ) Change subject: mb/*: Replace SNB PCI devices with references from chipset.cb ...................................................................... mb/*: Replace SNB PCI devices with references from chipset.cb Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/apple/macbookair4_2/devicetree.cb M src/mainboard/asrock/b75pro3-m/devicetree.cb M src/mainboard/asrock/h77pro4-m/devicetree.cb M src/mainboard/asus/h61-series/devicetree.cb M src/mainboard/asus/maximus_iv_gene-z/devicetree.cb M src/mainboard/asus/p8x7x-series/devicetree.cb M src/mainboard/biostar/th61-itx/devicetree.cb M src/mainboard/compulab/intense_pc/devicetree.cb M src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb M src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb M src/mainboard/gigabyte/ga-h61m-series/devicetree.cb M src/mainboard/google/butterfly/devicetree.cb M src/mainboard/google/link/devicetree.cb M src/mainboard/google/parrot/devicetree.cb M src/mainboard/google/stout/devicetree.cb M src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb M src/mainboard/hp/snb_ivb_laptops/devicetree.cb M src/mainboard/hp/z220_series/devicetree.cb M src/mainboard/intel/dcp847ske/devicetree.cb M src/mainboard/intel/emeraldlake2/devicetree.cb M src/mainboard/kontron/ktqm77/devicetree.cb M src/mainboard/lenovo/l520/devicetree.cb M src/mainboard/lenovo/s230u/devicetree.cb M src/mainboard/lenovo/t420/devicetree.cb M src/mainboard/lenovo/t420s/devicetree.cb M src/mainboard/lenovo/t430/devicetree.cb M src/mainboard/lenovo/t430s/devicetree.cb M src/mainboard/lenovo/t520/devicetree.cb M src/mainboard/lenovo/t530/devicetree.cb M src/mainboard/lenovo/x131e/devicetree.cb M src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb M src/mainboard/lenovo/x220/devicetree.cb M src/mainboard/lenovo/x230/devicetree.cb M src/mainboard/msi/ms7707/devicetree.cb M src/mainboard/roda/rv11/variants/rv11/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/mainboard/samsung/lumpy/devicetree.cb M src/mainboard/samsung/stumpy/devicetree.cb M src/mainboard/sapphire/pureplatinumh61/devicetree.cb M src/mainboard/supermicro/x9sae/devicetree.cb M src/mainboard/supermicro/x9scl/devicetree.cb M src/northbridge/intel/sandybridge/chipset.cb 42 files changed, 1,065 insertions(+), 1,016 deletions(-) Approvals: build bot (Jenkins): Verified Nico Huber: Looks good to me, but someone else must approve Elyes Haouas: Looks good to me, approved Jakub Czapiga: Looks good to me, but someone else must approve diff --git a/src/mainboard/apple/macbookair4_2/devicetree.cb b/src/mainboard/apple/macbookair4_2/devicetree.cb index df2f154..4b1b9af 100644 --- a/src/mainboard/apple/macbookair4_2/devicetree.cb +++ b/src/mainboard/apple/macbookair4_2/devicetree.cb @@ -26,67 +26,67 @@ register "pcie_port_coalesce" = "true" register "sata_interface_speed_support" = "0x3" register "sata_port_map" = "0x1" - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x8086 0x7270 end - device pci 16.1 off # Management Engine Interface 2 + device ref mei2 off # Management Engine Interface 2 end - device pci 16.2 off # Management Engine IDE-R + device ref me_ide_r off # Management Engine IDE-R end - device pci 16.3 off # Management Engine KT + device ref me_kt off # Management Engine KT end - device pci 19.0 off # Intel Gigabit Ethernet + device ref gbe off # Intel Gigabit Ethernet end - device pci 1a.0 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c + device ref ehci2 on # USB2 EHCI #2 Unsupported PCI device 8086:1c2c subsystemid 0x8086 0x7270 end - device pci 1b.0 on # High Definition Audio Audio controller + device ref hda on # High Definition Audio Audio controller subsystemid 0x8086 0x7270 end - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on # PCIe Port #1 subsystemid 0x8086 0x7270 end - device pci 1c.1 on # PCIe Port #2 + device ref pcie_rp2 on # PCIe Port #2 subsystemid 0x8086 0x7270 end - device pci 1c.2 off # PCIe Port #3 + device ref pcie_rp3 off # PCIe Port #3 end - device pci 1c.3 off # PCIe Port #4 + device ref pcie_rp4 off # PCIe Port #4 end - device pci 1c.4 off # PCIe Port #5 + device ref pcie_rp5 off # PCIe Port #5 end - device pci 1c.5 off # PCIe Port #6 + device ref pcie_rp6 off # PCIe Port #6 end - device pci 1c.6 off # PCIe Port #7 + device ref pcie_rp7 off # PCIe Port #7 end - device pci 1c.7 off # PCIe Port #8 + device ref pcie_rp8 off # PCIe Port #8 end - device pci 1d.0 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 + device ref ehci1 on # USB2 EHCI #1 Unsupported PCI device 8086:1c27 subsystemid 0x8086 0x7270 end - device pci 1e.0 off # PCI bridge + device ref pci_bridge off # PCI bridge end - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref lpc on # LPC bridge PCI-LPC bridge subsystemid 0x8086 0x7270 end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x8086 0x7270 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x8086 0x7270 end - device pci 1f.5 off # SATA Controller 2 + device ref sata2 off # SATA Controller 2 end - device pci 1f.6 off # Thermal + device ref thermal off # Thermal end end - device pci 00.0 on # Host bridge Host bridge + device ref host_bridge on # Host bridge Host bridge subsystemid 0x106b 0x00eb end - device pci 01.0 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101 + device ref peg10 on # PCIe Bridge for discrete graphics Unsupported PCI device 8086:0101 subsystemid 0x106b 0x00eb end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x106b 0x00eb end device pci 1a.7 on diff --git a/src/mainboard/asrock/b75pro3-m/devicetree.cb b/src/mainboard/asrock/b75pro3-m/devicetree.cb index f45418f..163cdb3 100644 --- a/src/mainboard/asrock/b75pro3-m/devicetree.cb +++ b/src/mainboard/asrock/b75pro3-m/devicetree.cb @@ -15,13 +15,13 @@ register "gpu_pch_backlight" = "0x00000000" device domain 0 on - device pci 00.0 on + device ref host_bridge on subsystemid 0x1849 0x0150 end - device pci 01.0 on + device ref peg10 on subsystemid 0x1849 0x0151 end - device pci 02.0 on + device ref igd on subsystemid 0x1849 0x0152 end chip southbridge/intel/bd82x6x @@ -39,53 +39,53 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x1849 0x1e3a end - device pci 16.1 off # Management Engine Interface 2 + device ref mei2 off # Management Engine Interface 2 end - device pci 16.2 off # Management Engine IDE-R + device ref me_ide_r off # Management Engine IDE-R end - device pci 16.3 on # Management Engine KT + device ref me_kt on # Management Engine KT subsystemid 0x1849 0x1e3d end - device pci 19.0 off # Intel Gigabit Ethernet + device ref gbe off # Intel Gigabit Ethernet end - device pci 1a.0 on # USB2 EHCI #2 + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # High Definition Audio Audio controller + device ref hda on # High Definition Audio Audio controller subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on # PCIe Port #1 subsystemid 0x1849 0x1e10 end - device pci 1c.1 off # PCIe Port #2 + device ref pcie_rp2 off # PCIe Port #2 end - device pci 1c.2 off # PCIe Port #3 + device ref pcie_rp3 off # PCIe Port #3 end - device pci 1c.3 off # PCIe Port #4 + device ref pcie_rp4 off # PCIe Port #4 end - device pci 1c.4 on # PCIe Port #5, ASMedia ASM1062 SATA Controller + device ref pcie_rp5 on # PCIe Port #5, ASMedia ASM1062 SATA Controller subsystemid 0x1849 0x1e18 end - device pci 1c.5 on # PCIe Port #6, Realtek PCIe GbE Controller + device ref pcie_rp6 on # PCIe Port #6, Realtek PCIe GbE Controller subsystemid 0x1849 0x1e1a end - device pci 1c.6 off # PCIe Port #7 + device ref pcie_rp7 off # PCIe Port #7 end - device pci 1c.7 off # PCIe Port #8 + device ref pcie_rp8 off # PCIe Port #8 end - device pci 1d.0 on # USB2 EHCI #1 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1849 0x1e26 end - device pci 1e.0 on # PCI bridge + device ref pci_bridge on # PCI bridge subsystemid 0x1849 0x244e end - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge subsystemid 0x1849 0x1e49 chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -130,15 +130,15 @@ device pnp 2e.17 on end # GPIOA end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1849 0x1e22 end - device pci 1f.5 off # SATA Controller 2 + device ref sata2 off # SATA Controller 2 end - device pci 1f.6 off # Thermal + device ref thermal off # Thermal end end end diff --git a/src/mainboard/asrock/h77pro4-m/devicetree.cb b/src/mainboard/asrock/h77pro4-m/devicetree.cb index 7d94706..646b9a3 100644 --- a/src/mainboard/asrock/h77pro4-m/devicetree.cb +++ b/src/mainboard/asrock/h77pro4-m/devicetree.cb @@ -2,11 +2,11 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on # Host bridge + device ref host_bridge on # Host bridge subsystemid 0x1849 0x0100 end - device pci 01.0 on end # PEG - slot "PCIE1" - device pci 02.0 on # iGPU + device ref peg10 on end # PEG - slot "PCIE1" + device ref igd on # iGPU subsystemid 0x1849 0x0102 end chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH @@ -20,45 +20,45 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1849 0x1e31 end - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x1849 0x1e3a end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1849 0x1e2d end - device pci 1b.0 on # High Definition Audio + device ref hda on # High Definition Audio subsystemid 0x1849 0x8892 end - device pci 1c.0 on # PCIe Port #1 - slot "PCIE4", 4 lanes + device ref pcie_rp1 on # PCIe Port #1 - slot "PCIE4", 4 lanes subsystemid 0x1849 0x1e10 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 - slot "PCIE2", 1 lane + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5 - slot "PCIE2", 1 lane subsystemid 0x1849 0x1e18 end - device pci 1c.5 on # PCIe Port #6 - RTL8111E GbE + device ref pcie_rp6 on # PCIe Port #6 - RTL8111E GbE subsystemid 0x1849 0x1e1a end - device pci 1c.6 on # PCIe Port #7 - slot "PCIE3", 1 lane + device ref pcie_rp7 on # PCIe Port #7 - slot "PCIE3", 1 lane subsystemid 0x1849 0x1e16 end - device pci 1c.7 on # PCIe Port #8 - ASM1061 SATA Controller + device ref pcie_rp8 on # PCIe Port #8 - ASM1061 SATA Controller subsystemid 0x1849 0x1e1e end - device pci 1d.0 on # USB2 EHCI #1 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1849 0x1e26 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge subsystemid 0x1849 0x1e4a chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy @@ -118,14 +118,14 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on # SATA (AHCI) + device ref sata1 on # SATA (AHCI) subsystemid 0x1849 0x1e02 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1849 0x1e22 end - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index abed76a..e1fe7c2 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -2,39 +2,39 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref host_bridge on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe off end # Intel GbE + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 off end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref pcie_rp1 off end # RP #1 + device ref pcie_rp2 off end # RP #2 + device ref pcie_rp3 off end # RP #3 + device ref pcie_rp4 off end # RP #4 + device ref pcie_rp5 off end # RP #5 + device ref pcie_rp6 off end # RP #6 + device ref pcie_rp7 off end # RP #7 + device ref pcie_rp8 off end # RP #8 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref ehci1 on end # EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 41fc4dc..9174e82 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1043 0x844d inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # VGA controller + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIe bridge for discrete graphics + device ref igd on end # VGA controller chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00000295" # Super I/O HWM @@ -14,28 +14,28 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x1043 0x849c end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # HD audio controller + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # HD audio controller subsystemid 0x1043 0x84dc end - device pci 1c.0 on end # PCIe port #1 - device pci 1c.1 off end # PCIe port #2 - device pci 1c.2 off end # PCIe port #3 - device pci 1c.3 off end # PCIe port #4 - device pci 1c.4 on end # PCIe port #5 - device pci 1c.5 on end # PCIe port #6 - device pci 1c.6 on end # PCIe port #7 - device pci 1c.7 off end # PCIe port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pcie_rp1 on end # PCIe port #1 + device ref pcie_rp2 off end # PCIe port #2 + device ref pcie_rp3 off end # PCIe port #3 + device ref pcie_rp4 off end # PCIe port #4 + device ref pcie_rp5 on end # PCIe port #5 + device ref pcie_rp6 on end # PCIe port #6 + device ref pcie_rp7 on end # PCIe port #7 + device ref pcie_rp8 off end # PCIe port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel @@ -74,10 +74,10 @@ device pnp 2e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index 75566d1..0dc77f3 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -2,9 +2,9 @@ chip northbridge/intel/sandybridge device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIEX16_1 - device pci 02.0 on end # iGPU + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIEX16_1 + device ref igd on end # iGPU chip southbridge/intel/bd82x6x register "sata_interface_speed_support" = "0x3" @@ -15,32 +15,32 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 off end # Intel GbE - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref xhci on end # xHCI + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe off end # Intel GbE + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 off end # RP #1 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1c.6 off end # RP #7 - device pci 1c.7 off end # RP #8 + device ref pcie_rp1 off end # RP #1 + device ref pcie_rp2 off end # RP #2 + device ref pcie_rp3 off end # RP #3 + device ref pcie_rp4 off end # RP #4 + device ref pcie_rp5 off end # RP #5 + device ref pcie_rp6 off end # RP #6 + device ref pcie_rp7 off end # RP #7 + device ref pcie_rp8 off end # RP #8 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/biostar/th61-itx/devicetree.cb b/src/mainboard/biostar/th61-itx/devicetree.cb index 5999a1d..611671a 100644 --- a/src/mainboard/biostar/th61-itx/devicetree.cb +++ b/src/mainboard/biostar/th61-itx/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1565 0x3108 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref host_bridge on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x003c0a01" @@ -15,18 +15,18 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio - device pci 1c.0 on end # RP #1: Realtek RTL8111F GbE NIC - device pci 1c.1 on end # RP #2: ASMedia ASM1042 USB3 #1 - device pci 1c.2 on end # RP #3: ASMedia ASM1042 USB3 #2 - device pci 1c.3 off end # RP #4 - device pci 1c.4 off end # RP #5 - device pci 1c.5 off end # RP #6 - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # MEI #1 + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio + device ref pcie_rp1 on end # RP #1: Realtek RTL8111F GbE NIC + device ref pcie_rp2 on end # RP #2: ASMedia ASM1042 USB3 #1 + device ref pcie_rp3 on end # RP #3: ASMedia ASM1042 USB3 #2 + device ref pcie_rp4 off end # RP #4 + device ref pcie_rp5 off end # RP #5 + device ref pcie_rp6 off end # RP #6 + device ref ehci1 on end # EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/ite/it8728f device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # COM1 @@ -56,10 +56,10 @@ device pnp 2e.a off end # CIR end end - device pci 1f.2 on end # SATA #1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA #2 (IDE mode) - device pci 1f.6 on end # Thermal subsystem + device ref sata1 on end # SATA #1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA #2 (IDE mode) + device ref thermal on end # Thermal subsystem end end end diff --git a/src/mainboard/compulab/intense_pc/devicetree.cb b/src/mainboard/compulab/intense_pc/devicetree.cb index 1ce2341..c108d4d 100644 --- a/src/mainboard/compulab/intense_pc/devicetree.cb +++ b/src/mainboard/compulab/intense_pc/devicetree.cb @@ -7,16 +7,16 @@ register "gpu_dp_d_hotplug" = "4" device domain 0 on - device pci 00.0 on # Host bridge + device ref host_bridge on # Host bridge subsystemid 0x8086 0x2010 end - device pci 01.0 on # PCIe Bridge for discrete graphics + device ref peg10 on # PCIe Bridge for discrete graphics subsystemid 0x8086 0x2010 end - device pci 01.1 on # PCIe Bridge for discrete graphics + device ref peg11 on # PCIe Bridge for discrete graphics subsystemid 0x8086 0x2010 end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x8086 0x2211 end @@ -47,29 +47,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 62b0b0b..5e52764 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -6,12 +6,12 @@ end device domain 0 on - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on # PEG1 (blue slot1) + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 on # PEG1 (blue slot1) smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "SLOT1" "SlotDataBusWidth16X" end - device pci 02.0 on end # Internal graphics VGA controller - device pci 06.0 off end # PEG2 + device ref igd on end # Internal graphics VGA controller + device ref peg60 off end # PEG2 chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gpe0_en" = "0x00002a46" @@ -29,25 +29,25 @@ register "superspeed_capable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x08040201" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio controller + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -77,10 +77,10 @@ device pnp 2e.11 off end # PP end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb index d7263c8..b0ef1ee 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb +++ b/src/mainboard/gigabyte/ga-b75m-d3h/devicetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on # Host bridge + device ref host_bridge on # Host bridge subsystemid 0x1458 0x5000 end - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on # Integrated VGA controller + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on # Integrated VGA controller subsystemid 0x1458 0xd000 end @@ -20,37 +20,37 @@ register "superspeed_capable_ports" = "0xf" - device pci 14.0 on # USB 3.0 Controller + device ref xhci on # USB 3.0 Controller subsystemid 0x1458 0x5007 end - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x1458 0x5006 end - device pci 1b.0 on # High Definition Audio + device ref hda on # High Definition Audio subsystemid 0x1458 0xa002 end - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5 device pci 00.0 on # PCI 10ec:8168 subsystemid 0x1458 0xe000 end end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x1458 0x5006 end - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # ISA/LPC bridge + device ref pci_bridge on end # PCI bridge + device ref lpc on # ISA/LPC bridge subsystemid 0x1458 0x5001 chip superio/ite/it8728f device pnp 2e.0 off end # FDC @@ -88,14 +88,14 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x1458 0xb005 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x1458 0x5001 end device pci 1f.4 off end - device pci 1f.5 off end # SATA Controller 2 + device ref sata2 off end # SATA Controller 2 end end end diff --git a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb index 299c134..8b602a3 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb +++ b/src/mainboard/gigabyte/ga-h61m-series/devicetree.cb @@ -4,9 +4,9 @@ device domain 0 on subsystemid 0x1458 0x5000 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 02.0 on end # iGPU + device ref host_bridge on end # Host bridge + device ref peg10 on end # PEG + device ref igd on end # iGPU chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x003c0a01" @@ -15,17 +15,17 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 on end # MEI #1 - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio + device ref mei1 on end # MEI #1 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index 5ff7f9d..24d973e 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -21,9 +21,9 @@ register "max_mem_clock_mhz" = "666" # DDR3-1333 device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -48,27 +48,27 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) - device pci 1c.1 on end # PCIe Port #2 (ETH0) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (mini PCIe Slot - WLAN & Serial debug) + device ref pcie_rp2 on end # PCIe Port #2 (ETH0) + device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) #force ASPM for PCIe bridge to Card Reader register "pcie_aspm[2]" = "0x3" - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -78,10 +78,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 4116188..c5a0a08 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -21,8 +21,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -46,24 +46,24 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 (WLAN remapped) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (WLAN actual) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 off end # PCIe Port #1 (WLAN remapped) + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 (WLAN actual) + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -75,10 +75,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index 7c1cc81..938f248 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -20,8 +20,8 @@ register "max_mem_clock_mhz" = "666" device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -44,34 +44,34 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN) - device pci 1c.2 on end # PCIe Port #3 (ETH0) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 (WLAN) + device ref pcie_rp3 on end # PCIe Port #3 (ETH0) + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on chip ec/compal/ene932 # 60/64 KBC device pnp ff.1 on # dummy address end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 87d0ed9..6710b41 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -27,8 +27,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -55,26 +55,26 @@ # Enable zero-based linear PCIe root port functions register "pcie_port_coalesce" = "true" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 (AUO4, BlueTooth) - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 (AUO4, BlueTooth) + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 (WLAN) + device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) register "pcie_aspm[2]" = "0x3" - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 (LAN) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 on end # PCIe Port #6 (LAN) + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 (Camera, WLAN, WWAN) + device ref pci_bridge off end # PCI bridge + device ref lpc on chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -84,10 +84,10 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 (HDD/SSD) - device pci 1f.3 on end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 (MSATA) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 (HDD/SSD) + device ref smbus on end # SMBus Controller + device ref sata2 off end # SATA Controller 2 (MSATA) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb index ce100b4..13398d0 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb +++ b/src/mainboard/hp/compaq_8200_elite_sff/devicetree.cb @@ -9,9 +9,9 @@ device domain 0 on subsystemid 0x103c 0x1495 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" @@ -24,24 +24,24 @@ register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x0" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt on end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 on end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge on end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/common device pnp 2e.ff on # passes SIO base addr to SSDT gen chip superio/nuvoton/npcd378 @@ -146,10 +146,10 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb index a4d723f..54d522c 100644 --- a/src/mainboard/hp/snb_ivb_laptops/devicetree.cb +++ b/src/mainboard/hp/snb_ivb_laptops/devicetree.cb @@ -18,7 +18,7 @@ device domain 0 on - device pci 00.0 on end # Host bridge + device ref host_bridge on end # Host bridge chip southbridge/intel/bd82x6x # Intel Cougar or Panther Point PCH register "pcie_port_coalesce" = "true" @@ -26,24 +26,24 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/hp/z220_series/devicetree.cb b/src/mainboard/hp/z220_series/devicetree.cb index 6794b62..265b0ef 100644 --- a/src/mainboard/hp/z220_series/devicetree.cb +++ b/src/mainboard/hp/z220_series/devicetree.cb @@ -9,10 +9,10 @@ device domain 0 on subsystemid 0x103c 0x1791 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 06.0 off end # Extra x4 port on north bridge + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref peg60 off end # Extra x4 port on north bridge chip southbridge/intel/bd82x6x # Intel Series 7 PCH register "docking_supported" = "0" @@ -27,25 +27,25 @@ register "xhci_switchable_ports" = "0x0000000f" register "xhci_overcurrent_mapping" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 on end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # xHCI + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt on end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge on end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip superio/common device pnp 2e.ff on # passes SIO base addr to SSDT gen chip superio/nuvoton/npcd378 @@ -150,10 +150,10 @@ device pnp 4e.0 on end # TPM module end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/dcp847ske/devicetree.cb b/src/mainboard/intel/dcp847ske/devicetree.cb index 5400af7..8850436 100644 --- a/src/mainboard/intel/dcp847ske/devicetree.cb +++ b/src/mainboard/intel/dcp847ske/devicetree.cb @@ -12,9 +12,9 @@ register "gpu_dp_b_hotplug" = "0x06" device domain 0 on - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "sata_port_map" = "0x1" @@ -23,25 +23,25 @@ register "gen1_dec" = "0x00fc0a01" # SuperIO @0xa00-0xaff - device pci 14.0 off end # USB xHCI - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 off end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 (unused) - device pci 1c.1 on end # PCIe Port #2 (full-length mPCIe/mSATA) - device pci 1c.2 on end # PCIe Port #3 (half-length mPCIe) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref xhci off end # USB xHCI + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 off end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref pcie_rp1 on end # PCIe Port #1 (unused) + device ref pcie_rp2 on end # PCIe Port #2 (full-length mPCIe/mSATA) + device ref pcie_rp3 on end # PCIe Port #3 (half-length mPCIe) + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 4e.0 off end # Floppy device pnp 4e.1 off end # Parallel port @@ -82,10 +82,10 @@ device pnp 4e.17 off end # GPIOA end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 2eeb745..ea17cc8 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -20,8 +20,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -41,28 +41,28 @@ # SuperIO range is 0x700-0x73f register "gen3_dec" = "0x003c0701" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (WLAN) + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 (Debug) + device ref pcie_rp4 on end # PCIe Port #4 (LAN) + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on end # LPC bridge + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index bf87661..e07cdf2 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -10,9 +10,9 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge x16 - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 on end # PCIe Bridge x16 + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable all SATA ports 0-5 @@ -32,29 +32,29 @@ register "xhci_switchable_ports" = "0x0f" register "superspeed_capable_ports" = "0x0f" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio # Disabling 1c.0 might break IRQ settings as it enables port coalescing # There are two mini PCIe x1 sockets, so one PCIe port is unrouted - device pci 1c.0 on end # PCIe Port #1 mini PCIe x1? - device pci 1c.1 on end # PCIe Port #2 mini PCIe x1? - device pci 1c.2 on end # PCIe Port #3 second Ethernet NIC - device pci 1c.3 on end # PCIe Port #4 third Ethernet NIC - device pci 1c.4 on end # PCIe Port #5 first Ethernet PHY - device pci 1c.5 on end # PCIe Port #6 FireWire - device pci 1c.6 on end # PCIe Port #7 PCIe x1 - device pci 1c.7 on end # PCIe Port #8 mini PCIe x1? + device ref pcie_rp1 on end # PCIe Port #1 mini PCIe x1? + device ref pcie_rp2 on end # PCIe Port #2 mini PCIe x1? + device ref pcie_rp3 on end # PCIe Port #3 second Ethernet NIC + device ref pcie_rp4 on end # PCIe Port #4 third Ethernet NIC + device ref pcie_rp5 on end # PCIe Port #5 first Ethernet PHY + device ref pcie_rp6 on end # PCIe Port #6 FireWire + device ref pcie_rp7 on end # PCIe Port #7 PCIe x1 + device ref pcie_rp8 on end # PCIe Port #8 mini PCIe x1? - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip superio/winbond/w83627dhg device pnp 2e.0 off # Floppy end @@ -134,10 +134,10 @@ end #ec/kontron/it8516e # TODO: TPM on 4e end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/l520/devicetree.cb b/src/mainboard/lenovo/l520/devicetree.cb index 9e56e79..ca16094 100644 --- a/src/mainboard/lenovo/l520/devicetree.cb +++ b/src/mainboard/lenovo/l520/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x21dd inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" @@ -35,24 +35,24 @@ register "spi_uvscc" = "0" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 on end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" @@ -89,8 +89,8 @@ end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -102,8 +102,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/s230u/devicetree.cb b/src/mainboard/lenovo/s230u/devicetree.cb index 16e1004..f105424 100644 --- a/src/mainboard/lenovo/s230u/devicetree.cb +++ b/src/mainboard/lenovo/s230u/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x2205 inherit - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "1" @@ -38,31 +38,31 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -74,8 +74,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index b764a83..33070eb 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21ce inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + device ref host_bridge on end # host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -49,32 +49,32 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on + device ref pcie_rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #5 (Ricoh SD & FW) - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref pcie_rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -136,8 +136,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -150,8 +150,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t420s/devicetree.cb b/src/mainboard/lenovo/t420s/devicetree.cb index 92c9085..b5576b2 100644 --- a/src/mainboard/lenovo/t420s/devicetree.cb +++ b/src/mainboard/lenovo/t420s/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21d2 inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on + device ref host_bridge on end # host bridge + device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M] + device ref igd on subsystemid 0x17aa 0x21d3 end # Integrated Graphics Controller @@ -51,28 +51,28 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 ExpressCard - device pci 1c.4 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref pcie_rp5 on end # PCIe Port #5 NEC Corporation uPD720200A USB 3.0 Host Controller + device ref pcie_rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -134,8 +134,8 @@ register "has_thinker1" = "1" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -148,8 +148,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t430/devicetree.cb b/src/mainboard/lenovo/t430/devicetree.cb index 8b15c84..bcffdaa 100644 --- a/src/mainboard/lenovo/t430/devicetree.cb +++ b/src/mainboard/lenovo/t430/devicetree.cb @@ -36,33 +36,33 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on # PCIe Port #1 + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on # PCIe Port #1 chip drivers/ricoh/rce822 # Ricoh cardreader register "disable_mask" = "0x87" register "sdwppol" = "1" device pci 00.0 on end # Ricoh SD card reader end end - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip ec/lenovo/pmh7 register "backlight_enable" = "0x01" register "dock_event_enable" = "0x01" @@ -125,8 +125,8 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus chip drivers/i2c/at24rf08c # eeprom, 8 virtual devices, same chip device i2c 54 on end device i2c 55 on end @@ -138,12 +138,12 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end - device pci 00.0 on end # Host bridge Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 04.0 off end # Signal processing controller + device ref host_bridge on end # Host bridge Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref dev4 off end # Signal processing controller end end diff --git a/src/mainboard/lenovo/t430s/devicetree.cb b/src/mainboard/lenovo/t430s/devicetree.cb index 9148892..175a5c8 100644 --- a/src/mainboard/lenovo/t430s/devicetree.cb +++ b/src/mainboard/lenovo/t430s/devicetree.cb @@ -17,9 +17,9 @@ device domain 0 on subsystemid 0x17aa 0x21fb inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Integrated Graphics Controller + device ref host_bridge on end # host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd on end # Integrated Graphics Controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -52,29 +52,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB Enhanced Host Controller #2 - device pci 1b.0 on end # High Definition Audio Controller - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 on + device ref ehci2 on end # USB Enhanced Host Controller #2 + device ref hda on end # High Definition Audio Controller + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref pcie_rp3 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #3 ExpressCard - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB Enhanced Host Controller #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe) + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB Enhanced Host Controller #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -118,8 +118,8 @@ register "evente_enable" = "0x0d" end end # LPC Controller - device pci 1f.2 on end # 6 port SATA AHCI Controller - device pci 1f.3 on + device ref sata1 on end # 6 port SATA AHCI Controller + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -132,8 +132,8 @@ device i2c 5f on end end end # SMBus Controller - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb index 55c8d98..7ef12ba2 100644 --- a/src/mainboard/lenovo/t520/devicetree.cb +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21cf inherit - device pci 00.0 on end # host bridge - device pci 01.0 on end # NVIDIA Corporation GF119M [NVS 4200M] - device pci 02.0 on + device ref host_bridge on end # host bridge + device ref peg10 on end # NVIDIA Copcie_rporation GF119M [NVS 4200M] + device ref igd on subsystemid 0x17aa 0x21d1 end # vga controller @@ -50,28 +50,27 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end - device pci 16.2 off end - device pci 16.3 off end - device pci 19.0 on # Intel Gigabit Ethernet + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end + device ref me_ide_r off end + device ref me_kt off end + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21ce end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 Integrated Wireless LAN + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 Express Card - device pci 1c.4 on end # PCIe Port #5 MMC/SDXC + IEEE1394 - device pci 1c.5 off end # PCIe Port #6 Intel Ethernet PHY - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI-2-PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp5 on end # PCIe Port #5 MMC/SDXC + IEEE1394 + device ref pcie_rp6 off end # PCIe Port #6 Intel Ethernet PHY + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -131,8 +130,8 @@ register "has_thinker1" = "1" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBUS controller + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBUS controller # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end diff --git a/src/mainboard/lenovo/t530/devicetree.cb b/src/mainboard/lenovo/t530/devicetree.cb index a274a67..d47acda 100644 --- a/src/mainboard/lenovo/t530/devicetree.cb +++ b/src/mainboard/lenovo/t530/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21f6 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIe bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH # GPI routing @@ -53,29 +53,29 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet subsystemid 0x17aa 0x21f3 end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on # PCIe Port #3 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on # PCIe Port #3 smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # PCI-LPC bridge + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # PCI-LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -137,8 +137,8 @@ register "has_thinker1" = "1" end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -151,8 +151,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x131e/devicetree.cb b/src/mainboard/lenovo/x131e/devicetree.cb index a0de163..0acf98bb 100644 --- a/src/mainboard/lenovo/x131e/devicetree.cb +++ b/src/mainboard/lenovo/x131e/devicetree.cb @@ -17,10 +17,10 @@ device domain 0 on subsystemid 0x17aa 0x21fe inherit - device pci 00.0 on end # Host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # Internal graphics VGA controller - device pci 04.0 off end # Signal processing controller + device ref host_bridge on end # Host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # Internal graphics VGA controller + device ref dev4 off end # Signal processing controller chip southbridge/intel/bd82x6x # GPI routing @@ -48,25 +48,25 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (WLAN card) - device pci 1c.2 on end # PCIe Port #3 (Card Reader) - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 (Ethernet controller) - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge PCI-LPC bridge + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 (WLAN card) + device ref pcie_rp3 on end # PCIe Port #3 (Card Reader) + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 on end # PCIe Port #6 (Ethernet controller) + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge PCI-LPC bridge chip drivers/pc80/tpm device pnp 0c31.0 on end end @@ -108,8 +108,8 @@ register "eventf_enable" = "0xff" end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on # SMBus + device ref sata1 on end # SATA Controller 1 + device ref smbus on # SMBus # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -122,8 +122,8 @@ device i2c 5f on end end end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb index 0c69353..704a410 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb +++ b/src/mainboard/lenovo/x1_carbon_gen1/devicetree.cb @@ -15,9 +15,9 @@ device domain 0 on subsystemid 0x17aa 0x21f9 inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -50,31 +50,31 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on chip drivers/ricoh/rce822 register "sdwppol" = "0" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -121,8 +121,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -135,8 +135,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x220/devicetree.cb b/src/mainboard/lenovo/x220/devicetree.cb index 46459c5..eb79baa 100644 --- a/src/mainboard/lenovo/x220/devicetree.cb +++ b/src/mainboard/lenovo/x220/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21db inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -48,34 +48,34 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21ce end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 (wlan) - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 (wlan) + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 on smbios_slot_desc "7" "3" "ExpressCard Slot" "8" end # PCIe Port #4 - device pci 1c.4 on + device ref pcie_rp5 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #5 (SD) - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -127,8 +127,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -141,8 +141,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/lenovo/x230/devicetree.cb b/src/mainboard/lenovo/x230/devicetree.cb index 5c1c124..490f837 100644 --- a/src/mainboard/lenovo/x230/devicetree.cb +++ b/src/mainboard/lenovo/x230/devicetree.cb @@ -18,9 +18,9 @@ device domain 0 on subsystemid 0x17aa 0x21fa inherit - device pci 00.0 on end # host bridge - device pci 01.0 off end # PCIe Bridge for discrete graphics - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref peg10 off end # PCIe Bridge for discrete graphics + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -51,33 +51,33 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on subsystemid 0x17aa 0x21f3 end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on chip drivers/ricoh/rce822 register "sdwppol" = "1" register "disable_mask" = "0x87" device pci 00.0 on end end end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on #LPC bridge + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on #LPC bridge chip ec/lenovo/pmh7 device pnp ff.1 on end # dummy register "backlight_enable" = "0x01" @@ -130,8 +130,8 @@ register "wwan_gpio_lvl" = "0" end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on + device ref sata1 on end # SATA Controller 1 + device ref smbus on # eeprom, 8 virtual devices, same chip chip drivers/i2c/at24rf08c device i2c 54 on end @@ -144,8 +144,8 @@ device i2c 5f on end end end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb index e0fbc1a..a2c0237 100644 --- a/src/mainboard/msi/ms7707/devicetree.cb +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -2,9 +2,9 @@ device domain 0 on subsystemid 0x1462 0x7707 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PCIe Bridge for discrete graphics - device pci 02.0 off end # Internal graphics + device ref host_bridge on end # Host bridge + device ref peg10 on end # PCIe Bridge for discrete graphics + device ref igd off end # Internal graphics chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "docking_supported" = "0" @@ -17,24 +17,24 @@ register "spi_uvscc" = "0x2005" register "gpe0_en" = "0x28000040" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # HD Audio controller - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # HD Audio controller + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" # 0x28 register "multi_function_register_1" = "0xc0" # 0x29 @@ -94,10 +94,10 @@ end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb index 44e7372..81037e8 100644 --- a/src/mainboard/roda/rv11/variants/rv11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rv11/devicetree.cb @@ -25,8 +25,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # Enable both SATA ports 0, 1 @@ -52,40 +52,40 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # High Definition Audio subsystemid 0x1a86 0x4352 end # Disabling 1c.0 might break IRQ settings as it enables port coalescing - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip ec/roda/it8518 # 60h/64h KBC device pnp ff.0 on # dummy address end end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index c6aa44c..79c182e 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -25,8 +25,8 @@ end device domain 0 on - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # LPC i/o generic decodes @@ -57,30 +57,30 @@ register "spi_uvscc" = "0x2005" register "spi_lvscc" = "0x2005" - device pci 14.0 on end # USB 3.0 Controller - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on # High Definition Audio + device ref xhci on end # USB 3.0 Controller + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on # High Definition Audio subsystemid 0x1a86 0x4352 end # Disabling 1c.0 might break IRQ settings as it enables port coalescing - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 on end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 - device pci 1c.4 on end # PCIe Port #5 - device pci 1c.5 on end # PCIe Port #6 - device pci 1c.6 on end # PCIe Port #7 - device pci 1c.7 on end # PCIe Port #8 + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 on end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 + device ref pcie_rp5 on end # PCIe Port #5 + device ref pcie_rp6 on end # PCIe Port #6 + device ref pcie_rp7 on end # PCIe Port #7 + device ref pcie_rp8 on end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip ec/roda/it8518 register "cpuhot_limit" = "100" # 60h/64h KBC @@ -144,10 +144,10 @@ device pnp 2e.c off end # CIR end end # LPC bridge - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index 4049709..681dfd8 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -21,8 +21,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -40,24 +40,24 @@ register "gen2_dec" = "0x003c0b01" register "gen3_dec" = "0x00fc1601" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (WLAN) + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 on end # PCIe Port #4 (LAN) + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/smsc/mec1308 device pnp 2e.1 on # PM1 io 0x60 = 0xb00 @@ -83,10 +83,10 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index b348f14..4147b16 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -20,8 +20,8 @@ device domain 0 on subsystemid 0x1ae0 0xc000 inherit - device pci 00.0 on end # host bridge - device pci 02.0 on end # vga controller + device ref host_bridge on end # host bridge + device ref igd on end # vga controller chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH # GPI routing @@ -37,24 +37,24 @@ # SuperIO range is 0x700-0x73f register "gen2_dec" = "0x003c0701" - device pci 16.0 on end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 on end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 (WLAN) - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 on end # PCIe Port #3 (Debug) - device pci 1c.3 on end # PCIe Port #4 (LAN) - device pci 1c.4 off end # PCIe Port #5 - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref mei1 on end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on end # USB2 EHCI #2 + device ref hda on end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 (WLAN) + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 on end # PCIe Port #3 (Debug) + device ref pcie_rp4 on end # PCIe Port #4 (LAN) + device ref pcie_rp5 off end # PCIe Port #5 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge chip superio/ite/it8772f # Enable GPIO10 as USBPWRON12# # Enable GPIO12 as USBPWRON13# @@ -102,10 +102,10 @@ device pnp 0c31.0 on end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 on end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal on end # Thermal end end end diff --git a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb index b1beae0..9e6789d 100644 --- a/src/mainboard/sapphire/pureplatinumh61/devicetree.cb +++ b/src/mainboard/sapphire/pureplatinumh61/devicetree.cb @@ -17,38 +17,38 @@ {0x9f, READ_NO_ADDR}, {0xad, WRITE_NO_ADDR}, {0x04, WRITE_NO_ADDR}}" - device pci 16.0 on # Management Engine Interface 1 + device ref mei1 on # Management Engine Interface 1 subsystemid 0x174b 0x1007 end - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 off end # Intel Gigabit Ethernet - device pci 1a.0 on # USB2 EHCI #2 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe off end # Intel Gigabit Ethernet + device ref ehci2 on # USB2 EHCI #2 subsystemid 0x174b 0x1007 end - device pci 1b.0 on # HD Audio Controller + device ref hda on # HD Audio Controller subsystemid 0x8086 0x1c20 end - device pci 1c.0 on # PCIe Port #1 + device ref pcie_rp1 on # PCIe Port #1 subsystemid 0x174b 0x1007 end - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5 subsystemid 0x174b 0x1007 end - device pci 1c.5 on # PCIe Port #6 + device ref pcie_rp6 on # PCIe Port #6 subsystemid 0x174b 0x1007 end - device pci 1c.6 off end # PCIe Port #7 - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on # USB2 EHCI #1 + device ref pcie_rp7 off end # PCIe Port #7 + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on # USB2 EHCI #1 subsystemid 0x174b 0x1007 end - device pci 1e.0 off end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref pci_bridge off end # PCI bridge + device ref lpc on # LPC bridge subsystemid 0x174b 0x1007 chip superio/fintek/f71808a register "multi_function_register_0" = "0x00" @@ -91,22 +91,22 @@ end end end - device pci 1f.2 on # SATA Controller 1 + device ref sata1 on # SATA Controller 1 subsystemid 0x174b 0x1007 end - device pci 1f.3 on # SMBus + device ref smbus on # SMBus subsystemid 0x174b 0x1007 end - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end - device pci 00.0 on # Host bridge + device ref host_bridge on # Host bridge subsystemid 0x174b 0x1007 end - device pci 01.0 on # PCIe Bridge for discrete graphics + device ref peg10 on # PCIe Bridge for discrete graphics subsystemid 0x174b 0x1007 end - device pci 02.0 on # Internal graphics VGA controller + device ref igd on # Internal graphics VGA controller subsystemid 0x8086 0x2010 end end diff --git a/src/mainboard/supermicro/x9sae/devicetree.cb b/src/mainboard/supermicro/x9sae/devicetree.cb index ed011c1..12cbbaf 100644 --- a/src/mainboard/supermicro/x9sae/devicetree.cb +++ b/src/mainboard/supermicro/x9sae/devicetree.cb @@ -10,11 +10,11 @@ device domain 0 on subsystemid 0x15d9 0x0644 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # CPU1 SLOT6 (x8 or x16) - device pci 01.1 on end # CPU1 SLOT4 (electrical x8 in x16 if present) - device pci 02.0 on end # iGPU - device pci 06.0 on end # CPU1 SLOT7 (electrical x4 in x8) + device ref host_bridge on end # Host bridge + device ref peg10 on end # CPU1 SLOT6 (x8 or x16) + device ref peg11 on end # CPU1 SLOT4 (electrical x8 in x16 if present) + device ref igd on end # iGPU + device ref peg60 on end # CPU1 SLOT7 (electrical x4 in x8) chip southbridge/intel/bd82x6x register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) @@ -26,29 +26,29 @@ register "xhci_overcurrent_mapping" = "0x00000c03" register "xhci_switchable_ports" = "0x0000000f" - device pci 14.0 on end # xHCI - device pci 16.0 on end # MEI #1 - device pci 16.1 off end # MEI #2 - device pci 16.2 off end # ME IDE-R - device pci 16.3 off end # ME KT - device pci 19.0 on end # Intel GbE LAN1 - device pci 1a.0 on end # EHCI #2 - device pci 1b.0 on end # HD Audio + device ref xhci on end # xHCI + device ref mei1 on end # MEI #1 + device ref mei2 off end # MEI #2 + device ref me_ide_r off end # ME IDE-R + device ref me_kt off end # ME KT + device ref gbe on end # Intel GbE LAN1 + device ref ehci2 on end # EHCI #2 + device ref hda on end # HD Audio - device pci 1c.0 on end # RP #1 PCH SLOT2 - device pci 1c.1 off end # RP #2 - device pci 1c.2 off end # RP #3 - device pci 1c.3 off end # RP #4 - device pci 1c.4 on end # RP #5 PCH SLOT3 - device pci 1c.5 off end # RP #6 - device pci 1c.6 on end # RP #7 PCH SLOT5 - device pci 1c.7 on # RP #8 + device ref pcie_rp1 on end # RP #1 PCH SLOT2 + device ref pcie_rp2 off end # RP #2 + device ref pcie_rp3 off end # RP #3 + device ref pcie_rp4 off end # RP #4 + device ref pcie_rp5 on end # RP #5 PCH SLOT3 + device ref pcie_rp6 off end # RP #6 + device ref pcie_rp7 on end # RP #7 PCH SLOT5 + device ref pcie_rp8 on # RP #8 device pci 00.0 on end # 574 GbE LAN2 end - device pci 1d.0 on end # EHCI #1 - device pci 1e.0 on end # PCI bridge - device pci 1f.0 on # LPC bridge + device ref ehci1 on end # EHCI #1 + device ref pci_bridge on end # PCI bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel port @@ -108,10 +108,10 @@ device pnp c31.0 on end # TPM end end - device pci 1f.2 on end # SATA (AHCI) - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA (Legacy) - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA (AHCI) + device ref smbus on end # SMBus + device ref sata2 off end # SATA (Legacy) + device ref thermal off end # Thermal end end end diff --git a/src/mainboard/supermicro/x9scl/devicetree.cb b/src/mainboard/supermicro/x9scl/devicetree.cb index b0f3534..e20aac2 100644 --- a/src/mainboard/supermicro/x9scl/devicetree.cb +++ b/src/mainboard/supermicro/x9scl/devicetree.cb @@ -1,11 +1,11 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x15d9 0x0624 inherit - device pci 00.0 on end # Host bridge - device pci 01.0 on end # PEG - device pci 01.1 on end # PEG - device pci 02.0 off end # iGPU - device pci 06.0 on end # PEG + device ref host_bridge on end # Host bridge + device ref peg10 on end # PEG + device ref peg11 on end # PEG + device ref igd off end # iGPU + device ref peg60 on end # PEG chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH register "gen1_dec" = "0x00fc0a01" # NCT6776 SuperIO (0x0a00-0aff) register "gen2_dec" = "0x00fc1641" # WPCM450 SuperIO (0x1600-16ff) @@ -16,32 +16,32 @@ register "sata_port_map" = "0x3f" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" - device pci 16.0 off end # Management Engine Interface 1 - device pci 16.1 off end # Management Engine Interface 2 - device pci 16.2 off end # Management Engine IDE-R - device pci 16.3 off end # Management Engine KT - device pci 19.0 on # Intel Gigabit Ethernet (not for X9SCL+-F) + device ref mei1 off end # Management Engine Interface 1 + device ref mei2 off end # Management Engine Interface 2 + device ref me_ide_r off end # Management Engine IDE-R + device ref me_kt off end # Management Engine KT + device ref gbe on # Intel Gigabit Ethernet (not for X9SCL+-F) subsystemid 0x15d9 0x1502 end - device pci 1a.0 on end # USB2 EHCI #2 - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 on end # PCIe Port #1 - device pci 1c.1 off end # PCIe Port #2 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1c.4 on # PCIe Port #5 + device ref ehci2 on end # USB2 EHCI #2 + device ref hda off end # High Definition Audio + device ref pcie_rp1 on end # PCIe Port #1 + device ref pcie_rp2 off end # PCIe Port #2 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref pcie_rp5 on # PCIe Port #5 device pci 00.0 on end # primary 574 GigE end - device pci 1c.5 off end # PCIe Port #6 - device pci 1c.6 on # PCIe Port #7 + device ref pcie_rp6 off end # PCIe Port #6 + device ref pcie_rp7 on # PCIe Port #7 device pci 00.0 on end # secondary 574 GigE on X9SCL+-F end - device pci 1c.7 off end # PCIe Port #8 - device pci 1d.0 on end # USB2 EHCI #1 - device pci 1e.0 on # PCI bridge + device ref pcie_rp8 off end # PCIe Port #8 + device ref ehci1 on end # USB2 EHCI #1 + device ref pci_bridge on # PCI bridge device pci 03.0 on end # Matrox G200e in BMC end - device pci 1f.0 on # LPC bridge + device ref lpc on # LPC bridge chip superio/nuvoton/nct6776 device pnp 2e.0 off end # Floppy device pnp 2e.1 off end # Parallel port @@ -105,10 +105,10 @@ device pnp 164e.6 off end end end - device pci 1f.2 on end # SATA Controller 1 - device pci 1f.3 on end # SMBus - device pci 1f.5 off end # SATA Controller 2 - device pci 1f.6 off end # Thermal + device ref sata1 on end # SATA Controller 1 + device ref smbus on end # SMBus + device ref sata2 off end # SATA Controller 2 + device ref thermal off end # Thermal end end end diff --git a/src/northbridge/intel/sandybridge/chipset.cb b/src/northbridge/intel/sandybridge/chipset.cb index afa1e5b..5635ca6 100644 --- a/src/northbridge/intel/sandybridge/chipset.cb +++ b/src/northbridge/intel/sandybridge/chipset.cb @@ -10,5 +10,38 @@ end device domain 0 on ops sandybridge_pci_domain_ops + device pci 00.0 alias host_bridge on end # host bridge + device pci 01.0 alias peg10 off end # PEG10 + device pci 01.1 alias peg11 off end # PEG11 + device pci 01.2 alias peg12 off end # PEG12 + device pci 02.0 alias igd off end # vga controller + device pci 04.0 alias dev4 off end # Device 4 + device pci 06.0 alias peg60 off end # PEG60 + + chip southbridge/intel/bd82x6x # Intel Series 6/7 PCH + device pci 14.0 alias xhci off end # USB 3.0 Controller (only on 7 series) + device pci 16.0 alias mei1 on end # Management Engine Interface 1 + device pci 16.1 alias mei2 off end # Management Engine Interface 2 + device pci 16.2 alias me_ide_r off end # Management Engine IDE-R + device pci 16.3 alias me_kt off end # Management Engine KT + device pci 19.0 alias gbe off end # Intel Gigabit Ethernet + device pci 1a.0 alias ehci2 off end # USB2 EHCI #2 + device pci 1b.0 alias hda off end # High Definition Audio + device pci 1c.0 alias pcie_rp1 off end # PCIe Port #1 + device pci 1c.1 alias pcie_rp2 off end # PCIe Port #2 + device pci 1c.2 alias pcie_rp3 off end # PCIe Port #3 + device pci 1c.3 alias pcie_rp4 off end # PCIe Port #4 + device pci 1c.4 alias pcie_rp5 off end # PCIe Port #5 + device pci 1c.5 alias pcie_rp6 off end # PCIe Port #6 + device pci 1c.6 alias pcie_rp7 off end # PCIe Port #7 + device pci 1c.7 alias pcie_rp8 off end # PCIe Port #8 + device pci 1d.0 alias ehci1 off end # USB2 EHCI #1 + device pci 1e.0 alias pci_bridge off end # PCI bridge + device pci 1f.0 alias lpc on end # LPC bridge + device pci 1f.2 alias sata1 off end # SATA Controller 1 + device pci 1f.3 alias smbus on end # SMBus + device pci 1f.5 alias sata2 off end # SATA Controller 2 + device pci 1f.6 alias thermal off end # Thermal + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/69502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Gerrit-Change-Number: 69502 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: util/autoport: Use chipset.cb references
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72597 ) Change subject: util/autoport: Use chipset.cb references ...................................................................... util/autoport: Use chipset.cb references TESTED with x220 logs. Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72597 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jakub Czapiga <jacz(a)semihalf.com> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/autoport/bd82x6x.go M util/autoport/main.go M util/autoport/sandybridge.go 3 files changed, 62 insertions(+), 34 deletions(-) Approvals: build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved Jakub Czapiga: Looks good to me, but someone else must approve diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go index f00c89f..987d7bf 100644 --- a/util/autoport/bd82x6x.go +++ b/util/autoport/bd82x6x.go @@ -230,34 +230,34 @@ "sata_port_map": fmt.Sprintf("0x%x", PCIMap[PCIAddr{Bus: 0, Dev: 0x1f, Func: 2}].ConfigDump[0x92]&0x3f), - "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), - "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), - "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), + "docking_supported": (FormatBool((FADT[113] & (1 << 1)) != 0)), + "spi_uvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c8]), + "spi_lvscc": fmt.Sprintf("0x%x", inteltool.RCBA[0x38c4]&^(1<<23)), }, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, additionalComment: "USB 3.0 Controller"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, additionalComment: "Management Engine Interface 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, additionalComment: "Management Engine Interface 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, additionalComment: "Management Engine IDE-R"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, additionalComment: "Management Engine KT"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, additionalComment: "Intel Gigabit Ethernet"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, additionalComment: "High Definition Audio"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, additionalComment: "PCIe Port #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, additionalComment: "PCIe Port #2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, additionalComment: "PCIe Port #3"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, additionalComment: "PCIe Port #4"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, additionalComment: "PCIe Port #5"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, additionalComment: "PCIe Port #6"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, additionalComment: "PCIe Port #7"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, additionalComment: "PCIe Port #8"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, additionalComment: "USB2 EHCI #1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, additionalComment: "PCI bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, additionalComment: "LPC bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, additionalComment: "SATA Controller 1"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, additionalComment: "SMBus"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, additionalComment: "SATA Controller 2"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, additionalComment: "Thermal"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x14, Func: 0}, writeEmpty: false, alias: "xhci", additionalComment: "USB 3.0 Controller"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 0}, writeEmpty: true, alias: "mei1", additionalComment: "Management Engine Interface 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 1}, writeEmpty: true, alias: "mei2", additionalComment: "Management Engine Interface 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 2}, writeEmpty: true, alias: "me_ide_r", additionalComment: "Management Engine IDE-R"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x16, Func: 3}, writeEmpty: true, alias: "me_kt", additionalComment: "Management Engine KT"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x19, Func: 0}, writeEmpty: true, alias: "gbe", additionalComment: "Intel Gigabit Ethernet"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1a, Func: 0}, writeEmpty: true, alias: "echi2", additionalComment: "USB2 EHCI #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1b, Func: 0}, writeEmpty: true, alias: "hda", additionalComment: "High Definition Audio"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 0}, writeEmpty: true, alias: "pcie_rp1", additionalComment: "PCIe Port #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 1}, writeEmpty: true, alias: "pcie_rp2", additionalComment: "PCIe Port #2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 2}, writeEmpty: true, alias: "pcie_rp3", additionalComment: "PCIe Port #3"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 3}, writeEmpty: true, alias: "pcie_rp4", additionalComment: "PCIe Port #4"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 4}, writeEmpty: true, alias: "pcie_rp5", additionalComment: "PCIe Port #5"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 5}, writeEmpty: true, alias: "pcie_rp6", additionalComment: "PCIe Port #6"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 6}, writeEmpty: true, alias: "pcie_rp7", additionalComment: "PCIe Port #7"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1c, Func: 7}, writeEmpty: true, alias: "pcie_rp8", additionalComment: "PCIe Port #8"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1d, Func: 0}, writeEmpty: true, alias: "ehci1", additionalComment: "USB2 EHCI #1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1e, Func: 0}, writeEmpty: true, alias: "pci_bridge", additionalComment: "PCI bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 0}, writeEmpty: true, alias: "lpc", additionalComment: "LPC bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 2}, writeEmpty: true, alias: "sata1", additionalComment: "SATA Controller 1"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 3}, writeEmpty: true, alias: "smbus", additionalComment: "SMBus"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 5}, writeEmpty: true, alias: "sata2", additionalComment: "SATA Controller 2"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1f, Func: 6}, writeEmpty: true, alias: "thermal", additionalComment: "Thermal"}, }, } @@ -278,7 +278,7 @@ File: "southbridge/intel/common/acpi/platform.asl", }) DSDTIncludes = append(DSDTIncludes, DSDTInclude{ - File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", + File: "southbridge/intel/bd82x6x/acpi/globalnvs.asl", }) DSDTIncludes = append(DSDTIncludes, DSDTInclude{ File: "southbridge/intel/common/acpi/sleepstates.asl", diff --git a/util/autoport/main.go b/util/autoport/main.go index 9b0b436..ed7cb0e 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -238,6 +238,7 @@ type PCISlot struct { PCIAddr + alias string additionalComment string writeEmpty bool } @@ -361,14 +362,18 @@ } } -func WriteDev(dt *os.File, offset int, dev DevTreeNode) { +func WriteDev(dt *os.File, offset int, alias string, dev DevTreeNode) { Offset(dt, offset) switch dev.Chip { case "cpu_cluster", "lapic", "domain", "ioapic": fmt.Fprintf(dt, "device %s 0x%x ", dev.Chip, dev.Dev) writeOn(dt, dev) case "pci", "pnp": - fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + if alias != "" { + fmt.Fprintf(dt, "device ref %s ", alias) + } else { + fmt.Fprintf(dt, "device %s %02x.%x ", dev.Chip, dev.Dev, dev.Func) + } writeOn(dt, dev) case "i2c": fmt.Fprintf(dt, "device %s %02x ", dev.Chip, dev.Dev) @@ -422,7 +427,14 @@ } for _, child := range dev.Children { - WriteDev(dt, offset+1, child) + alias = "" + for _, slot := range dev.PCISlots { + if slot.PCIAddr.Bus == child.Bus && + slot.PCIAddr.Dev == child.Dev && slot.PCIAddr.Func == child.Func { + alias = slot.alias + } + } + WriteDev(dt, offset+1, alias, child) } Offset(dt, offset) @@ -739,7 +751,7 @@ defer devtree.Close() MatchDev(&DevTree) - WriteDev(devtree, 0, DevTree) + WriteDev(devtree, 0, "", DevTree) if MainboardInit != "" || MainboardEnable != "" || MainboardIncludes != nil { mainboard := Create(ctx, "mainboard.c") diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go index a60018e..bd7f0f0 100644 --- a/util/autoport/sandybridge.go +++ b/util/autoport/sandybridge.go @@ -41,9 +41,9 @@ PCIController: true, ChildPCIBus: 0, PCISlots: []PCISlot{ - PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"}, - PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"}, + PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"}, }, }, }, -- To view, visit https://review.coreboot.org/c/coreboot/+/72597 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3 Gerrit-Change-Number: 72597 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: include/bootstate.h: Fail compilation on invalid bootstate hooks
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72708 ) Change subject: include/bootstate.h: Fail compilation on invalid bootstate hooks ...................................................................... include/bootstate.h: Fail compilation on invalid bootstate hooks No BS_ON_EXIT hooks are run on BS_PAYLOAD_BOOT or BS_OS_RESUME, so don't allow these hooks. Change-Id: I318165f0bd510aed3138d3612dd3e264901aba96 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72708 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/include/bootstate.h 1 file changed, 22 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Benjamin Doron: Looks good to me, approved diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 87ed0c8..a1743a8 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -188,7 +188,11 @@ }; \ static struct boot_state_init_entry * \ bsie_ ## func_ ##_## state_ ##_## when_ BOOT_STATE_INIT_ATTR = \ - &func_ ##_## state_ ##_## when_; + &func_ ##_## state_ ##_## when_; \ + _Static_assert(!(state_ == BS_PAYLOAD_BOOT && when_ == BS_ON_EXIT), \ + "Invalid bootstate hook"); \ + _Static_assert(!(state_ == BS_OS_RESUME && when_ == BS_ON_EXIT), \ + "Invalid bootstate hook"); /* Hook per arch when coreboot is exiting to payload or ACPI OS resume. It's * the very last thing done before the transition. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72708 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I318165f0bd510aed3138d3612dd3e264901aba96 Gerrit-Change-Number: 72708 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: soc/intel/*: Fix dead bootstate code
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72707 ) Change subject: soc/intel/*: Fix dead bootstate code ...................................................................... soc/intel/*: Fix dead bootstate code No bootstate hook is called on exit of BS_OS_RESUME or BS_PAYLOAD_BOOT. Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72707 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/common/block/gpio/gpio.c M src/soc/intel/skylake/pmc.c 2 files changed, 17 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Benjamin Doron: Looks good to me, approved diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index 08fce94..015b5da 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -1028,7 +1028,7 @@ free(snapshot); } -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_EXIT, snapshot_cleanup, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, snapshot_cleanup, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, snapshot_cleanup, NULL); bool gpio_get_vw_info(gpio_t pad, unsigned int *vw_index, unsigned int *vw_bit) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 61662d2..71d1ef0 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -144,4 +144,4 @@ } BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_handle_wake_pin, NULL); -BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_EXIT, pm1_handle_wake_pin, NULL); +BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, pm1_handle_wake_pin, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/72707 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2b5b834d0663616a9523fd119f007e3bac8e7bf2 Gerrit-Change-Number: 72707 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/starlabs/starbook/adl: Enable HPD GPIO
by Paul Fagerburg (Code Review) 04 Feb '23

04 Feb '23

Paul Fagerburg has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72431 ) Change subject: mb/starlabs/starbook/adl: Enable HPD GPIO ...................................................................... mb/starlabs/starbook/adl: Enable HPD GPIO Enable the HPD GPIO so that the USB-C port can be used for DisplayPort. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/starlabs/starbook/variants/adl/gpio.c 1 file changed, 17 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved diff --git a/src/mainboard/starlabs/starbook/variants/adl/gpio.c b/src/mainboard/starlabs/starbook/variants/adl/gpio.c index 0113164..7da161b 100644 --- a/src/mainboard/starlabs/starbook/variants/adl/gpio.c +++ b/src/mainboard/starlabs/starbook/variants/adl/gpio.c @@ -75,7 +75,7 @@ /* A18: DDI B DP HPD */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* A19: TCP0 HPD */ - PAD_NC(GPP_A19, NONE), + PAD_CFG_NF(GPP_A19, NONE, PLTRST, NF1), /* A20: Test Point 44 */ PAD_NC(GPP_A20, NONE), /* A21: Fingerprint Reader Interrupt */ -- To view, visit https://review.coreboot.org/c/coreboot/+/72431 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Gerrit-Change-Number: 72431 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Paul Fagerburg <pfagerburg(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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