coreboot-gerrit February 2023

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[S] Change in coreboot[master]: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform
by Harsha B R (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Ravishankar Sarawadi, Sridhar Siricilla. Harsha B R has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72742 ) Change subject: mb/intel/mtlrvp: Remove GPP_A12 for chrome platform ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Interesting, since no one use it why it prevent the G3? Or real HW is connected to WLAN? Yes, the WLAN is connected and the signal wrt GPP_A12 pin never turns the 1.8A rail low even though the system is at S5. At S5, since this is still active (which turns out to be a wake signal) at S5, DUT reboots. -- To view, visit https://review.coreboot.org/c/coreboot/+/72742 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 Gerrit-Change-Number: 72742 Gerrit-PatchSet: 1 Gerrit-Owner: Harsha B R <harsha.b.r(a)intel.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Anilkumar N <anilkumar.n(a)intel.com> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Attention: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 03:29:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[master]: mb/google/brya/var/constitution: Add SOLDERDOWN support
by build bot (Jenkins) (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: David Wu, Tarun Tuli. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72775 ) Change subject: mb/google/brya/var/constitution: Add SOLDERDOWN support ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt: Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-169858): https://review.coreboot.org/c/coreboot/+/72775/comment/d06c3f5d_b48c1864 PS3, Line 9: # See util/spd_tools/README.md for more details and instructions. 'README' may be misspelled - perhaps 'README'? -- To view, visit https://review.coreboot.org/c/coreboot/+/72775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Gerrit-Change-Number: 72775 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 03:25:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72735 ) Change subject: soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges ...................................................................... soc/amd/cezanne/chipset.cb: add missing ops for GPP GFX bridges Commit b171f768127d ("soc/amd/*: Hook up GPP bridges ops to devicetree") missed adding the amd_external_pcie_gpp_ops ops to the gpp_gfx_bridge PCIe ports, so add them. Those devices were previously covered by the PCI_DID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 PCI device ID in the list that got removed in the referenced commit. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72735 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> --- M src/soc/amd/cezanne/chipset.cb 1 file changed, 22 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Fred Reitberger: Looks good to me, approved diff --git a/src/soc/amd/cezanne/chipset.cb b/src/soc/amd/cezanne/chipset.cb index 691153f..c779390 100644 --- a/src/soc/amd/cezanne/chipset.cb +++ b/src/soc/amd/cezanne/chipset.cb @@ -8,9 +8,9 @@ device pci 00.2 alias iommu off ops amd_iommu_ops end device pci 01.0 on end # Dummy Host Bridge, do not disable - device pci 01.1 alias gpp_gfx_bridge_0 off end - device pci 01.2 alias gpp_gfx_bridge_1 off end - device pci 01.3 alias gpp_gfx_bridge_2 off end + device pci 01.1 alias gpp_gfx_bridge_0 off ops amd_external_pcie_gpp_ops end + device pci 01.2 alias gpp_gfx_bridge_1 off ops amd_external_pcie_gpp_ops end + device pci 01.3 alias gpp_gfx_bridge_2 off ops amd_external_pcie_gpp_ops end device pci 02.0 on end # Dummy Host Bridge, do not disable device pci 02.1 alias gpp_bridge_0 off ops amd_external_pcie_gpp_ops end -- To view, visit https://review.coreboot.org/c/coreboot/+/72735 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I55434bf486569b32901b3840193a09cc5955abb2 Gerrit-Change-Number: 72735 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: mb/google/brya/var/constitution: Add SOLDERDOWN support
by David Wu (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: David Wu, Tarun Tuli. David Wu has uploaded a new patch set (#3) to the change originally created by Morris Hsu. ( https://review.coreboot.org/c/coreboot/+/72775 ) Change subject: mb/google/brya/var/constitution: Add SOLDERDOWN support ...................................................................... mb/google/brya/var/constitution: Add SOLDERDOWN support Constitution will use SOLDERDOWN. Add memory.c to override baseboard. BUG=b:267539938 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Signed-off-by: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/Kconfig.name A src/mainboard/google/brya/variants/constitution/Makefile.inc A src/mainboard/google/brya/variants/constitution/memory.c A src/mainboard/google/brya/variants/constitution/memory/Makefile.inc A src/mainboard/google/brya/variants/constitution/memory/dram_id.generated.txt A src/mainboard/google/brya/variants/constitution/memory/mem_parts_used.txt 7 files changed, 140 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/72775/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/72775 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4 Gerrit-Change-Number: 72775 Gerrit-PatchSet: 3 Gerrit-Owner: Morris Hsu <morris-hsu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Tarun Tuli <taruntuli(a)google.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PCO SoC
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72755 ) Change subject: soc/amd: Use common reset code for PCO SoC ...................................................................... soc/amd: Use common reset code for PCO SoC This switches the Picasso SoC to use the common reset code. Picasso supports warm resets, so set the SOC_AMD_SUPPORTS_WARM_RESET flag. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72755 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc D src/soc/amd/picasso/reset.c 3 files changed, 20 insertions(+), 32 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index a0254e9..d34b2ab 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -50,6 +50,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SATA select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI @@ -61,6 +62,7 @@ select SOC_AMD_COMMON_BLOCK_UART select SOC_AMD_COMMON_BLOCK_UCODE select SOC_AMD_COMMON_FSP_DMI_TABLES + select SOC_AMD_SUPPORTS_WARM_RESET select SSE2 select UDK_2017_BINDING select USE_DDR4 diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 50fc62c..e7ed68e 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -12,19 +12,16 @@ bootblock-y += early_fch.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c @@ -38,7 +35,6 @@ ramstage-y += i2c.c ramstage-y += mca.c ramstage-y += pcie_gpp.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += sata.c ramstage-y += soc_util.c diff --git a/src/soc/amd/picasso/reset.c b/src/soc/amd/picasso/reset.c deleted file mode 100644 index 8181d90..0000000 --- a/src/soc/amd/picasso/reset.c +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - /* TODO: Would a warm_reset() suffice? */ - do_cold_reset(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72755 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I52515b20ef6c70b137f176d95480757b16bd8735 Gerrit-Change-Number: 72755 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Use common reset code for PHX & Glinda SoCs
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72754 ) Change subject: soc/amd: Use common reset code for PHX & Glinda SoCs ...................................................................... soc/amd: Use common reset code for PHX & Glinda SoCs This switches the Phoenix & Glinda SoCs to use the common reset code. Cezanne and newer do not support warm reset, so use cold resets in all cases (including the OS). Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72754 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/Makefile.inc M src/soc/amd/glinda/fch.c D src/soc/amd/glinda/reset.c M src/soc/amd/phoenix/Kconfig M src/soc/amd/phoenix/Makefile.inc M src/soc/amd/phoenix/fch.c D src/soc/amd/phoenix/reset.c 8 files changed, 24 insertions(+), 66 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 7b0b736..214fc81 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMI # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_SMM # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/Makefile.inc b/src/soc/amd/glinda/Makefile.inc index 891a68d..ef0d27d 100644 --- a/src/soc/amd/glinda/Makefile.inc +++ b/src/soc/amd/glinda/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/glinda/fch.c b/src/soc/amd/glinda/fch.c index af5f0ec..5608e7c 100644 --- a/src/soc/amd/glinda/fch.c +++ b/src/soc/amd/glinda/fch.c @@ -6,6 +6,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -196,6 +197,7 @@ void fch_init(void *chip_info) { + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/glinda/reset.c b/src/soc/amd/glinda/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/glinda/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 883359c..37a2fc9 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/phoenix/Makefile.inc b/src/soc/amd/phoenix/Makefile.inc index 1c24243..84825d0 100644 --- a/src/soc/amd/phoenix/Makefile.inc +++ b/src/soc/amd/phoenix/Makefile.inc @@ -15,19 +15,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -40,7 +37,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/phoenix/fch.c b/src/soc/amd/phoenix/fch.c index 91df79e..c2f0558 100644 --- a/src/soc/amd/phoenix/fch.c +++ b/src/soc/amd/phoenix/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -192,6 +193,7 @@ void fch_init(void *chip_info) { + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/phoenix/reset.c b/src/soc/amd/phoenix/reset.c deleted file mode 100644 index 83bfcee..0000000 --- a/src/soc/amd/phoenix/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Move to common? */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Assert reset signals only. */ - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72754 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4593fa9766ac9e988722a02e355c971e147b8fae Gerrit-Change-Number: 72754 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: soc/amd: Use common reset code for CZN & MDN SoCs
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72659 ) Change subject: soc/amd: Use common reset code for CZN & MDN SoCs ...................................................................... soc/amd: Use common reset code for CZN & MDN SoCs This switches the Cezanne & Mendocino SoCs to use the common reset code. This patch does not change any behavior on those chips. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72659 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/cezanne/Kconfig M src/soc/amd/cezanne/Makefile.inc M src/soc/amd/cezanne/fch.c D src/soc/amd/cezanne/reset.c M src/soc/amd/mendocino/Kconfig M src/soc/amd/mendocino/Makefile.inc M src/soc/amd/mendocino/fch.c D src/soc/amd/mendocino/reset.c 8 files changed, 22 insertions(+), 76 deletions(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 35c2927..e1ab7b8 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -55,6 +55,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/cezanne/Makefile.inc b/src/soc/amd/cezanne/Makefile.inc index 5313e0d..a8474e2 100644 --- a/src/soc/amd/cezanne/Makefile.inc +++ b/src/soc/amd/cezanne/Makefile.inc @@ -12,18 +12,15 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -37,7 +34,6 @@ ramstage-y += graphics.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/cezanne/fch.c b/src/soc/amd/cezanne/fch.c index 0936c5e..f065c8e 100644 --- a/src/soc/amd/cezanne/fch.c +++ b/src/soc/amd/cezanne/fch.c @@ -4,6 +4,7 @@ #include <amdblocks/acpimmio.h> #include <amdblocks/amd_pci_util.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/gpio.h> #include <amdblocks/i2c.h> #include <amdblocks/smi.h> @@ -130,11 +131,6 @@ PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* Configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -204,7 +200,7 @@ void fch_init(void *chip_info) { - fch_init_resets(); + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/cezanne/reset.c b/src/soc/amd/cezanne/reset.c deleted file mode 100644 index 1360bd5..0000000 --- a/src/soc/amd/cezanne/reset.c +++ /dev/null @@ -1,29 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 7faa479..5b274f9 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -61,6 +61,7 @@ select SOC_AMD_COMMON_BLOCK_PM select SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE select SOC_AMD_COMMON_BLOCK_PSP_GEN2 + select SOC_AMD_COMMON_BLOCK_RESET select SOC_AMD_COMMON_BLOCK_SMBUS select SOC_AMD_COMMON_BLOCK_SMI select SOC_AMD_COMMON_BLOCK_SMM diff --git a/src/soc/amd/mendocino/Makefile.inc b/src/soc/amd/mendocino/Makefile.inc index 7d7033a..1dc0773 100644 --- a/src/soc/amd/mendocino/Makefile.inc +++ b/src/soc/amd/mendocino/Makefile.inc @@ -14,19 +14,16 @@ bootblock-y += espi_util.c bootblock-y += gpio.c bootblock-y += i2c.c -bootblock-y += reset.c bootblock-y += uart.c verstage-y += i2c.c verstage-y += espi_util.c verstage_x86-y += gpio.c -verstage_x86-y += reset.c verstage_x86-y += uart.c romstage-y += fsp_m_params.c romstage-y += gpio.c romstage-y += i2c.c -romstage-y += reset.c romstage-y += romstage.c romstage-y += uart.c @@ -39,7 +36,6 @@ ramstage-y += gpio.c ramstage-y += i2c.c ramstage-y += mca.c -ramstage-y += reset.c ramstage-y += root_complex.c ramstage-y += uart.c ramstage-y += xhci.c diff --git a/src/soc/amd/mendocino/fch.c b/src/soc/amd/mendocino/fch.c index abe2dc1..5edbcc6 100644 --- a/src/soc/amd/mendocino/fch.c +++ b/src/soc/amd/mendocino/fch.c @@ -5,6 +5,7 @@ #include <amdblocks/amd_pci_util.h> #include <amdblocks/gpio.h> #include <amdblocks/pci_clk_req.h> +#include <amdblocks/reset.h> #include <amdblocks/smi.h> #include <assert.h> #include <bootstate.h> @@ -126,11 +127,6 @@ PM_ACPI_TIMER_EN_EN); } -static void fch_init_resets(void) -{ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); -} - /* configure the general purpose PCIe clock outputs according to the devicetree settings */ static void gpp_clk_setup(void) { @@ -202,7 +198,7 @@ void fch_init(void *chip_info) { - fch_init_resets(); + set_resets_to_cold(); i2c_soc_init(); fch_init_acpi_ports(); diff --git a/src/soc/amd/mendocino/reset.c b/src/soc/amd/mendocino/reset.c deleted file mode 100644 index ac0c981..0000000 --- a/src/soc/amd/mendocino/reset.c +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/io.h> -#include <cf9_reset.h> -#include <reset.h> -#include <soc/southbridge.h> -#include <amdblocks/acpimmio.h> -#include <amdblocks/reset.h> - -void do_cold_reset(void) -{ - /* De-assert and then assert all PwrGood signals on CF9 reset. */ - pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | - TOGGLE_ALL_PWR_GOOD); - outb(RST_CPU | SYS_RST, RST_CNT); -} - -void do_warm_reset(void) -{ - /* Warm resets are not supported and must be executed as cold */ - do_cold_reset(); -} - -void do_board_reset(void) -{ - do_cold_reset(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/72659 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie05c790573e4e68f3ec91bacffcc7d7efb986d79 Gerrit-Change-Number: 72659 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... soc/amd: Create AMD common reset code This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda. PCO supports the warm reset, and future chips can support it by setting the SOC_AMD_SUPPORTS_WARM_RESET option. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658 Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/common/block/include/amdblocks/reset.h M src/soc/amd/common/block/pm/Kconfig M src/soc/amd/common/block/pm/Makefile.inc A src/soc/amd/common/block/pm/reset.c 4 files changed, 73 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved diff --git a/src/soc/amd/common/block/include/amdblocks/reset.h b/src/soc/amd/common/block/include/amdblocks/reset.h index 353720c..3706d08 100644 --- a/src/soc/amd/common/block/include/amdblocks/reset.h +++ b/src/soc/amd/common/block/include/amdblocks/reset.h @@ -3,9 +3,11 @@ #ifndef AMD_BLOCK_RESET_H #define AMD_BLOCK_RESET_H -#include <console/console.h> +#include <amdblocks/acpimmio.h> #include <arch/cache.h> +#include <console/console.h> #include <halt.h> +#include <soc/southbridge.h> void do_warm_reset(void); void do_cold_reset(void); @@ -28,4 +30,10 @@ halt(); } +static inline void set_resets_to_cold(void) +{ + /* De-assert and then assert all PwrGood signals on CF9 reset. */ + pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD); +} + #endif /* AMD_BLOCK_RESET_H */ diff --git a/src/soc/amd/common/block/pm/Kconfig b/src/soc/amd/common/block/pm/Kconfig index 538301d..7d2513e 100644 --- a/src/soc/amd/common/block/pm/Kconfig +++ b/src/soc/amd/common/block/pm/Kconfig @@ -15,3 +15,14 @@ platforms that use FSP for hardware initialization. endif # SOC_AMD_COMMON_BLOCK_PM + +config SOC_AMD_COMMON_BLOCK_RESET + bool + help + Select this option to use AMD common reset driver support. + +config SOC_AMD_SUPPORTS_WARM_RESET + bool + depends on SOC_AMD_COMMON_BLOCK_RESET + help + Select this option if the chip supports warm reset. diff --git a/src/soc/amd/common/block/pm/Makefile.inc b/src/soc/amd/common/block/pm/Makefile.inc index 27d9bb5..de1809a 100644 --- a/src/soc/amd/common/block/pm/Makefile.inc +++ b/src/soc/amd/common/block/pm/Makefile.inc @@ -1,5 +1,13 @@ ## SPDX-License-Identifier: GPL-2.0-only + bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c + +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c + smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c diff --git a/src/soc/amd/common/block/pm/reset.c b/src/soc/amd/common/block/pm/reset.c new file mode 100644 index 0000000..52c6334 --- /dev/null +++ b/src/soc/amd/common/block/pm/reset.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <cf9_reset.h> +#include <reset.h> +#include <soc/southbridge.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/reset.h> + +void do_cold_reset(void) +{ + set_resets_to_cold(); + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_warm_reset(void) +{ + /* If warm resets are not supported, executed a cold reset */ + if (!CONFIG(SOC_AMD_SUPPORTS_WARM_RESET)) + do_cold_reset(); /* Does not return */ + + outb(RST_CPU | SYS_RST, RST_CNT); +} + +void do_board_reset(void) +{ + do_cold_reset(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 3 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: merged

1 0

[M] Change in coreboot[master]: soc/amd: Create AMD common reset code
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Jason Glenesk, Raul Rangel, Martin L Roth, Matt DeVillier, Fred Reitberger, Elyes Haouas. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72658 ) Change subject: soc/amd: Create AMD common reset code ...................................................................... Patch Set 2: (1 comment) File src/soc/amd/common/block/pm/Makefile.inc: https://review.coreboot.org/c/coreboot/+/72658/comment/a6adfe4a_66387afc PS2, Line 4: bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c > I originally had this as I did in the original patch: […] i would have put it all in one block as you outlined it above, but either way works -- To view, visit https://review.coreboot.org/c/coreboot/+/72658 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7 Gerrit-Change-Number: 72658 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sat, 04 Feb 2023 03:22:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[master]: amdfwtool: Add entry types required to support glinda & phoenix SOC
by Felix Held (Code Review) 04 Feb '23

04 Feb '23

Attention is currently required from: Bao Zheng. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/69045 ) Change subject: amdfwtool: Add entry types required to support glinda & phoenix SOC ...................................................................... Patch Set 17: (2 comments) File util/amdfwtool/amdfwtool.h: https://review.coreboot.org/c/coreboot/+/69045/comment/90750d36_a4d69221 PS9, Line 71: AMD_FW_TPMLITE = 0x5f, : AMD_FW_PSP_SMUSCS = 0x5f, > Done added a comment in CB:72713 File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/69045/comment/92fc7227_9d763662 PS9, Line 281: else if (strcmp(fw_name, "RIB_FILE") == 0) { : fw_type = AMD_RIB; : subprog = 0; : } > { .type = AMD_RIB, .subprog = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, […] added in CB:72507 -- To view, visit https://review.coreboot.org/c/coreboot/+/69045 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f Gerrit-Change-Number: 69045 Gerrit-PatchSet: 17 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Comment-Date: Sat, 04 Feb 2023 03:17:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: ritul guru <ritul.bits(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023