coreboot-gerrit February 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72051 ) Change subject: mb/google/nissa/var/craask: Modify clkreq to clksrc mapping ...................................................................... mb/google/nissa/var/craask: Modify clkreq to clksrc mapping NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=1,clk_req=2 in mFIT. BUG=b:265720813 TEST=build firmware and veirfy suspend function on DUT. Cq-Depend: chrome-internal:5351299 Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051 Reviewed-by: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craask/gpio.c M src/mainboard/google/brya/variants/craask/overridetree.cb 2 files changed, 29 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Ren Kuo: Looks good to me, but someone else must approve Kangheui Won: Looks good to me, approved Tyler Wang: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index bebc8d2..9ccb57a 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -13,7 +13,7 @@ PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), - /* D7 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + /* D7 : SRCCLKREQ2# ==> SSD_CLKREQ_ODL */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* D11 : EN_PP3300_SSD */ PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 45078c9..5b9bf80 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -502,9 +502,12 @@ probe SD_CARD SD_GL9750S end device ref pcie_rp9 on - # Enable NVMe SSD PCIe 9-12 using clk 2 + # Enable NVMe SSD PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware + # design.Due to inconsistency between PMC firmware and FSP, we need to set + # clk_src to clk_req number, not same as hardware mapping in coreboot.Then + # swap correct setting to clk_src=1,clk_req=2 in mFIT. register "pch_pcie_rp[PCH_RP(9)]" = "{ - .clk_src = 1, + .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" -- To view, visit https://review.coreboot.org/c/coreboot/+/72051 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Gerrit-Change-Number: 72051 Gerrit-PatchSet: 10 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Reka Norman <rekanorman(a)chromium.org> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: Tyler Wang <tyler.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/brya/var/marasov: Turn off camera power during S0ix
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72089 ) Change subject: mb/google/brya/var/marasov: Turn off camera power during S0ix ...................................................................... mb/google/brya/var/marasov: Turn off camera power during S0ix Turn off camera power during S0ix to improve power consumption. BUG=b:265754302 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu(a)pegatron.corp-partner.google.com> Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> --- M src/mainboard/google/brya/variants/marasov/Makefile.inc M src/mainboard/google/brya/variants/marasov/include/variant/gpio.h A src/mainboard/google/brya/variants/marasov/variant.c 3 files changed, 39 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Frank Chu: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/marasov/Makefile.inc b/src/mainboard/google/brya/variants/marasov/Makefile.inc index 4d25f34e..70f6401 100644 --- a/src/mainboard/google/brya/variants/marasov/Makefile.inc +++ b/src/mainboard/google/brya/variants/marasov/Makefile.inc @@ -7,3 +7,5 @@ romstage-y += memory.c ramstage-y += gpio.c + +ramstage-y += variant.c diff --git a/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h index c4fe342..f62197d 100644 --- a/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/marasov/include/variant/gpio.h @@ -5,4 +5,6 @@ #include <baseboard/gpio.h> +#define CAM_PWR GPP_A17 + #endif diff --git a/src/mainboard/google/brya/variants/marasov/variant.c b/src/mainboard/google/brya/variants/marasov/variant.c new file mode 100644 index 0000000..dad8a3c --- /dev/null +++ b/src/mainboard/google/brya/variants/marasov/variant.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <acpi/acpigen.h> +#include <baseboard/variants.h> +#include <variant/gpio.h> + +void variant_generate_s0ix_hook(enum s0ix_entry entry) +{ + /* Add board-specific MS0X entries */ + if (entry == S0IX_ENTRY) + acpigen_soc_clear_tx_gpio(CAM_PWR); + if (entry == S0IX_EXIT) + acpigen_soc_set_tx_gpio(CAM_PWR); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/72089 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a Gerrit-Change-Number: 72089 Gerrit-PatchSet: 11 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ken Lu <ken_lu(a)pegatron.corp-partner.google.com> Gerrit-CC: Kyle Lin <kylelinck(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72694 ) Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed ...................................................................... mb/google/skyrim/var/frostflow: Override SPI flash bus speed Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version of the current phase. BUG=b:260127676 TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed. Observe that the boot time improved by 100 ms compared to 66 MHz SPI flash bus speed. firmware log: SPI fast read speed: 100 MHz At 66 MHz: Total Time: 1,563,384 At 100 MHz: Total Time: 1,462,570 Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/mainboard/google/skyrim/Kconfig 1 file changed, 30 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/skyrim/Kconfig b/src/mainboard/google/skyrim/Kconfig index d945474..55b6ece 100644 --- a/src/mainboard/google/skyrim/Kconfig +++ b/src/mainboard/google/skyrim/Kconfig @@ -157,6 +157,7 @@ config OVERRIDE_EFS_SPI_SPEED_MIN_BOARD hex default 0x5 if BOARD_GOOGLE_SKYRIM + default 0x1 if BOARD_GOOGLE_FROSTFLOW default 0xffffffff help Minimum board version starting which the Override EFS SPI Speed -- To view, visit https://review.coreboot.org/c/coreboot/+/72694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Gerrit-Change-Number: 72694 Gerrit-PatchSet: 3 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chao Gui <chaogui(a)google.com> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: mb/google/skyrim/var/frostflow: Override SPI flash bus speed
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Frank Wu, John Su, Raul Rangel, Jason Nien, Ian Feng, Dtrain Hsu, Jon Murphy, Martin Roth, Karthik Ramasubramanian, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72694 ) Change subject: mb/google/skyrim/var/frostflow: Override SPI flash bus speed ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/72694 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Gerrit-Change-Number: 72694 Gerrit-PatchSet: 2 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chao Gui <chaogui(a)google.com> Gerrit-Attention: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 00:59:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: vc/amd/pi: Fix "No such file or directory"
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/71855 ) Change subject: vc/amd/pi: Fix "No such file or directory" ...................................................................... vc/amd/pi: Fix "No such file or directory" Fix: cc1: error: src/vendorcode/amd/pi/00670F00: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/binaryPI: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Include: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Common: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/CPU/Family: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch: No such file or directory [-Werror=missing-include-dirs] cc1: error: src/vendorcode/amd/pi/00670F00/Proc/Fch/Common: No such file or directory [-Werror=missing-include-dirs] Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71855 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless(a)gmail.com> --- M src/vendorcode/amd/pi/00670F00/Makefile.inc M src/vendorcode/amd/pi/Makefile.inc 2 files changed, 52 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Martin L Roth: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 2ac4987..a7eba30 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -25,30 +25,6 @@ #***************************************************************************** ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) -# AGESA V5 Files - -AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) - -BINARY_PI_INC = -I$(AGESA_ROOT) -BINARY_PI_INC += -I$(AGESA_ROOT)/binaryPI -BINARY_PI_INC += -I$(AGESA_ROOT)/Include -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Common -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU/Family -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch -BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch/Common - -AGESA_INC = -I$(obj) -AGESA_INC += $(BINARY_PI_INC) - -AGESA_INC += -I$(src)/soc/amd/stoneyridge/include -AGESA_INC += -I$(src)/soc/amd/common/block/include - -AGESA_INC += -I$(src)/arch/x86/include -AGESA_INC += -I$(src)/include -AGESA_INC += -I$(src)/commonlib/include -AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include AGESA_CFLAGS += -march=amdfam10 -fno-strict-aliasing -D__LIBAGESA__ diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index d36671a..e62abab 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -30,6 +30,33 @@ subdirs-y += 00670F00 +ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) +# AGESA V5 Files + +AGESA_ROOT = $(top)/$(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) + +BINARY_PI_INC = -I$(AGESA_ROOT) +BINARY_PI_INC += -I$(AGESA_ROOT)/binaryPI +BINARY_PI_INC += -I$(AGESA_ROOT)/Include +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Common +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/CPU/Family +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch +BINARY_PI_INC += -I$(AGESA_ROOT)/Proc/Fch/Common + +AGESA_INC = -I$(obj) +AGESA_INC += $(BINARY_PI_INC) + +AGESA_INC += -I$(src)/soc/amd/stoneyridge/include +AGESA_INC += -I$(src)/soc/amd/common/block/include + +AGESA_INC += -I$(src)/arch/x86/include +AGESA_INC += -I$(src)/include +AGESA_INC += -I$(src)/commonlib/include +AGESA_INC += -I$(VBOOT_SOURCE)/firmware/include +endif + ifeq ($(CONFIG_CPU_AMD_PI_00730F01),y) # AGESA V5 Files -- To view, visit https://review.coreboot.org/c/coreboot/+/71855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Gerrit-Change-Number: 71855 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[master]: vc/amd/pi: Fix "No such file or directory"
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Arthur Heymans, Elyes Haouas, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/71855 ) Change subject: vc/amd/pi: Fix "No such file or directory" ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/71855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I745f4fc421c91c413fe0d3155d3494ed9704eeb6 Gerrit-Change-Number: 71855 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 00:55:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: util/scripts/testsoc: Pass arguments to abuild
by Martin L Roth (Code Review) 05 Feb '23

05 Feb '23

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/72766 ) Change subject: util/scripts/testsoc: Pass arguments to abuild ...................................................................... util/scripts/testsoc: Pass arguments to abuild This allows the user to pass one or more arguments through the testsoc script to abuild. Example: testsoc -K SOC_AMD_CEZANNE -a "--skip_unset BOARD_GOOGLE_NIPPERKIN" Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72766 Reviewed-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M util/scripts/testsoc 1 file changed, 31 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, but someone else must approve Fred Reitberger: Looks good to me, approved diff --git a/util/scripts/testsoc b/util/scripts/testsoc index 81ce2f0..c093042 100755 --- a/util/scripts/testsoc +++ b/util/scripts/testsoc @@ -11,6 +11,9 @@ CPUS=$(nproc || echo "4") NO_CROS=0 +# Extra arguments to pass to abuild +ABUILD_ARGS="" + # Text STYLE variables BOLD="\033[1m" RED='\033[38;5;9m' @@ -26,6 +29,7 @@ Usage: ${PROGNAME} [options] Options: + -a | --abuild "<text>" Specify options to pass to abuild -C | --cpus <num> Specify number of CPUs to use (currently ${CPUS}) -K | --kconfig <CONFIG> Search for Kconfig option -n | --no_cros Don't run chromeos builds @@ -66,7 +70,7 @@ local mblist local mainboards=() - if ! args="$(getopt -l version,help,debug,nocolor,kconfig:,cpus:,no_cros -o C:K:nDhV -- "$@")"; then + if ! args="$(getopt -l version,help,debug,nocolor,kconfig:,cpus:,no_cros,abuild: -o a:C:K:nDhV -- "$@")"; then usage exit 1 fi @@ -75,6 +79,10 @@ while true; do case "$1" in + -a | --abuild) + shift + ABUILD_ARGS=$1 + ;; -C | --cpus) shift CPUS=$1 @@ -155,7 +163,7 @@ rm -rf "./${OUTPUT}" # Non-CrOS build - if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}"; then + if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" ${ABUILD_ARGS}; then _echo_error "Error: Non-cros build of ${board} failed." exit 1 fi @@ -163,7 +171,7 @@ # CrOS build if [[ ${NO_CROS} -eq 0 ]]; then rm -rf "./${OUTPUT}" - if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" --chromeos; then + if ! "${ABUILD}" --exitcode --cpus ${CPUS} --target "${board}" --chromeos ${ABUILD_ARGS}; then _echo_error "Error: CrOS build of ${board} failed." exit 1 fi -- To view, visit https://review.coreboot.org/c/coreboot/+/72766 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic2bc8d656022560ed1eebf6eee0512d3633ebe84 Gerrit-Change-Number: 72766 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[master]: [UNTESTED] soc/amd/stoneyridge: remove LIDS field from global NVS
by Matt DeVillier (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Patrick Georgi, Jason Nien, Matt DeVillier, Martin Roth, Felix Held. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/72182 ) Change subject: [UNTESTED] soc/amd/stoneyridge: remove LIDS field from global NVS ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: tested on google/liara -- To view, visit https://review.coreboot.org/c/coreboot/+/72182 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Gerrit-Change-Number: 72182 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 05 Feb 2023 00:50:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[master]: device/pci_device.c: Add way to limit max bus numbers
by David Hendricks (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Arthur Heymans, Jonathan Zhang, Angel Pons. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59395 ) Change subject: device/pci_device.c: Add way to limit max bus numbers ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/59395 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0582b156df1a5f76119a3687886c4d58f2d3ad6f Gerrit-Change-Number: 59395 Gerrit-PatchSet: 12 Gerrit-Owner: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 05 Feb 2023 00:37:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[master]: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED
by David Hendricks (Code Review) 05 Feb '23

05 Feb '23

Attention is currently required from: Jonathan Zhang, Julius Werner, Angel Pons, Subrata Banik, Kyösti Mälkki, Aaron Durbin, Patrick Rudolph, Lance Zhao, Marc Jones, Nico Huber, Philipp Deppenwiese, Tim Wawrzynczak, Peter Tsung Ho Wu, Ron Minnich. David Hendricks has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52585 ) Change subject: lib: set up specific purpose memory as LB_MEM_SOFT_RESERVED ...................................................................... Patch Set 15: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/52585/comment/231f3739_67dfb5a0 PS14, Line 37: [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=… > Since we're trying to migrate to archive. […] Done Patchset: PS15: > Nico your point is valid. I'm not directly involved ATM, but I know folks that are. […] Thanks, Tim. If you think it's appropriate, would you mind filing a ticket on ticket.coreboot.org or somewhere to track that? -- To view, visit https://review.coreboot.org/c/coreboot/+/52585 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie70795bcb8c97e9dd5fb772adc060e1606f9bab0 Gerrit-Change-Number: 52585 Gerrit-PatchSet: 15 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Reviewer: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Attention: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Attention: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Attention: Lance Zhao Gerrit-Attention: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Deppenwiese <philipp.deppenwiese(a)9elements.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Peter Tsung Ho Wu <tsung(a)amazon.com> Gerrit-Attention: Ron Minnich <rminnich(a)google.com> Gerrit-Comment-Date: Sun, 05 Feb 2023 00:22:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: David Hendricks <david.hendricks(a)gmail.com> Comment-In-Reply-To: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit February 2023